static void omap_hsmmc1_before_set_reg(struct device *dev, int slot,
int power_on, int vdd)
{
u32 reg, prog_io;
struct omap_mmc_platform_data *mmc = dev->platform_data;
if (mmc->slots[0].remux)
mmc->slots[0].remux(dev, slot, power_on);
/*
* Assume we power both OMAP VMMC1 (for CMD, CLK, DAT0..3) and the
* card with Vcc regulator (from twl4030 or whatever). OMAP has both
* 1.8V and 3.0V modes, controlled by the PBIAS register.
*
* In 8-bit modes, OMAP VMMC1A (for DAT4..7) needs a supply, which
* is most naturally TWL VSIM; those pins also use PBIAS.
*
* FIXME handle VMMC1A as needed ...
*/
if (power_on) {
if (cpu_is_omap2430()) {
reg = omap_ctrl_readl(OMAP243X_CONTROL_DEVCONF1);
if ((1 << vdd) >= MMC_VDD_30_31)
reg |= OMAP243X_MMC1_ACTIVE_OVERWRITE;
else
reg &= ~OMAP243X_MMC1_ACTIVE_OVERWRITE;
omap_ctrl_writel(reg, OMAP243X_CONTROL_DEVCONF1);
}
if (mmc->slots[0].internal_clock) {
reg = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
reg |= OMAP2_MMCSDIO1ADPCLKISEL;
omap_ctrl_writel(reg, OMAP2_CONTROL_DEVCONF0);
}
reg = omap_ctrl_readl(control_pbias_offset);
if (cpu_is_omap3630()) {
/* Set MMC I/O to 52Mhz */
prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
prog_io |= OMAP3630_PRG_SDMMC1_SPEEDCTRL;
omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
} else {
reg |= OMAP2_PBIASSPEEDCTRL0;
}
reg &= ~OMAP2_PBIASLITEPWRDNZ0;
omap_ctrl_writel(reg, control_pbias_offset);
} else {
reg = omap_ctrl_readl(control_pbias_offset);
reg &= ~OMAP2_PBIASLITEPWRDNZ0;
omap_ctrl_writel(reg, control_pbias_offset);
}
}
/*
* Configures GPIOs 126, 127 and 129 to 1.8V mode instead of 3.0V
* mode for MMC1 in case bootloader did not configure things.
* Note that if the pins are used for MMC1, pbias-regulator
* manages the IO voltage.
*/
static void __init omap3_gpio126_127_129(void)
{
u32 reg;
reg = omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
reg &= ~OMAP343X_PBIASLITEVMODE1;
reg |= OMAP343X_PBIASLITEPWRDNZ1;
omap_ctrl_writel(reg, OMAP343X_CONTROL_PBIAS_LITE);
if (cpu_is_omap3630()) {
reg = omap_ctrl_readl(OMAP34XX_CONTROL_WKUP_CTRL);
reg |= OMAP36XX_GPIO_IO_PWRDNZ;
omap_ctrl_writel(reg, OMAP34XX_CONTROL_WKUP_CTRL);
}
}
void am35x_musb_reset(void)
{
u32 regval;
/* Reset the musb interface */
regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
regval |= AM35XX_USBOTGSS_SW_RST;
omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
regval &= ~AM35XX_USBOTGSS_SW_RST;
omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
}
static int __init omap_i2c_init(void)
{
/* Disable OMAP 3630 internal pull-ups for I2Ci */
if (cpu_is_omap3630()) {
u32 prog_io;
prog_io = omap_ctrl_readl(OMAP343X_CONTROL_PROG_IO1);
/* Program (bit 19)=1 to disable internal pull-up on I2C1 */
prog_io |= OMAP3630_PRG_I2C1_PULLUPRESX;
/* Program (bit 0)=1 to disable internal pull-up on I2C2 */
prog_io |= OMAP3630_PRG_I2C2_PULLUPRESX;
omap_ctrl_writel(prog_io, OMAP343X_CONTROL_PROG_IO1);
prog_io = omap_ctrl_readl(OMAP36XX_CONTROL_PROG_IO2);
/* Program (bit 7)=1 to disable internal pull-up on I2C3 */
#if (CONFIG_SAMSUNG_REL_HW_REV == 5)
if(get_hw_revision() == 0x06) {
printk("aalto_05_i2c setting\n");
prog_io &= ~OMAP3630_PRG_I2C3_PULLUPRESX;
} else {
prog_io |= OMAP3630_PRG_I2C3_PULLUPRESX;
}
#else
prog_io |= OMAP3630_PRG_I2C3_PULLUPRESX;
#endif
omap_ctrl_writel(prog_io, OMAP36XX_CONTROL_PROG_IO2);
prog_io = omap_ctrl_readl(OMAP36XX_CONTROL_PROG_IO_WKUP1);
/* Program (bit 5)=1 to disable internal pull-up on I2C4(SR) */
prog_io |= OMAP3630_PRG_SR_PULLUPRESX;
omap_ctrl_writel(prog_io, OMAP36XX_CONTROL_PROG_IO_WKUP1);
}
omap_register_i2c_bus(2, 400, NULL, board_i2c_boardinfo1,
ARRAY_SIZE(board_i2c_boardinfo1));
omap_register_i2c_bus(1, 400, NULL, omap_board_i2c_boardinfo,
ARRAY_SIZE(omap_board_i2c_boardinfo));
omap_register_i2c_bus(3, 400, NULL, board_i2c_boardinfo3,
ARRAY_SIZE(board_i2c_boardinfo3));
return 0;
}
static int twl_mmc2_set_power(struct device *dev, int slot, int power_on,
int vdd)
{
int ret = 0;
struct twl_mmc_controller *c = &hsmmc[1];
struct omap_mmc_platform_data *mmc = dev->platform_data;
int mode;
pr_debug("%s %s power_on:%d", __func__, c->name, power_on);
if (power_on) {
/* only MMC2 supports a CLKIN */
if (mmc->slots[0].internal_clock) {
u32 reg;
reg = omap_ctrl_readl(control_devconf1_offset);
reg |= OMAP2_MMCSDIO2ADPCLKISEL;
omap_ctrl_writel(reg, control_devconf1_offset);
}
}
#if 0
mode = power_on ? regulator_enable(c->vcc): regulator_disable(c->vcc);
#else
mode = power_on ? REGULATOR_MODE_NORMAL : REGULATOR_MODE_STANDBY;
ret = regulator_set_mode(c->vcc, mode);
#endif
return ret;
}
static void am3517_evm_ethernet_init(struct emac_platform_data *pdata)
{
unsigned int regval;
pdata->ctrl_reg_offset = AM35XX_EMAC_CNTRL_OFFSET;
pdata->ctrl_mod_reg_offset = AM35XX_EMAC_CNTRL_MOD_OFFSET;
pdata->ctrl_ram_offset = AM35XX_EMAC_CNTRL_RAM_OFFSET;
pdata->ctrl_ram_size = AM35XX_EMAC_CNTRL_RAM_SIZE;
pdata->version = EMAC_VERSION_2;
pdata->hw_ram_addr = AM35XX_EMAC_HW_RAM_ADDR;
pdata->interrupt_enable = am3517_enable_ethernet_int;
pdata->interrupt_disable = am3517_disable_ethernet_int;
am3517_emac_device.dev.platform_data = pdata;
platform_device_register(&am3517_emac_device);
platform_device_register(&am3517_mdio_device);
clk_add_alias(NULL, dev_name(&am3517_mdio_device.dev),
NULL, &am3517_emac_device.dev);
regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
regval = regval & (~(AM35XX_CPGMACSS_SW_RST));
omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
return ;
}
static void __init omap_apollon_init(void)
{
u32 v;
omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC);
omap_board_config = apollon_config;
omap_board_config_size = ARRAY_SIZE(apollon_config);
apollon_init_smc91x();
apollon_led_init();
apollon_flash_init();
apollon_usb_init();
/* REVISIT: where's the correct place */
omap_mux_init_signal("sys_nirq", OMAP_PULL_ENA | OMAP_PULL_UP);
/* LCD PWR_EN */
omap_mux_init_signal("mcbsp2_dr.gpio_11", OMAP_PULL_ENA | OMAP_PULL_UP);
/* Use Interal loop-back in MMC/SDIO Module Input Clock selection */
v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
v |= (1 << 24);
omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
/*
* Make sure the serial ports are muxed on at this point.
* You have to mux them off in device drivers later on
* if not needed.
*/
platform_add_devices(apollon_devices, ARRAY_SIZE(apollon_devices));
omap_serial_init();
}
static void __init mmc_init(void)
{
int i;
u32 reg;
// MMC1
mmc_data[0].slots[0].switch_pin = -EINVAL;
mmc_data[0].slots[0].gpio_wp = -EINVAL;
// MMC2
mmc_data[1].slots[0].switch_pin = -EINVAL;
mmc_data[1].slots[0].gpio_wp = -EINVAL;
/*
* MMC2 has been designed to be used with a level shifter
* but we are NOT using anyone.
*/
reg = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
reg |= OMAP2_MMCSDIO2ADPCLKISEL;
omap_ctrl_writel(reg, OMAP343X_CONTROL_DEVCONF1);
// Wifi AR6103 on MMC2
gpio_init(GPIO_ATH_WARM_RST, 0);
gpio_init(GPIO_ATH_RST_WLAN, 1);
omap_mux_init_gpio(GPIO_ATH_WARM_RST, OMAP_PIN_OUTPUT);
omap_mux_init_gpio(GPIO_ATH_RST_WLAN, OMAP_PIN_OUTPUT);
for (i = 0; i < OMAP34XX_NR_MMC; i++)
hsmmc_data[i] = &mmc_data[i];
board_parrot_init_mmc(hsmmc_data, 2);
}
static void __init omap_apollon_init(void)
{
u32 v;
apollon_led_init();
apollon_flash_init();
apollon_usb_init();
/* REVISIT: where's the correct place */
omap_cfg_reg(W19_24XX_SYS_NIRQ);
/* Use Interal loop-back in MMC/SDIO Module Input Clock selection */
v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
v |= (1 << 24);
omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
/*
* Make sure the serial ports are muxed on at this point.
* You have to mux them off in device drivers later on
* if not needed.
*/
platform_add_devices(apollon_devices, ARRAY_SIZE(apollon_devices));
omap_board_config = apollon_config;
omap_board_config_size = ARRAY_SIZE(apollon_config);
omap_serial_init();
}
static void __init omap_apollon_init(void)
{
u32 v;
omap2420_mux_init(board_mux, OMAP_PACKAGE_ZAC);
apollon_init_smc91x();
apollon_led_init();
apollon_flash_init();
apollon_usb_init();
/* REVISIT: where's the correct place */
omap_mux_init_signal("sys_nirq", OMAP_PULL_ENA | OMAP_PULL_UP);
/* LCD PWR_EN */
omap_mux_init_signal("mcbsp2_dr.gpio_11", OMAP_PULL_ENA | OMAP_PULL_UP);
/* Use Interal loop-back in MMC/SDIO Module Input Clock selection */
v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
v |= (1 << 24);
omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
/*
* Make sure the serial ports are muxed on at this point.
* You have to mux them off in device drivers later on
* if not needed.
*/
apollon_smc91x_resources[1].start = gpio_to_irq(APOLLON_ETHR_GPIO_IRQ);
apollon_smc91x_resources[1].end = gpio_to_irq(APOLLON_ETHR_GPIO_IRQ);
platform_add_devices(apollon_devices, ARRAY_SIZE(apollon_devices));
omap_serial_init();
omap_sdrc_init(NULL, NULL);
omap_display_init(&apollon_dss_data);
}
static void am3517_evm_clear_vpfe_intr(int vdint)
{
unsigned int vpfe_int_clr;
vpfe_int_clr = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
switch (vdint) {
/* VD0 interrrupt */
case INT_35XX_CCDC_VD0_IRQ:
vpfe_int_clr &= ~AM35XX_VPFE_CCDC_VD0_INT_CLR;
vpfe_int_clr |= AM35XX_VPFE_CCDC_VD0_INT_CLR;
break;
/* VD1 interrrupt */
case INT_35XX_CCDC_VD1_IRQ:
vpfe_int_clr &= ~AM35XX_VPFE_CCDC_VD1_INT_CLR;
vpfe_int_clr |= AM35XX_VPFE_CCDC_VD1_INT_CLR;
break;
/* VD2 interrrupt */
case INT_35XX_CCDC_VD2_IRQ:
vpfe_int_clr &= ~AM35XX_VPFE_CCDC_VD2_INT_CLR;
vpfe_int_clr |= AM35XX_VPFE_CCDC_VD2_INT_CLR;
break;
/* Clear all interrrupts */
default:
vpfe_int_clr &= ~(AM35XX_VPFE_CCDC_VD0_INT_CLR |
AM35XX_VPFE_CCDC_VD1_INT_CLR |
AM35XX_VPFE_CCDC_VD2_INT_CLR);
vpfe_int_clr |= (AM35XX_VPFE_CCDC_VD0_INT_CLR |
AM35XX_VPFE_CCDC_VD1_INT_CLR |
AM35XX_VPFE_CCDC_VD2_INT_CLR);
break;
}
omap_ctrl_writel(vpfe_int_clr, AM35XX_CONTROL_LVL_INTR_CLEAR);
vpfe_int_clr = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
}
static int am33xx_suspend_init(void)
{
u32 temp;
gfx_l4ls_clkdm = clkdm_lookup("gfx_l4ls_gfx_clkdm");
l3s_clkdm = clkdm_lookup("l3s_clkdm");
l4fw_clkdm = clkdm_lookup("l4fw_clkdm");
clk_24mhz_clkdm = clkdm_lookup("clk_24mhz_clkdm");
if ((!gfx_l4ls_clkdm) || (!l3s_clkdm) || (!l4fw_clkdm) ||
(!clk_24mhz_clkdm)) {
pr_err("PM: Cannot lookup clockdomains\n");
return -ENODEV;
}
/* Physical resume address to be used by ROM code */
am33xx_pm->ipc.reg0 = (AM33XX_OCMC_END -
am33xx_do_wfi_sz + am33xx_resume_offset + 0x4);
/*
* Save SDRAM config in shadow register.
* When the EMIF gets powered back up, its SDRAM_CONFIG register gets
* loaded from the SECURE_SDRAM_CONFIG register.
*/
temp = readl(am33xx_emif_base + EMIF_SDRAM_CONFIG);
omap_ctrl_writel(temp, AM33XX_CONTROL_SECURE_SDRAM_CONFIG);
return 0;
}
static inline void omap242x_mmc_mux(struct omap_mmc_platform_data
*mmc_controller)
{
if ((mmc_controller->slots[0].switch_pin > 0) && \
(mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
OMAP_PIN_INPUT_PULLUP);
if ((mmc_controller->slots[0].gpio_wp > 0) && \
(mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
OMAP_PIN_INPUT_PULLUP);
omap_mux_init_signal("sdmmc_cmd", 0);
omap_mux_init_signal("sdmmc_clki", 0);
omap_mux_init_signal("sdmmc_clko", 0);
omap_mux_init_signal("sdmmc_dat0", 0);
omap_mux_init_signal("sdmmc_dat_dir0", 0);
omap_mux_init_signal("sdmmc_cmd_dir", 0);
if (mmc_controller->slots[0].caps & MMC_CAP_4_BIT_DATA) {
omap_mux_init_signal("sdmmc_dat1", 0);
omap_mux_init_signal("sdmmc_dat2", 0);
omap_mux_init_signal("sdmmc_dat3", 0);
omap_mux_init_signal("sdmmc_dat_dir1", 0);
omap_mux_init_signal("sdmmc_dat_dir2", 0);
omap_mux_init_signal("sdmmc_dat_dir3", 0);
}
if (mmc_controller->slots[0].internal_clock) {
u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
v |= (1 << 24);
omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
}
}
void rhino_ethernet_init(struct emac_platform_data *pdata)
{
u32 regval, mac_lo, mac_hi;
mac_lo = omap_ctrl_readl(AM35XX_CONTROL_FUSE_EMAC_LSB);
mac_hi = omap_ctrl_readl(AM35XX_CONTROL_FUSE_EMAC_MSB);
pdata->mac_addr[0] = (u_int8_t)((mac_hi & 0xFF0000) >> 16);
pdata->mac_addr[1] = (u_int8_t)((mac_hi & 0xFF00) >> 8);
pdata->mac_addr[2] = (u_int8_t)((mac_hi & 0xFF) >> 0);
pdata->mac_addr[3] = (u_int8_t)((mac_lo & 0xFF0000) >> 16);
pdata->mac_addr[4] = (u_int8_t)((mac_lo & 0xFF00) >> 8);
pdata->mac_addr[5] = (u_int8_t)((mac_lo & 0xFF) >> 0);
pdata->ctrl_reg_offset = AM35XX_EMAC_CNTRL_OFFSET;
pdata->ctrl_mod_reg_offset = AM35XX_EMAC_CNTRL_MOD_OFFSET;
pdata->ctrl_ram_offset = AM35XX_EMAC_CNTRL_RAM_OFFSET;
pdata->ctrl_ram_size = AM35XX_EMAC_CNTRL_RAM_SIZE;
pdata->version = EMAC_VERSION_2;
pdata->hw_ram_addr = AM35XX_EMAC_HW_RAM_ADDR;
pdata->interrupt_enable = am3517_enable_ethernet_int;
pdata->interrupt_disable = am3517_disable_ethernet_int;
am3517_emac_device.dev.platform_data = pdata;
platform_device_register(&am3517_mdio_device);
platform_device_register(&am3517_emac_device);
clk_add_alias(NULL, dev_name(&am3517_mdio_device.dev),
NULL, &am3517_emac_device.dev);
regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
regval = regval & (~(AM35XX_CPGMACSS_SW_RST));
omap_ctrl_writel(regval, AM35XX_CONTROL_IP_SW_RESET);
regval = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
return ;
}
void __init am35xx_emac_init(unsigned long mdio_bus_freq, u8 rmii_en)
{
u32 v;
int err;
am35xx_emac_pdata.rmii_en = rmii_en;
am35xx_emac_mdio_pdata.bus_freq = mdio_bus_freq;
err = platform_device_register(&am35xx_emac_device);
if (err) {
pr_err("AM35x: failed registering EMAC device: %d\n", err);
return;
}
err = platform_device_register(&am35xx_emac_mdio_device);
if (err) {
pr_err("AM35x: failed registering EMAC MDIO device: %d\n", err);
platform_device_unregister(&am35xx_emac_device);
return;
}
v = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
v &= ~AM35XX_CPGMACSS_SW_RST;
omap_ctrl_writel(v, AM35XX_CONTROL_IP_SW_RESET);
omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); /* OCP barrier */
}
static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
int controller_nr)
{
if (cpu_is_omap2420() && controller_nr == 0) {
omap_cfg_reg(H18_24XX_MMC_CMD);
omap_cfg_reg(H15_24XX_MMC_CLKI);
omap_cfg_reg(G19_24XX_MMC_CLKO);
omap_cfg_reg(F20_24XX_MMC_DAT0);
omap_cfg_reg(F19_24XX_MMC_DAT_DIR0);
omap_cfg_reg(G18_24XX_MMC_CMD_DIR);
if (mmc_controller->slots[0].wires == 4) {
omap_cfg_reg(H14_24XX_MMC_DAT1);
omap_cfg_reg(E19_24XX_MMC_DAT2);
omap_cfg_reg(D19_24XX_MMC_DAT3);
omap_cfg_reg(E20_24XX_MMC_DAT_DIR1);
omap_cfg_reg(F18_24XX_MMC_DAT_DIR2);
omap_cfg_reg(E18_24XX_MMC_DAT_DIR3);
}
/*
* Use internal loop-back in MMC/SDIO Module Input Clock
* selection
*/
if (mmc_controller->slots[0].internal_clock) {
u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
v |= (1 << 24);
omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
}
}
}
void am35x_set_mode(u8 musb_mode)
{
u32 devconf2 = omap_ctrl_readl(AM35XX_CONTROL_DEVCONF2);
devconf2 &= ~CONF2_OTGMODE;
switch (musb_mode) {
#ifdef CONFIG_USB_MUSB_HDRC_HCD
case MUSB_HOST: /* Force VBUS valid, ID = 0 */
devconf2 |= CONF2_FORCE_HOST;
break;
#endif
#ifdef CONFIG_USB_GADGET_MUSB_HDRC
case MUSB_PERIPHERAL: /* Force VBUS valid, ID = 1 */
devconf2 |= CONF2_FORCE_DEVICE;
break;
#endif
#ifdef CONFIG_USB_MUSB_OTG
case MUSB_OTG: /* Don't override the VBUS/ID comparators */
devconf2 |= CONF2_NO_OVERRIDE;
break;
#endif
default:
pr_info(KERN_INFO "Unsupported mode %u\n", musb_mode);
}
omap_ctrl_writel(devconf2, AM35XX_CONTROL_DEVCONF2);
}
/**
* omap3_ctrl_init - does static initializations for control module
*
* Initializes system control module. This sets up the sysconfig autoidle,
* and sets up modem and iva2 so that they can be idled properly.
*/
void __init omap3_ctrl_init(void)
{
omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
omap3_ctrl_set_iva_bootmode_idle();
omap3_ctrl_setup_d2d_padconf();
}
static void omap2_usb_devconf_set(u8 port, u32 mask)
{
u32 r;
r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
r |= USBTXWRMODEI(port, mask);
omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
}
static void omap2_usb2_enable_5pinunitll(void)
{
u32 r;
r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
r |= USBTXWRMODEI(2, USB_UNIDIR_TLL) | USBT2TLL5PI;
omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
}
static void __init hsmmc2_internal_input_clk(void)
{
u32 reg;
reg = omap_ctrl_readl(OMAP343X_CONTROL_DEVCONF1);
reg |= OMAP2_MMCSDIO2ADPCLKISEL;
omap_ctrl_writel(reg, OMAP343X_CONTROL_DEVCONF1);
}
static void omap2_usb2_disable_5pinbitll(void)
{
u32 r;
r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
r &= ~(USBTXWRMODEI(2, USB_BIDIR_TLL) | USBT2TLL5PI);
omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0);
}
static void mapphone_gault_init(void)
{
const u32 usim_io_pwrdnz = 0x00000040;
u32 reg;
#ifdef CONFIG_ARM_OF
struct device_node *node;
const void *prop;
#endif
offmode_strategy = OFFMODE_STRATEGY_DISABLED;
#ifdef CONFIG_ARM_OF
/*
* load "offmode strategy" setting
*/
node = of_find_node_by_path(DT_PATH_POWER_MANAGEMENT);
if (node) {
prop = of_get_property(node,
DT_PROP_OFFMODE_STRATEGY, NULL);
if (prop)
offmode_strategy = *(bool *)prop;
else
printk(KERN_ERR"Read property %s error!\n",
DT_PROP_OFFMODE_STRATEGY);
of_node_put(node);
}
#endif
switch (offmode_strategy)
{
case OFFMODE_STRATEGY_DISABLED:
printk(KERN_INFO "offmode strategy is: disabled\n");
break;
case OFFMODE_STRATEGY_INSUSPEND:
printk(KERN_INFO "offmode strategy is: offmode in suspend\n");
break;
case OFFMODE_STRATEGY_IDLETIMER:
printk(KERN_INFO "offmode strategy is: offmode on idle timeout\n");
break;
default:
printk(KERN_INFO "offmode strategy is: undefined\n");
}
/* For G2 SIM Card Block used by MSP GPIOs, these pins
can be configured for 3V or 1.8V */
reg = omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE);
/* SIM Block 1.8V */
reg &= ~OMAP2_PBIASSPEEDCTRL0;
reg &= ~OMAP2_PBIASLITEPWRDNZ0;
omap_ctrl_writel(reg, OMAP343X_CONTROL_PBIAS_LITE);
reg = 0;
/* set the CONTROL_WKUP_CTRL to reflect that the voltage is stabilized
* This is the magic bit given by TI to use SIM Block for MSP test
* and reset
*/
reg = omap_readl((unsigned int)0x48002A5C);
reg |= usim_io_pwrdnz;
omap_writel(reg, (unsigned int)0x48002A5C);
}
/* [email protected] for GPIO_126, 127, 129 */ static void __init hub_mmc1_gpio_init(void) { u32 reg; reg = omap_ctrl_readl(OMAP36XX_CONTROL_WKUP_CTRL); reg |= OMAP36XX_GPIO_IO_PWRDNZ; omap_ctrl_writel(reg, OMAP36XX_CONTROL_WKUP_CTRL); reg = omap_ctrl_readl(OMAP343X_CONTROL_PBIAS_LITE); reg |= OMAP343X_PBIASLITEPWRDNZ1; //power is stable reg &= ~OMAP343X_PBIASLITEVMODE1; //1.8V omap_ctrl_writel(reg, OMAP343X_CONTROL_PBIAS_LITE); printk(KERN_ERR "%s\n", __func__); // mdelay(100); // omap_mux_init_signal("gpio_128", OMAP_PIN_OUTPUT); }
static __init void am3517_evm_mcbsp1_init(void)
{
u32 devconf0;
/* McBSP1 CLKR/FSR signal to be connected to CLKX/FSX pin */
devconf0 = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
devconf0 |= OMAP2_MCBSP1_CLKR_MASK | OMAP2_MCBSP1_FSR_MASK;
omap_ctrl_writel(devconf0, OMAP2_CONTROL_DEVCONF0);
}
static void __init am35xx_emac_reset(void)
{
u32 v;
v = omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET);
v &= ~AM35XX_CPGMACSS_SW_RST;
omap_ctrl_writel(v, AM35XX_CONTROL_IP_SW_RESET);
omap_ctrl_readl(AM35XX_CONTROL_IP_SW_RESET); /* OCP barrier */
}
static void am35xx_disable_emac_int(void)
{
u32 v;
v = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
v |= (AM35XX_CPGMAC_C0_RX_PULSE_CLR | AM35XX_CPGMAC_C0_TX_PULSE_CLR);
omap_ctrl_writel(v, AM35XX_CONTROL_LVL_INTR_CLEAR);
omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR); /* OCP barrier */
}
void am35x_musb_clear_irq(void)
{
u32 regval;
regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
regval |= AM35XX_USBOTGSS_INT_CLR;
omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
}
/**
* omap4_trim_configure() - Handle device trim variance for omap4
*/
int omap4_trim_configure(void)
{
u32 val;
/* if not trimmed, we set force overide, insted of efuse. */
if (bgap_trim_sw_overide) {
/* Fill in recommended values */
val = 0x0f << OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_SHIFT;
val |= OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_MASK;
val |= 0x1 << OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_SHIFT;
val |= OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_MASK;
omap_ctrl_writel(val,
OMAP4_CTRL_MODULE_CORE_LDOSRAM_MPU_VOLTAGE_CTRL);
omap_ctrl_writel(val,
OMAP4_CTRL_MODULE_CORE_LDOSRAM_CORE_VOLTAGE_CTRL);
omap_ctrl_writel(val,
OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL);
}
/* OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_1 is reserved for 4470 */
if (!cpu_is_omap447x()) {
/* For all trimmed and untrimmed write recommended value */
val = 0x10 << OMAP4_AVDAC_TRIM_BYTE0_SHIFT;
val |= 0x01 << OMAP4_AVDAC_TRIM_BYTE1_SHIFT;
val |= 0x4d << OMAP4_AVDAC_TRIM_BYTE2_SHIFT;
val |= 0x1C << OMAP4_AVDAC_TRIM_BYTE3_SHIFT;
omap4_ctrl_pad_writel(val,
OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_1);
}
/* DDR I/O Trim override as per erratum i684 */
if (ddr_io_trim_override) {
omap4_ctrl_pad_writel(OMAP4_LPDDR2_I684_FIX_VALUE,
OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_2);
}
/* Required for DPLL_MPU to lock at 2.4 GHz */
if (dpll_trim_override)
omap_ctrl_writel(0x29,
OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_0);
return 0;
}
static void am3517_disable_ethernet_int(void)
{
u32 regval;
regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
regval = (regval | AM35XX_CPGMAC_C0_RX_PULSE_CLR |
AM35XX_CPGMAC_C0_TX_PULSE_CLR);
omap_ctrl_writel(regval, AM35XX_CONTROL_LVL_INTR_CLEAR);
regval = omap_ctrl_readl(AM35XX_CONTROL_LVL_INTR_CLEAR);
}
