/* dump current cir register contents */ static void cir_dump_regs(struct fintek_dev *fintek) { fintek_config_mode_enable(fintek); fintek_select_logical_dev(fintek, fintek->logical_dev_cir); pr_reg("%s: Dump CIR logical device registers:\n", FINTEK_DRIVER_NAME); pr_reg(" * CR CIR BASE ADDR: 0x%x\n", (fintek_cr_read(fintek, CIR_CR_BASE_ADDR_HI) << 8) | fintek_cr_read(fintek, CIR_CR_BASE_ADDR_LO)); pr_reg(" * CR CIR IRQ NUM: 0x%x\n", fintek_cr_read(fintek, CIR_CR_IRQ_SEL)); fintek_config_mode_disable(fintek); pr_reg("%s: Dump CIR registers:\n", FINTEK_DRIVER_NAME); pr_reg(" * STATUS: 0x%x\n", fintek_cir_reg_read(fintek, CIR_STATUS)); pr_reg(" * CONTROL: 0x%x\n", fintek_cir_reg_read(fintek, CIR_CONTROL)); pr_reg(" * RX_DATA: 0x%x\n", fintek_cir_reg_read(fintek, CIR_RX_DATA)); pr_reg(" * TX_CONTROL: 0x%x\n", fintek_cir_reg_read(fintek, CIR_TX_CONTROL)); pr_reg(" * TX_DATA: 0x%x\n", fintek_cir_reg_read(fintek, CIR_TX_DATA)); }
/* dump current cir wake register contents */ static void cir_wake_dump_regs(struct nvt_dev *nvt) { u8 i, fifo_len; nvt_efm_enable(nvt); nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE); pr_reg("%s: Dump CIR WAKE logical device registers:\n", NVT_DRIVER_NAME); pr_reg(" * CR CIR WAKE ACTIVE : 0x%x\n", nvt_cr_read(nvt, CR_LOGICAL_DEV_EN)); pr_reg(" * CR CIR WAKE BASE ADDR: 0x%x\n", (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) | nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO)); pr_reg(" * CR CIR WAKE IRQ NUM: 0x%x\n", nvt_cr_read(nvt, CR_CIR_IRQ_RSRC)); nvt_efm_disable(nvt); pr_reg("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME); pr_reg(" * IRCON: 0x%x\n", nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON)); pr_reg(" * IRSTS: 0x%x\n", nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS)); pr_reg(" * IREN: 0x%x\n", nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN)); pr_reg(" * FIFO CMP DEEP: 0x%x\n", nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP)); pr_reg(" * FIFO CMP TOL: 0x%x\n", nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL)); pr_reg(" * FIFO COUNT: 0x%x\n", nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT)); pr_reg(" * SLCH: 0x%x\n", nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH)); pr_reg(" * SLCL: 0x%x\n", nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL)); pr_reg(" * FIFOCON: 0x%x\n", nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON)); pr_reg(" * SRXFSTS: 0x%x\n", nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS)); pr_reg(" * SAMPLE RX FIFO: 0x%x\n", nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO)); pr_reg(" * WR FIFO DATA: 0x%x\n", nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA)); pr_reg(" * RD FIFO ONLY: 0x%x\n", nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY)); pr_reg(" * RD FIFO ONLY IDX: 0x%x\n", nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)); pr_reg(" * FIFO IGNORE: 0x%x\n", nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE)); pr_reg(" * IRFSM: 0x%x\n", nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM)); fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT); pr_reg("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len); pr_reg("* Contents = "); for (i = 0; i < fifo_len; i++) printk(KERN_CONT "%02x ", nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY)); printk(KERN_CONT "\n"); }
/* dump current cir register contents */ static void cir_dump_regs(struct nvt_dev *nvt) { nvt_efm_enable(nvt); nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); pr_reg("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME); pr_reg(" * CR CIR ACTIVE : 0x%x\n", nvt_cr_read(nvt, CR_LOGICAL_DEV_EN)); pr_reg(" * CR CIR BASE ADDR: 0x%x\n", (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) | nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO)); pr_reg(" * CR CIR IRQ NUM: 0x%x\n", nvt_cr_read(nvt, CR_CIR_IRQ_RSRC)); nvt_efm_disable(nvt); pr_reg("%s: Dump CIR registers:\n", NVT_DRIVER_NAME); pr_reg(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON)); pr_reg(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS)); pr_reg(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN)); pr_reg(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT)); pr_reg(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP)); pr_reg(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC)); pr_reg(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH)); pr_reg(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL)); pr_reg(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON)); pr_reg(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS)); pr_reg(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO)); pr_reg(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT)); pr_reg(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO)); pr_reg(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH)); pr_reg(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL)); pr_reg(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM)); }
static ssize_t omap2_iommu_dump_ctx(struct iommu *obj, char *buf, ssize_t len) { char *p = buf; pr_reg(REVISION); pr_reg(SYSCONFIG); pr_reg(SYSSTATUS); pr_reg(IRQSTATUS); pr_reg(IRQENABLE); pr_reg(WALKING_ST); pr_reg(CNTL); pr_reg(FAULT_AD); pr_reg(TTB); pr_reg(LOCK); pr_reg(LD_TLB); pr_reg(CAM); pr_reg(RAM); pr_reg(GFLUSH); pr_reg(FLUSH_ENTRY); pr_reg(READ_CAM); pr_reg(READ_RAM); pr_reg(EMU_FAULT_AD); out: return p - buf; }
static void print_phy_regs(void) { pr_info("----- EHCI PHY REG DUMP -----\n"); pr_reg("USBHOST_PHY_CONTROL", readl(EXYNOS5_USBHOST_PHY_CONTROL)); pr_reg("HOSTPHYCTRL0", readl(EXYNOS5_PHY_HOST_CTRL0)); pr_reg("HOSTPHYTUNE0", readl(EXYNOS5_PHY_HOST_TUNE0)); pr_reg("HSICPHYCTRL1", readl(EXYNOS5_PHY_HSIC_CTRL1)); pr_reg("HSICPHYTUNE1", readl(EXYNOS5_PHY_HSIC_TUNE1)); pr_reg("HSICPHYCTRL2", readl(EXYNOS5_PHY_HSIC_CTRL2)); pr_reg("HSICPHYTUNE2", readl(EXYNOS5_PHY_HSIC_TUNE2)); pr_reg("HOSTEHCICTRL", readl(EXYNOS5_PHY_HOST_EHCICTRL)); pr_reg("OHCICTRL", readl(EXYNOS5_PHY_HOST_OHCICTRL)); pr_reg("USBOTG_SYS", readl(EXYNOS5_PHY_OTG_SYS)); pr_reg("USBOTG_TUNE", readl(EXYNOS5_PHY_OTG_TUNE)); pr_info("-----------------------------\n"); }
static void print_ehci_regs(struct mif_ehci_regs *base) { pr_info("------- EHCI reg dump -------\n"); pr_reg("HCCPBASE", base->caps_hc_capbase); pr_reg("HCSPARAMS", base->caps_hcs_params); pr_reg("HCCPARAMS", base->caps_hcc_params); pr_reg("USBCMD", base->regs.command); pr_reg("USBSTS", base->regs.status); pr_reg("USBINTR", base->regs.intr_enable); pr_reg("FRINDEX", base->regs.frame_index); pr_reg("CTRLDSSEGMENT", base->regs.segment); pr_reg("PERIODICLISTBASE", base->regs.frame_list); pr_reg("ASYNCLISTADDR", base->regs.async_next); pr_reg("CONFIGFLAG", base->regs.configured_flag); pr_reg("PORT0 Status/Control", base->port_usb); pr_reg("PORT1 Status/Control", base->port_hsic0); pr_reg("PORT2 Status/Control", base->port_hsic1); pr_reg("INSNREG00", base->insnreg00); pr_reg("INSNREG01", base->insnreg01); pr_reg("INSNREG02", base->insnreg02); pr_reg("INSNREG03", base->insnreg03); pr_reg("INSNREG04", base->insnreg04); pr_reg("INSNREG05", base->insnreg05); pr_reg("INSNREG06", base->insnreg06); pr_reg("INSNREG07", base->insnreg07); pr_info("-----------------------------\n"); }