static int tegra30_ahub_resume(struct device *dev) { int ret; ret = pm_runtime_get_sync(dev); if (ret < 0) return ret; ret = regcache_sync(ahub->regmap_ahub); ret |= regcache_sync(ahub->regmap_apbif); pm_runtime_put(dev); return ret; }
static int wm8776_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { struct wm8776_priv *wm8776 = snd_soc_codec_get_drvdata(codec); switch (level) { case SND_SOC_BIAS_ON: break; case SND_SOC_BIAS_PREPARE: break; case SND_SOC_BIAS_STANDBY: if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) { regcache_sync(wm8776->regmap); /* Disable the global powerdown; DAPM does the rest */ snd_soc_update_bits(codec, WM8776_PWRDOWN, 1, 0); } break; case SND_SOC_BIAS_OFF: snd_soc_update_bits(codec, WM8776_PWRDOWN, 1, 1); break; } return 0; }
static int max97236_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { struct max97236_priv *max97236 = snd_soc_codec_get_drvdata(codec); switch (level) { case SND_SOC_BIAS_ON: break; case SND_SOC_BIAS_PREPARE: break; case SND_SOC_BIAS_STANDBY: if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { regcache_cache_only(max97236->regmap, false); regcache_sync(max97236->regmap); } break; case SND_SOC_BIAS_OFF: break; } codec->dapm.bias_level = level; return 0; }
static int max97236_pm_resume(struct device *dev) { struct max97236_priv *max97236 = dev_get_drvdata(dev); struct snd_soc_codec *codec = max97236->codec; struct snd_soc_card *card = codec->card; struct snd_soc_dai_link *dai_link = card->dai_link; int i = 0; for (i = 0; i < card->num_links; i++) if (card->dai_link[i].ignore_suspend) return 0; if (pm_delay_enable) { pr_info("%s: enter, setting extclk to %d\n", __func__, extclk_freq); msleep(3000); } cancel_delayed_work(&max97236->jack_work); regcache_cache_only(max97236->regmap, false); /* max97236_reset(max97236); */ regcache_sync(max97236->regmap); max97236_set_clk_dividers(max97236); max97236->jack_state = M97236_JACK_STATE_NONE; if (test_jack_presence(max97236, 10)) snd_soc_jack_report(max97236->jack, max97236->jack_state, 0x7E00); return 0; }
static int __maybe_unused cs35l34_runtime_resume(struct device *dev) { struct cs35l34_private *cs35l34 = dev_get_drvdata(dev); int ret; ret = regulator_bulk_enable(cs35l34->num_core_supplies, cs35l34->core_supplies); if (ret != 0) { dev_err(dev, "Failed to enable core supplies: %d\n", ret); return ret; } regcache_cache_only(cs35l34->regmap, false); gpiod_set_value_cansleep(cs35l34->reset_gpio, 1); msleep(CS35L34_START_DELAY); ret = regcache_sync(cs35l34->regmap); if (ret != 0) { dev_err(dev, "Failed to restore register cache\n"); goto err; } return 0; err: regcache_cache_only(cs35l34->regmap, true); regulator_bulk_disable(cs35l34->num_core_supplies, cs35l34->core_supplies); return ret; }
static int si47xx_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { #if 0 struct si47xx_priv *si47xx = snd_soc_codec_get_drvdata(codec); u16 reg; switch (level) { case SND_SOC_BIAS_ON: case SND_SOC_BIAS_PREPARE: case SND_SOC_BIAS_STANDBY: if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { /* Power everything up... */ reg = snd_soc_read(codec, SI47XX_DACCTL); snd_soc_write(codec, SI47XX_DACCTL, reg & ~0x4); /* ..then sync in the register cache. */ regcache_sync(si47xx->regmap); } break; case SND_SOC_BIAS_OFF: reg = snd_soc_read(codec, SI47XX_DACCTL); snd_soc_write(codec, SI47XX_DACCTL, reg | 0x4); break; } codec->dapm.bias_level = level; #endif return 0; }
static int arizona_runtime_resume(struct device *dev) { struct arizona *arizona = dev_get_drvdata(dev); int ret; dev_dbg(arizona->dev, "Leaving AoD mode\n"); ret = regulator_enable(arizona->dcvdd); if (ret != 0) { dev_err(arizona->dev, "Failed to enable DCVDD: %d\n", ret); return ret; } regcache_cache_only(arizona->regmap, false); ret = arizona_wait_for_boot(arizona); if (ret != 0) { regulator_disable(arizona->dcvdd); return ret; } regcache_sync(arizona->regmap); return 0; }
static int fsl_dcu_drm_pm_resume(struct device *dev) { struct fsl_dcu_drm_device *fsl_dev = dev_get_drvdata(dev); int ret; if (!fsl_dev) return 0; ret = clk_enable(fsl_dev->clk); if (ret < 0) { dev_err(dev, "failed to enable dcu clk\n"); clk_unprepare(fsl_dev->clk); return ret; } ret = clk_prepare(fsl_dev->clk); if (ret < 0) { dev_err(dev, "failed to prepare dcu clk\n"); return ret; } drm_kms_helper_poll_enable(fsl_dev->drm); regcache_cache_only(fsl_dev->regmap, false); regcache_sync(fsl_dev->regmap); return 0; }
static int es8328_resume(struct snd_soc_codec *codec) { struct regmap *regmap = dev_get_regmap(codec->dev, NULL); struct es8328_priv *es8328; int ret; es8328 = snd_soc_codec_get_drvdata(codec); ret = clk_prepare_enable(es8328->clk); if (ret) { dev_err(codec->dev, "unable to enable clock\n"); return ret; } ret = regulator_bulk_enable(ARRAY_SIZE(es8328->supplies), es8328->supplies); if (ret) { dev_err(codec->dev, "unable to enable regulators\n"); return ret; } regcache_mark_dirty(regmap); ret = regcache_sync(regmap); if (ret) { dev_err(codec->dev, "unable to sync regcache\n"); return ret; } return 0; }
static int wm8711_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { struct wm8711_priv *wm8711 = snd_soc_codec_get_drvdata(codec); u16 reg = snd_soc_read(codec, WM8711_PWR) & 0xff7f; switch (level) { case SND_SOC_BIAS_ON: snd_soc_write(codec, WM8711_PWR, reg); break; case SND_SOC_BIAS_PREPARE: break; case SND_SOC_BIAS_STANDBY: if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) regcache_sync(wm8711->regmap); snd_soc_write(codec, WM8711_PWR, reg | 0x0040); break; case SND_SOC_BIAS_OFF: snd_soc_write(codec, WM8711_ACTIVE, 0x0); snd_soc_write(codec, WM8711_PWR, 0xffff); break; } codec->dapm.bias_level = level; return 0; }
static int ak4613_resume(struct snd_soc_component *component) { struct regmap *regmap = dev_get_regmap(component->dev, NULL); regcache_cache_only(regmap, false); return regcache_sync(regmap); }
static int cs42l73_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { struct cs42l73_private *cs42l73 = snd_soc_codec_get_drvdata(codec); switch (level) { case SND_SOC_BIAS_ON: snd_soc_update_bits(codec, CS42L73_DMMCC, MCLKDIS, 0); snd_soc_update_bits(codec, CS42L73_PWRCTL1, PDN, 0); break; case SND_SOC_BIAS_PREPARE: break; case SND_SOC_BIAS_STANDBY: if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { regcache_cache_only(cs42l73->regmap, false); regcache_sync(cs42l73->regmap); } snd_soc_update_bits(codec, CS42L73_PWRCTL1, PDN, 1); break; case SND_SOC_BIAS_OFF: snd_soc_update_bits(codec, CS42L73_PWRCTL1, PDN, 1); snd_soc_update_bits(codec, CS42L73_DMMCC, MCLKDIS, 1); break; } codec->dapm.bias_level = level; return 0; }
static int adau1761_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { struct adau *adau = snd_soc_codec_get_drvdata(codec); switch (level) { case SND_SOC_BIAS_ON: break; case SND_SOC_BIAS_PREPARE: break; case SND_SOC_BIAS_STANDBY: regcache_cache_only(adau->regmap, false); regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL, ADAU17X1_CLOCK_CONTROL_SYSCLK_EN, ADAU17X1_CLOCK_CONTROL_SYSCLK_EN); if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) regcache_sync(adau->regmap); break; case SND_SOC_BIAS_OFF: regmap_update_bits(adau->regmap, ADAU17X1_CLOCK_CONTROL, ADAU17X1_CLOCK_CONTROL_SYSCLK_EN, 0); regcache_cache_only(adau->regmap, true); break; } return 0; }
static int mt8183_afe_runtime_resume(struct device *dev) { struct mtk_base_afe *afe = dev_get_drvdata(dev); struct mt8183_afe_private *afe_priv = afe->platform_priv; int ret; ret = mt8183_afe_enable_clock(afe); if (ret) return ret; if (!afe->regmap || afe_priv->pm_runtime_bypass_reg_ctl) goto skip_regmap; regcache_cache_only(afe->regmap, false); regcache_sync(afe->regmap); /* enable audio sys DCM for power saving */ regmap_update_bits(afe->regmap, AUDIO_TOP_CON0, 0x1 << 29, 0x1 << 29); /* force cpu use 8_24 format when writing 32bit data */ regmap_update_bits(afe->regmap, AFE_MEMIF_MSB, CPU_HD_ALIGN_MASK_SFT, 0 << CPU_HD_ALIGN_SFT); /* set all output port to 24bit */ regmap_write(afe->regmap, AFE_CONN_24BIT, 0xffffffff); regmap_write(afe->regmap, AFE_CONN_24BIT_1, 0xffffffff); /* enable AFE */ regmap_update_bits(afe->regmap, AFE_DAC_CON0, 0x1, 0x1); skip_regmap: return 0; }
static int ml26124_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { struct ml26124_priv *priv = snd_soc_codec_get_drvdata(codec); switch (level) { case SND_SOC_BIAS_ON: snd_soc_update_bits(codec, ML26124_PW_SPAMP_PW_MNG, ML26124_R26_MASK, ML26124_BLT_PREAMP_ON); msleep(100); snd_soc_update_bits(codec, ML26124_PW_SPAMP_PW_MNG, ML26124_R26_MASK, ML26124_MICBEN_ON | ML26124_BLT_ALL_ON); break; case SND_SOC_BIAS_PREPARE: break; case SND_SOC_BIAS_STANDBY: /* VMID ON */ if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { snd_soc_update_bits(codec, ML26124_PW_REF_PW_MNG, ML26124_VMID, ML26124_VMID); msleep(500); regcache_sync(priv->regmap); } break; case SND_SOC_BIAS_OFF: /* VMID OFF */ snd_soc_update_bits(codec, ML26124_PW_REF_PW_MNG, ML26124_VMID, 0); break; } codec->dapm.bias_level = level; return 0; }
static int ak4613_resume(struct snd_soc_codec *codec) { struct regmap *regmap = dev_get_regmap(codec->dev, NULL); regcache_mark_dirty(regmap); return regcache_sync(regmap); }
static int tas6424_power_on(struct snd_soc_codec *codec) { struct tas6424_data *tas6424 = snd_soc_codec_get_drvdata(codec); int ret; ret = regulator_bulk_enable(ARRAY_SIZE(tas6424->supplies), tas6424->supplies); if (ret < 0) { dev_err(codec->dev, "failed to enable supplies: %d\n", ret); return ret; } regcache_cache_only(tas6424->regmap, false); ret = regcache_sync(tas6424->regmap); if (ret < 0) { dev_err(codec->dev, "failed to sync regcache: %d\n", ret); return ret; } snd_soc_write(codec, TAS6424_CH_STATE_CTRL, TAS6424_ALL_STATE_MUTE); /* any time we come out of HIZ, the output channels automatically run DC * load diagnostics, wait here until this completes */ msleep(230); return 0; }
static int cs42l52_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { struct cs42l52_private *cs42l52 = snd_soc_codec_get_drvdata(codec); switch (level) { case SND_SOC_BIAS_ON: break; case SND_SOC_BIAS_PREPARE: snd_soc_update_bits(codec, CS42L52_PWRCTL1, CS42L52_PWRCTL1_PDN_CODEC, 0); break; case SND_SOC_BIAS_STANDBY: if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) { regcache_cache_only(cs42l52->regmap, false); regcache_sync(cs42l52->regmap); } snd_soc_write(codec, CS42L52_PWRCTL1, CS42L52_PWRCTL1_PDN_ALL); break; case SND_SOC_BIAS_OFF: snd_soc_write(codec, CS42L52_PWRCTL1, CS42L52_PWRCTL1_PDN_ALL); regcache_cache_only(cs42l52->regmap, true); break; } codec->dapm.bias_level = level; return 0; }
static int sun8i_codec_runtime_resume(struct device *dev) { struct sun8i_codec *scodec = dev_get_drvdata(dev); int ret; ret = clk_prepare_enable(scodec->clk_module); if (ret) { dev_err(dev, "Failed to enable the module clock\n"); return ret; } ret = clk_prepare_enable(scodec->clk_bus); if (ret) { dev_err(dev, "Failed to enable the bus clock\n"); goto err_disable_modclk; } regcache_cache_only(scodec->regmap, false); ret = regcache_sync(scodec->regmap); if (ret) { dev_err(dev, "Failed to sync regmap cache\n"); goto err_disable_clk; } return 0; err_disable_clk: clk_disable_unprepare(scodec->clk_bus); err_disable_modclk: clk_disable_unprepare(scodec->clk_module); return ret; }
static int s2801x_sys_resume(struct device *dev) { dev_dbg(dev, "(*) %s\n", __func__); /* Audio mixer Alive Configuration */ __raw_writel(S2801_ALIVE_ON, EXYNOS_PMU_AUD_PATH_CFG); /* Audio mixer unreset */ if (s2801x->sysreg_reset == NULL) { dev_err(dev, "sysreg_reset registers not set\n"); return -ENXIO; } writel(S2801_SW_UN_RESET, s2801x->sysreg_reset); /*write Audio mixer i2c address */ if (s2801x->sysreg_i2c_id == NULL) { dev_err(dev, "sysreg_i2c_id registers not set\n"); return -ENXIO; } writel(s2801x->i2c_addr, s2801x->sysreg_i2c_id); /* Reset the codec */ s2801x_reset_sys_data(); /* set ap path by defaut*/ s2801x_init_mixer(); regcache_cache_only(s2801x->regmap, false); regcache_sync(s2801x->regmap); return 0; }
static int sta529_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { struct sta529 *sta529 = snd_soc_codec_get_drvdata(codec); switch (level) { case SND_SOC_BIAS_ON: case SND_SOC_BIAS_PREPARE: snd_soc_update_bits(codec, STA529_FFXCFG0, POWER_CNTLMSAK, POWER_UP); snd_soc_update_bits(codec, STA529_MISC, FFX_CLK_MSK, FFX_CLK_ENB); break; case SND_SOC_BIAS_STANDBY: if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) regcache_sync(sta529->regmap); snd_soc_update_bits(codec, STA529_FFXCFG0, POWER_CNTLMSAK, POWER_STDBY); /* Making FFX output to zero */ snd_soc_update_bits(codec, STA529_FFXCFG0, FFX_MASK, FFX_OFF); snd_soc_update_bits(codec, STA529_MISC, FFX_CLK_MSK, FFX_CLK_DIS); break; case SND_SOC_BIAS_OFF: break; } return 0; }
static int tas5086_soc_resume(struct snd_soc_codec *codec) { struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec); /* Restore codec state */ return regcache_sync(priv->regmap); }
static int wm8711_set_bias_level(struct snd_soc_component *component, enum snd_soc_bias_level level) { struct wm8711_priv *wm8711 = snd_soc_component_get_drvdata(component); u16 reg = snd_soc_component_read32(component, WM8711_PWR) & 0xff7f; switch (level) { case SND_SOC_BIAS_ON: snd_soc_component_write(component, WM8711_PWR, reg); break; case SND_SOC_BIAS_PREPARE: break; case SND_SOC_BIAS_STANDBY: if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) regcache_sync(wm8711->regmap); snd_soc_component_write(component, WM8711_PWR, reg | 0x0040); break; case SND_SOC_BIAS_OFF: snd_soc_component_write(component, WM8711_ACTIVE, 0x0); snd_soc_component_write(component, WM8711_PWR, 0xffff); break; } return 0; }
static int stm32_i2s_resume(struct device *dev) { struct stm32_i2s_data *i2s = dev_get_drvdata(dev); regcache_cache_only(i2s->regmap, false); return regcache_sync(i2s->regmap); }
static int uda134x_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { struct uda134x_priv *uda134x = snd_soc_codec_get_drvdata(codec); struct uda134x_platform_data *pd = uda134x->pd; pr_debug("%s bias level %d\n", __func__, level); switch (level) { case SND_SOC_BIAS_ON: break; case SND_SOC_BIAS_PREPARE: /* power on */ if (pd->power) { pd->power(1); regcache_sync(uda134x->regmap); } break; case SND_SOC_BIAS_STANDBY: break; case SND_SOC_BIAS_OFF: /* power off */ if (pd->power) { pd->power(0); regcache_mark_dirty(uda134x->regmap); } break; } return 0; }
static int aic31xx_power_on(struct snd_soc_codec *codec) { struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec); int ret = 0; ret = regulator_bulk_enable(ARRAY_SIZE(aic31xx->supplies), aic31xx->supplies); if (ret) return ret; if (gpio_is_valid(aic31xx->pdata.gpio_reset)) { gpio_set_value(aic31xx->pdata.gpio_reset, 1); udelay(100); } regcache_cache_only(aic31xx->regmap, false); ret = regcache_sync(aic31xx->regmap); if (ret != 0) { dev_err(codec->dev, "Failed to restore cache: %d\n", ret); regcache_cache_only(aic31xx->regmap, true); regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies), aic31xx->supplies); return ret; } return 0; }
static int cs4271_soc_resume(struct snd_soc_codec *codec) { int ret; struct cs4271_private *cs4271 = snd_soc_codec_get_drvdata(codec); ret = regulator_bulk_enable(ARRAY_SIZE(cs4271->supplies), cs4271->supplies); if (ret < 0) { dev_err(codec->dev, "Failed to enable regulators: %d\n", ret); return ret; } /* Do a proper reset after power up */ cs4271_reset(codec); /* Restore codec state */ ret = regcache_sync(cs4271->regmap); if (ret < 0) return ret; /* then disable the power-down bit */ ret = regmap_update_bits(cs4271->regmap, CS4271_MODE2, CS4271_MODE2_PDN, 0); if (ret < 0) return ret; return 0; }
static int wm8728_set_bias_level(struct snd_soc_codec *codec, enum snd_soc_bias_level level) { struct wm8728_priv *wm8728 = snd_soc_codec_get_drvdata(codec); u16 reg; switch (level) { case SND_SOC_BIAS_ON: case SND_SOC_BIAS_PREPARE: case SND_SOC_BIAS_STANDBY: if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) { /* Power everything up... */ reg = snd_soc_read(codec, WM8728_DACCTL); snd_soc_write(codec, WM8728_DACCTL, reg & ~0x4); /* ..then sync in the register cache. */ regcache_sync(wm8728->regmap); } break; case SND_SOC_BIAS_OFF: reg = snd_soc_read(codec, WM8728_DACCTL); snd_soc_write(codec, WM8728_DACCTL, reg | 0x4); break; } return 0; }
static int ssm2602_resume(struct snd_soc_codec *codec) { struct ssm2602_priv *ssm2602 = snd_soc_codec_get_drvdata(codec); regcache_sync(ssm2602->regmap); return 0; }
static int rt5616_resume(struct snd_soc_codec *codec) { struct rt5616_priv *rt5616 = snd_soc_codec_get_drvdata(codec); regcache_cache_only(rt5616->regmap, false); regcache_sync(rt5616->regmap); return 0; }