static int lp873x_probe(struct i2c_client *client, const struct i2c_device_id *ids) { struct lp873x *lp873; int ret; unsigned int otpid; lp873 = devm_kzalloc(&client->dev, sizeof(*lp873), GFP_KERNEL); if (!lp873) return -ENOMEM; lp873->dev = &client->dev; lp873->regmap = devm_regmap_init_i2c(client, &lp873x_regmap_config); if (IS_ERR(lp873->regmap)) { ret = PTR_ERR(lp873->regmap); dev_err(lp873->dev, "Failed to initialize register map: %d\n", ret); return ret; } ret = regmap_read(lp873->regmap, LP873X_REG_OTP_REV, &otpid); if (ret) { dev_err(lp873->dev, "Failed to read OTP ID\n"); return ret; } lp873->rev = otpid & LP873X_OTP_REV_OTP_ID; i2c_set_clientdata(client, lp873); ret = mfd_add_devices(lp873->dev, PLATFORM_DEVID_AUTO, lp873x_cells, ARRAY_SIZE(lp873x_cells), NULL, 0, NULL); return ret; }
/* flash */ static void lm3639_flash_brightness_set(struct led_classdev *cdev, enum led_brightness brightness) { int ret; unsigned int reg_val; struct lm3639_chip_data *pchip; pchip = container_of(cdev, struct lm3639_chip_data, cdev_flash); ret = regmap_read(pchip->regmap, REG_FLAG, ®_val); if (ret < 0) goto out; if (reg_val != 0) dev_info(pchip->dev, "last flag is 0x%x\n", reg_val); /* torch off before flash control */ ret = regmap_update_bits(pchip->regmap, REG_ENABLE, 0x06, 0x00); if (ret < 0) goto out; /* brightness 0 means off state */ if (!brightness) return; ret = regmap_update_bits(pchip->regmap, REG_FL_CONF_1, 0x0F, brightness - 1); if (ret < 0) goto out; ret = regmap_update_bits(pchip->regmap, REG_ENABLE, 0x06, 0x06); if (ret < 0) goto out; return; out: dev_err(pchip->dev, "i2c failed to access register\n"); }
static int max8973_get_current_limit(struct regulator_dev *rdev) { struct max8973_chip *max = rdev_get_drvdata(rdev); unsigned int control2; int ret; ret = regmap_read(max->regmap, MAX8973_CONTROL2, &control2); if (ret < 0) { dev_err(max->dev, "register %d read failed: %d\n", MAX8973_CONTROL2, ret); return ret; } switch (control2 & MAX8973_CKKADV_TRIP_MASK) { case MAX8973_CKKADV_TRIP_DISABLE: return 15000000; case MAX8973_CKKADV_TRIP_150mV_PER_US: return 12000000; case MAX8973_CKKADV_TRIP_75mV_PER_US: return 9000000; default: break; } return 9000000; }
static int arizona_poll_reg(struct arizona *arizona, int timeout, unsigned int reg, unsigned int mask, unsigned int target) { unsigned int val = 0; int ret, i; for (i = 0; i < timeout; i++) { ret = regmap_read(arizona->regmap, reg, &val); if (ret != 0) { dev_err(arizona->dev, "Failed to read reg %u: %d\n", reg, ret); continue; } if ((val & mask) == target) return 0; msleep(1); } dev_err(arizona->dev, "Polling reg %u timed out: %x\n", reg, val); return -ETIMEDOUT; }
static int rockchip_pmu_set_idle_request(struct rockchip_pm_domain *pd, bool idle) { const struct rockchip_domain_info *pd_info = pd->info; struct rockchip_pmu *pmu = pd->pmu; unsigned int val; if (pd_info->req_mask == 0) return 0; regmap_update_bits(pmu->regmap, pmu->info->req_offset, pd_info->req_mask, idle ? -1U : 0); dsb(sy); do { regmap_read(pmu->regmap, pmu->info->ack_offset, &val); } while ((val & pd_info->ack_mask) != (idle ? pd_info->ack_mask : 0)); while (rockchip_pmu_domain_is_idle(pd) != idle) cpu_relax(); return 0; }
static int __mtk_rtc_read_time(struct mt6397_rtc *rtc, struct rtc_time *tm, int *sec) { int ret; u16 data[RTC_OFFSET_COUNT]; mutex_lock(&rtc->lock); ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_TC_SEC, data, RTC_OFFSET_COUNT); if (ret < 0) goto exit; tm->tm_sec = data[RTC_OFFSET_SEC]; tm->tm_min = data[RTC_OFFSET_MIN]; tm->tm_hour = data[RTC_OFFSET_HOUR]; tm->tm_mday = data[RTC_OFFSET_DOM]; tm->tm_mon = data[RTC_OFFSET_MTH]; tm->tm_year = data[RTC_OFFSET_YEAR]; ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_TC_SEC, sec); exit: mutex_unlock(&rtc->lock); return ret; }
static int ncp6335d_restore_working_reg(struct device_node *node, struct ncp6335d_info *dd) { int ret; unsigned int val; /* Restore register from back up register */ ret = regmap_read(dd->regmap, dd->vsel_backup_reg, &val); if (ret < 0) { dev_err(dd->dev, "Failed to get backup data from reg %d, ret = %d\n", dd->vsel_backup_reg, ret); return ret; } ret = regmap_update_bits(dd->regmap, dd->vsel_reg, NCP6335D_VOUT_SEL_MASK, val); if (ret < 0) { dev_err(dd->dev, "Failed to update working reg %d, ret = %d\n", dd->vsel_reg, ret); return ret; } return ret; }
static int lm363x_regulator_enable_time(struct regulator_dev *rdev) { enum lm363x_regulator_id id = rdev_get_id(rdev); u8 val, addr, mask; switch (id) { case LM3631_LDO_CONT: addr = LM3631_REG_ENTIME_VCONT; mask = LM3631_ENTIME_CONT_MASK; break; case LM3631_LDO_OREF: addr = LM3631_REG_ENTIME_VOREF; mask = LM3631_ENTIME_MASK; break; case LM3631_LDO_POS: addr = LM3631_REG_ENTIME_VPOS; mask = LM3631_ENTIME_MASK; break; case LM3631_LDO_NEG: addr = LM3631_REG_ENTIME_VNEG; mask = LM3631_ENTIME_MASK; break; default: return 0; } if (regmap_read(rdev->regmap, addr, (unsigned int *)&val)) return -EINVAL; val = (val & mask) >> LM3631_ENTIME_SHIFT; if (id == LM3631_LDO_CONT) return ldo_cont_enable_time[val]; else return ENABLE_TIME_USEC * val; }
static int max77693_get_flash_faults(struct max77693_sub_led *sub_led) { struct max77693_led_device *led = sub_led_to_led(sub_led); struct regmap *rmap = led->regmap; unsigned int v; u8 fault_open_mask, fault_short_mask; int ret; sub_led->flash_faults = 0; if (led->iout_joint) { fault_open_mask = FLASH_INT_FLED1_OPEN | FLASH_INT_FLED2_OPEN; fault_short_mask = FLASH_INT_FLED1_SHORT | FLASH_INT_FLED2_SHORT; } else { fault_open_mask = (sub_led->fled_id == FLED1) ? FLASH_INT_FLED1_OPEN : FLASH_INT_FLED2_OPEN; fault_short_mask = (sub_led->fled_id == FLED1) ? FLASH_INT_FLED1_SHORT : FLASH_INT_FLED2_SHORT; } ret = regmap_read(rmap, MAX77693_LED_REG_FLASH_INT, &v); if (ret < 0) return ret; if (v & fault_open_mask) sub_led->flash_faults |= LED_FAULT_OVER_VOLTAGE; if (v & fault_short_mask) sub_led->flash_faults |= LED_FAULT_SHORT_CIRCUIT; if (v & FLASH_INT_OVER_CURRENT) sub_led->flash_faults |= LED_FAULT_OVER_CURRENT; return 0; }
static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai, int clk_id, unsigned int freq, int fsl_dir) { struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai); u32 val_cr2, reg_cr2; if (fsl_dir == FSL_FMT_TRANSMITTER) reg_cr2 = FSL_SAI_TCR2; else reg_cr2 = FSL_SAI_RCR2; regmap_read(sai->regmap, reg_cr2, &val_cr2); val_cr2 &= ~FSL_SAI_CR2_MSEL_MASK; switch (clk_id) { case FSL_SAI_CLK_BUS: val_cr2 |= FSL_SAI_CR2_MSEL_BUS; break; case FSL_SAI_CLK_MAST1: val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1; break; case FSL_SAI_CLK_MAST2: val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2; break; case FSL_SAI_CLK_MAST3: val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3; break; default: return -EINVAL; } regmap_write(sai->regmap, reg_cr2, val_cr2); return 0; }
/* * Synchronous read protocol for RevB0 onwards: * * 1. Write '1' to ReadState bit in KEYP_SCAN register * 2. Wait 2*32KHz clocks, so that HW can successfully enter read mode * synchronously * 3. Read rows in old array first if events are more than one * 4. Read rows in recent array * 5. Wait 4*32KHz clocks * 6. Write '0' to ReadState bit of KEYP_SCAN register so that hw can * synchronously exit read mode. */ static int pmic8xxx_chk_sync_read(struct pmic8xxx_kp *kp) { int rc; unsigned int scan_val; rc = regmap_read(kp->regmap, KEYP_SCAN, &scan_val); if (rc < 0) { dev_err(kp->dev, "Error reading KEYP_SCAN reg, rc=%d\n", rc); return rc; } scan_val |= 0x1; rc = regmap_write(kp->regmap, KEYP_SCAN, scan_val); if (rc < 0) { dev_err(kp->dev, "Error writing KEYP_SCAN reg, rc=%d\n", rc); return rc; } /* 2 * 32KHz clocks */ udelay((2 * DIV_ROUND_UP(USEC_PER_SEC, KEYP_CLOCK_FREQ)) + 1); return rc; }
static int lp8860_init(struct lp8860_led *led) { unsigned int read_buf; int ret, i, reg_count; if (led->regulator) { ret = regulator_enable(led->regulator); if (ret) { dev_err(&led->client->dev, "Failed to enable regulator\n"); return ret; } } if (led->enable_gpio) gpiod_direction_output(led->enable_gpio, 1); ret = lp8860_fault_check(led); if (ret) goto out; ret = regmap_read(led->regmap, LP8860_STATUS, &read_buf); if (ret) goto out; ret = lp8860_unlock_eeprom(led, LP8860_UNLOCK_EEPROM); if (ret) { dev_err(&led->client->dev, "Failed unlocking EEPROM\n"); goto out; } reg_count = ARRAY_SIZE(lp8860_eeprom_disp_regs) / sizeof(lp8860_eeprom_disp_regs[0]); for (i = 0; i < reg_count; i++) { ret = regmap_write(led->eeprom_regmap, lp8860_eeprom_disp_regs[i].reg, lp8860_eeprom_disp_regs[i].value); if (ret) { dev_err(&led->client->dev, "Failed writing EEPROM\n"); goto out; } } ret = lp8860_unlock_eeprom(led, LP8860_LOCK_EEPROM); if (ret) goto out; ret = regmap_write(led->regmap, LP8860_EEPROM_CNTRL, LP8860_PROGRAM_EEPROM); if (ret) { dev_err(&led->client->dev, "Failed programming EEPROM\n"); goto out; } return ret; out: if (ret) if (led->enable_gpio) gpiod_direction_output(led->enable_gpio, 0); if (led->regulator) { ret = regulator_disable(led->regulator); if (ret) dev_err(&led->client->dev, "Failed to disable regulator\n"); } return ret; }
static ssize_t tsc200x_selftest_show(struct device *dev, struct device_attribute *attr, char *buf) { struct tsc200x *ts = dev_get_drvdata(dev); unsigned int temp_high; unsigned int temp_high_orig; unsigned int temp_high_test; bool success = true; int error; mutex_lock(&ts->mutex); /* * Test TSC200X communications via temp high register. */ __tsc200x_disable(ts); error = regmap_read(ts->regmap, TSC200X_REG_TEMP_HIGH, &temp_high_orig); if (error) { dev_warn(dev, "selftest failed: read error %d\n", error); success = false; goto out; } temp_high_test = (temp_high_orig - 1) & MAX_12BIT; error = regmap_write(ts->regmap, TSC200X_REG_TEMP_HIGH, temp_high_test); if (error) { dev_warn(dev, "selftest failed: write error %d\n", error); success = false; goto out; } error = regmap_read(ts->regmap, TSC200X_REG_TEMP_HIGH, &temp_high); if (error) { dev_warn(dev, "selftest failed: read error %d after write\n", error); success = false; goto out; } if (temp_high != temp_high_test) { dev_warn(dev, "selftest failed: %d != %d\n", temp_high, temp_high_test); success = false; } /* hardware reset */ tsc200x_set_reset(ts, false); usleep_range(100, 500); /* only 10us required */ tsc200x_set_reset(ts, true); if (!success) goto out; /* test that the reset really happened */ error = regmap_read(ts->regmap, TSC200X_REG_TEMP_HIGH, &temp_high); if (error) { dev_warn(dev, "selftest failed: read error %d after reset\n", error); success = false; goto out; } if (temp_high != temp_high_orig) { dev_warn(dev, "selftest failed after reset: %d != %d\n", temp_high, temp_high_orig); success = false; } out: __tsc200x_enable(ts); mutex_unlock(&ts->mutex); return sprintf(buf, "%d\n", success); }
static inline int __at86rf230_read(struct at86rf230_local *lp, unsigned int addr, unsigned int *data) { return regmap_read(lp->regmap, addr, data); }
static int __devinit tps51632_init_dcdc(struct tps51632_chip *tps, struct tps51632_regulator_platform_data *pdata) { int ret; uint8_t control = 0; int vsel; unsigned int vmax; if (pdata->enable_pwm) { control |= TPS51632_DVFS_PWMEN; tps->pwm_enabled = pdata->enable_pwm; } vsel = DIV_ROUND_UP(pdata->base_voltage_uV - TPS51632_MIN_VOLATGE, TPS51632_VOLATGE_STEP) + 0x19; ret = regmap_write(tps->regmap, TPS51632_VOLTAGE_BASE_REG, vsel); if (ret < 0) { dev_err(tps->dev, "BASE reg write failed, err %d\n", ret); return ret; } if (pdata->dvfs_step_20mV) control |= TPS51632_DVFS_STEP_20; if (pdata->enable_vmax_alarm) control |= TPS51632_DVFS_VMAX_PG; if (pdata->enable_overcurrent_alram) control |= TPS51632_DVFS_OCA_EN; if (pdata->max_voltage_uV) { /** * TPS51632 hw behavior: VMAX register can be write only * once as it get locked after first write. The lock get * reset only when device is power-reset. * Write register only when lock bit is not enabled. */ ret = regmap_read(tps->regmap, TPS51632_VMAX_REG, &vmax); if (ret < 0) { dev_err(tps->dev, "VMAX read failed, err %d\n", ret); return ret; } if (vmax & TPS51632_VMAX_LOCK) goto skip_vmax_config; vsel = DIV_ROUND_UP(pdata->max_voltage_uV - TPS51632_MIN_VOLATGE, TPS51632_VOLATGE_STEP) + 0x19; ret = regmap_write(tps->regmap, TPS51632_VMAX_REG, vsel); if (ret < 0) { dev_err(tps->dev, "VMAX write failed, err %d\n", ret); return ret; } } skip_vmax_config: ret = regmap_write(tps->regmap, TPS51632_DVFS_CONTROL_REG, control); if (ret < 0) { dev_err(tps->dev, "DVFS reg write failed, err %d\n", ret); return ret; } tps->change_uv_per_us = max(6000u, pdata->slew_rate_uv_per_us); vsel = BIT(tps->change_uv_per_us/6000 - 1); ret = regmap_write(tps->regmap, TPS51632_SLEW_REGS, vsel); if (ret < 0) dev_err(tps->dev, "SLEW reg write failed, err %d\n", ret); return ret; }
static int da9063_regulator_probe(struct platform_device *pdev) { struct da9063 *da9063 = dev_get_drvdata(pdev->dev.parent); struct da9063_pdata *da9063_pdata = dev_get_platdata(da9063->dev); struct of_regulator_match *da9063_reg_matches = NULL; struct da9063_regulators_pdata *regl_pdata; const struct da9063_dev_model *model; struct da9063_regulators *regulators; struct da9063_regulator *regl; struct regulator_config config; bool bcores_merged, bmem_bio_merged; int id, irq, n, n_regulators, ret, val; size_t size; regl_pdata = da9063_pdata ? da9063_pdata->regulators_pdata : NULL; if (!regl_pdata) regl_pdata = da9063_parse_regulators_dt(pdev, &da9063_reg_matches); if (IS_ERR(regl_pdata) || regl_pdata->n_regulators == 0) { dev_err(&pdev->dev, "No regulators defined for the platform\n"); return PTR_ERR(regl_pdata); } /* Find regulators set for particular device model */ for (model = regulators_models; model->regulator_info; model++) { if (model->dev_model == da9063->model) break; } if (!model->regulator_info) { dev_err(&pdev->dev, "Chip model not recognised (%u)\n", da9063->model); return -ENODEV; } ret = regmap_read(da9063->regmap, DA9063_REG_CONFIG_H, &val); if (ret < 0) { dev_err(&pdev->dev, "Error while reading BUCKs configuration\n"); return ret; } bcores_merged = val & DA9063_BCORE_MERGE; bmem_bio_merged = val & DA9063_BUCK_MERGE; n_regulators = model->n_regulators; if (bcores_merged) n_regulators -= 2; /* remove BCORE1, BCORE2 */ else n_regulators--; /* remove BCORES_MERGED */ if (bmem_bio_merged) n_regulators -= 2; /* remove BMEM, BIO */ else n_regulators--; /* remove BMEM_BIO_MERGED */ /* Allocate memory required by usable regulators */ size = sizeof(struct da9063_regulators) + n_regulators * sizeof(struct da9063_regulator); regulators = devm_kzalloc(&pdev->dev, size, GFP_KERNEL); if (!regulators) return -ENOMEM; regulators->n_regulators = n_regulators; platform_set_drvdata(pdev, regulators); /* Register all regulators declared in platform information */ n = 0; id = 0; while (n < regulators->n_regulators) { /* Skip regulator IDs depending on merge mode configuration */ switch (id) { case DA9063_ID_BCORE1: case DA9063_ID_BCORE2: if (bcores_merged) { id++; continue; } break; case DA9063_ID_BMEM: case DA9063_ID_BIO: if (bmem_bio_merged) { id++; continue; } break; case DA9063_ID_BCORES_MERGED: if (!bcores_merged) { id++; continue; } break; case DA9063_ID_BMEM_BIO_MERGED: if (!bmem_bio_merged) { id++; continue; } break; } /* Initialise regulator structure */ regl = ®ulators->regulator[n]; regl->hw = da9063; regl->info = &model->regulator_info[id]; regl->desc = regl->info->desc; regl->desc.type = REGULATOR_VOLTAGE; regl->desc.owner = THIS_MODULE; if (regl->info->mode.reg) regl->mode = devm_regmap_field_alloc(&pdev->dev, da9063->regmap, regl->info->mode); if (regl->info->suspend.reg) regl->suspend = devm_regmap_field_alloc(&pdev->dev, da9063->regmap, regl->info->suspend); if (regl->info->sleep.reg) regl->sleep = devm_regmap_field_alloc(&pdev->dev, da9063->regmap, regl->info->sleep); if (regl->info->suspend_sleep.reg) regl->suspend_sleep = devm_regmap_field_alloc(&pdev->dev, da9063->regmap, regl->info->suspend_sleep); if (regl->info->ilimit.reg) regl->ilimit = devm_regmap_field_alloc(&pdev->dev, da9063->regmap, regl->info->ilimit); /* Register regulator */ memset(&config, 0, sizeof(config)); config.dev = &pdev->dev; config.init_data = da9063_get_regulator_initdata(regl_pdata, id); config.driver_data = regl; if (da9063_reg_matches) config.of_node = da9063_reg_matches[id].of_node; config.regmap = da9063->regmap; regl->rdev = devm_regulator_register(&pdev->dev, ®l->desc, &config); if (IS_ERR(regl->rdev)) { dev_err(&pdev->dev, "Failed to register %s regulator\n", regl->desc.name); return PTR_ERR(regl->rdev); } id++; n++; } /* LDOs overcurrent event support */ irq = platform_get_irq_byname(pdev, "LDO_LIM"); if (irq < 0) { dev_err(&pdev->dev, "Failed to get IRQ.\n"); return irq; } ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, da9063_ldo_lim_event, IRQF_TRIGGER_LOW | IRQF_ONESHOT, "LDO_LIM", regulators); if (ret) { dev_err(&pdev->dev, "Failed to request LDO_LIM IRQ.\n"); return ret; } return 0; }
static int adau1977_power_enable(struct adau1977 *adau1977) { unsigned int val; int ret = 0; if (adau1977->enabled) return 0; ret = regulator_enable(adau1977->avdd_reg); if (ret) return ret; if (adau1977->dvdd_reg) { ret = regulator_enable(adau1977->dvdd_reg); if (ret) goto err_disable_avdd; } if (adau1977->reset_gpio) gpiod_set_value_cansleep(adau1977->reset_gpio, 1); regcache_cache_only(adau1977->regmap, false); if (adau1977->switch_mode) adau1977->switch_mode(adau1977->dev); ret = adau1977_reset(adau1977); if (ret) goto err_disable_dvdd; ret = regmap_update_bits(adau1977->regmap, ADAU1977_REG_POWER, ADAU1977_POWER_PWUP, ADAU1977_POWER_PWUP); if (ret) goto err_disable_dvdd; ret = regcache_sync(adau1977->regmap); if (ret) goto err_disable_dvdd; /* * The PLL register is not affected by the software reset. It is * possible that the value of the register was changed to the * default value while we were in cache only mode. In this case * regcache_sync will skip over it and we have to manually sync * it. */ ret = regmap_read(adau1977->regmap, ADAU1977_REG_PLL, &val); if (ret) goto err_disable_dvdd; if (val == 0x41) { regcache_cache_bypass(adau1977->regmap, true); ret = regmap_write(adau1977->regmap, ADAU1977_REG_PLL, 0x41); if (ret) goto err_disable_dvdd; regcache_cache_bypass(adau1977->regmap, false); } adau1977->enabled = true; return ret; err_disable_dvdd: if (adau1977->dvdd_reg) regulator_disable(adau1977->dvdd_reg); err_disable_avdd: regulator_disable(adau1977->avdd_reg); return ret; }
static int __devinit ncp6335d_init(struct ncp6335d_info *dd, const struct ncp6335d_platform_data *pdata) { int rc; unsigned int val; switch (pdata->default_vsel) { case NCP6335D_VSEL0: dd->vsel_reg = REG_NCP6335D_PROGVSEL0; dd->mode_bit = NCP6335D_PWM_MODE0; break; case NCP6335D_VSEL1: dd->vsel_reg = REG_NCP6335D_PROGVSEL1; dd->mode_bit = NCP6335D_PWM_MODE1; break; default: dev_err(dd->dev, "Invalid VSEL ID %d\n", pdata->default_vsel); return -EINVAL; } /* get the current programmed voltage */ rc = regmap_read(dd->regmap, dd->vsel_reg, &val); if (rc) { dev_err(dd->dev, "Unable to get volatge rc(%d)", rc); return rc; } dd->vsel_ctrl_val = val; dd->curr_voltage = ((val & NCP6335D_VOUT_SEL_MASK) * NCP6335D_STEP_VOLTAGE_UV) + NCP6335D_MIN_VOLTAGE_UV; /* set discharge */ rc = regmap_update_bits(dd->regmap, REG_NCP6335D_PGOOD, NCP6335D_PGOOD_DISCHG, (pdata->discharge_enable ? NCP6335D_PGOOD_DISCHG : 0)); if (rc) { dev_err(dd->dev, "Unable to set Active Discharge rc(%d)\n", rc); return -EINVAL; } /* set slew rate */ if (pdata->slew_rate_ns < NCP6335D_MIN_SLEW_NS || pdata->slew_rate_ns > NCP6335D_MAX_SLEW_NS) { dev_err(dd->dev, "Invalid slew rate %d\n", pdata->slew_rate_ns); return -EINVAL; } val = DIV_ROUND_UP(pdata->slew_rate_ns, NCP6335D_MIN_SLEW_NS); dd->slew_rate = val * NCP6335D_MIN_SLEW_NS; if (val) val = ilog2(val); else dd->slew_rate = NCP6335D_MIN_SLEW_NS; rc = regmap_update_bits(dd->regmap, REG_NCP6335D_TIMING, NCP6335D_SLEW_MASK, val << NCP6335D_SLEW_SHIFT); if (rc) dev_err(dd->dev, "Unable to set slew rate rc(%d)\n", rc); if (pdata->rearm_disable) { rc = regmap_update_bits(dd->regmap, REG_NCP6335D_LIMCONF, NCP6335D_TSD_MASK, NCP6335D_TSD_VAL); if (rc) dev_err(dd->dev, "Unable to reset REARM bit rc(%d)\n", rc); } /* Set Sleep mode bit */ rc = regmap_update_bits(dd->regmap, REG_NCP6335D_COMMAND, NCP6335D_SLEEP_MODE, pdata->sleep_enable ? NCP6335D_SLEEP_MODE : 0); if (rc) dev_err(dd->dev, "Unable to set sleep mode (%d)\n", rc); dump_registers(dd, REG_NCP6335D_PROGVSEL0, __func__); dump_registers(dd, REG_NCP6335D_PGOOD, __func__); dump_registers(dd, REG_NCP6335D_TIMING, __func__); dump_registers(dd, REG_NCP6335D_COMMAND, __func__); dump_registers(dd, REG_NCP6335D_LIMCONF, __func__); return rc; }
/* * alc5632 2 wire address is determined by A1 pin * state during powerup. * low = 0x1a * high = 0x1b */ static int alc5632_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id) { struct alc5632_priv *alc5632; int ret, ret1, ret2; unsigned int vid1, vid2; alc5632 = devm_kzalloc(&client->dev, sizeof(struct alc5632_priv), GFP_KERNEL); if (alc5632 == NULL) return -ENOMEM; i2c_set_clientdata(client, alc5632); alc5632->regmap = devm_regmap_init_i2c(client, &alc5632_regmap); if (IS_ERR(alc5632->regmap)) { ret = PTR_ERR(alc5632->regmap); dev_err(&client->dev, "regmap_init() failed: %d\n", ret); return ret; } ret1 = regmap_read(alc5632->regmap, ALC5632_VENDOR_ID1, &vid1); ret2 = regmap_read(alc5632->regmap, ALC5632_VENDOR_ID2, &vid2); if (ret1 != 0 || ret2 != 0) { dev_err(&client->dev, "Failed to read chip ID: ret1=%d, ret2=%d\n", ret1, ret2); return -EIO; } vid2 >>= 8; if ((vid1 != 0x10EC) || (vid2 != id->driver_data)) { dev_err(&client->dev, "Device is not a ALC5632: VID1=0x%x, VID2=0x%x\n", vid1, vid2); return -EINVAL; } ret = alc5632_reset(alc5632->regmap); if (ret < 0) { dev_err(&client->dev, "Failed to issue reset\n"); return ret; } alc5632->id = vid2; switch (alc5632->id) { case 0x5c: alc5632_dai.name = "alc5632-hifi"; break; default: return -EINVAL; } ret = snd_soc_register_codec(&client->dev, &soc_codec_device_alc5632, &alc5632_dai, 1); if (ret < 0) { dev_err(&client->dev, "Failed to register codec: %d\n", ret); return ret; } return ret; }
static ssize_t regmap_map_read_file(struct file *file, char __user *user_buf, size_t count, loff_t *ppos) { int reg_len, val_len, tot_len; size_t buf_pos = 0; loff_t p = 0; ssize_t ret; int i; struct regmap *map = file->private_data; char *buf; unsigned int val; if (*ppos < 0 || !count) return -EINVAL; buf = kmalloc(count, GFP_KERNEL); if (!buf) return -ENOMEM; /* Calculate the length of a fixed format */ reg_len = regmap_calc_reg_len(map->max_register, buf, count); val_len = 2 * map->format.val_bytes; tot_len = reg_len + val_len + 3; /* : \n */ for (i = 0; i < map->max_register + 1; i++) { if (!regmap_readable(map, i)) continue; if (regmap_precious(map, i)) continue; /* If we're in the region the user is trying to read */ if (p >= *ppos) { /* ...but not beyond it */ if (buf_pos >= count - 1 - tot_len) break; /* Format the register */ snprintf(buf + buf_pos, count - buf_pos, "%.*x: ", reg_len, i); buf_pos += reg_len + 2; /* Format the value, write all X if we can't read */ ret = regmap_read(map, i, &val); if (ret == 0) snprintf(buf + buf_pos, count - buf_pos, "%.*x", val_len, val); else memset(buf + buf_pos, 'X', val_len); buf_pos += 2 * map->format.val_bytes; buf[buf_pos++] = '\n'; } p += tot_len; } ret = buf_pos; if (copy_to_user(user_buf, buf, buf_pos)) { ret = -EFAULT; goto out; } *ppos += buf_pos; out: kfree(buf); return ret; }
static int palmas_i2c_probe(struct i2c_client *i2c, const struct i2c_device_id *id) { struct palmas *palmas; struct palmas_platform_data *pdata; struct device_node *node = i2c->dev.of_node; int ret = 0, i; unsigned int reg, addr; int slave; struct mfd_cell *children; pdata = dev_get_platdata(&i2c->dev); if (node && !pdata) { pdata = devm_kzalloc(&i2c->dev, sizeof(*pdata), GFP_KERNEL); if (!pdata) return -ENOMEM; palmas_dt_to_pdata(node, pdata); } if (!pdata) return -EINVAL; palmas = devm_kzalloc(&i2c->dev, sizeof(struct palmas), GFP_KERNEL); if (palmas == NULL) return -ENOMEM; i2c_set_clientdata(i2c, palmas); palmas->dev = &i2c->dev; palmas->id = id->driver_data; palmas->irq = i2c->irq; for (i = 0; i < PALMAS_NUM_CLIENTS; i++) { if (i == 0) palmas->i2c_clients[i] = i2c; else { palmas->i2c_clients[i] = i2c_new_dummy(i2c->adapter, i2c->addr + i); if (!palmas->i2c_clients[i]) { dev_err(palmas->dev, "can't attach client %d\n", i); ret = -ENOMEM; goto err; } } palmas->regmap[i] = devm_regmap_init_i2c(palmas->i2c_clients[i], &palmas_regmap_config[i]); if (IS_ERR(palmas->regmap[i])) { ret = PTR_ERR(palmas->regmap[i]); dev_err(palmas->dev, "Failed to allocate regmap %d, err: %d\n", i, ret); goto err; } } /* Change IRQ into clear on read mode for efficiency */ slave = PALMAS_BASE_TO_SLAVE(PALMAS_INTERRUPT_BASE); addr = PALMAS_BASE_TO_REG(PALMAS_INTERRUPT_BASE, PALMAS_INT_CTRL); reg = PALMAS_INT_CTRL_INT_CLEAR; regmap_write(palmas->regmap[slave], addr, reg); ret = regmap_add_irq_chip(palmas->regmap[slave], palmas->irq, IRQF_ONESHOT | IRQF_TRIGGER_LOW, 0, &palmas_irq_chip, &palmas->irq_data); if (ret < 0) goto err; slave = PALMAS_BASE_TO_SLAVE(PALMAS_PU_PD_OD_BASE); addr = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE, PALMAS_PRIMARY_SECONDARY_PAD1); if (pdata->mux_from_pdata) { reg = pdata->pad1; ret = regmap_write(palmas->regmap[slave], addr, reg); if (ret) goto err_irq; } else { ret = regmap_read(palmas->regmap[slave], addr, ®); if (ret) goto err_irq; } if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0)) palmas->gpio_muxed |= PALMAS_GPIO_0_MUXED; if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK)) palmas->gpio_muxed |= PALMAS_GPIO_1_MUXED; else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK) == (2 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT)) palmas->led_muxed |= PALMAS_LED1_MUXED; else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK) == (3 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT)) palmas->pwm_muxed |= PALMAS_PWM1_MUXED; if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK)) palmas->gpio_muxed |= PALMAS_GPIO_2_MUXED; else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK) == (2 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT)) palmas->led_muxed |= PALMAS_LED2_MUXED; else if ((reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK) == (3 << PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT)) palmas->pwm_muxed |= PALMAS_PWM2_MUXED; if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3)) palmas->gpio_muxed |= PALMAS_GPIO_3_MUXED; addr = PALMAS_BASE_TO_REG(PALMAS_PU_PD_OD_BASE, PALMAS_PRIMARY_SECONDARY_PAD2); if (pdata->mux_from_pdata) { reg = pdata->pad2; ret = regmap_write(palmas->regmap[slave], addr, reg); if (ret) goto err_irq; } else { ret = regmap_read(palmas->regmap[slave], addr, ®); if (ret) goto err_irq; } if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4)) palmas->gpio_muxed |= PALMAS_GPIO_4_MUXED; if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK)) palmas->gpio_muxed |= PALMAS_GPIO_5_MUXED; if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6)) palmas->gpio_muxed |= PALMAS_GPIO_6_MUXED; if (!(reg & PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK)) palmas->gpio_muxed |= PALMAS_GPIO_7_MUXED; dev_info(palmas->dev, "Muxing GPIO %x, PWM %x, LED %x\n", palmas->gpio_muxed, palmas->pwm_muxed, palmas->led_muxed); reg = pdata->power_ctrl; slave = PALMAS_BASE_TO_SLAVE(PALMAS_PMU_CONTROL_BASE); addr = PALMAS_BASE_TO_REG(PALMAS_PMU_CONTROL_BASE, PALMAS_POWER_CTRL); ret = regmap_write(palmas->regmap[slave], addr, reg); if (ret) goto err_irq; /* * If we are probing with DT do this the DT way and return here * otherwise continue and add devices using mfd helpers. */ if (node) { ret = of_platform_populate(node, NULL, NULL, &i2c->dev); if (ret < 0) goto err_irq; else return ret; } children = kmemdup(palmas_children, sizeof(palmas_children), GFP_KERNEL); if (!children) { ret = -ENOMEM; goto err_irq; } children[PALMAS_PMIC_ID].platform_data = pdata->pmic_pdata; children[PALMAS_PMIC_ID].pdata_size = sizeof(*pdata->pmic_pdata); children[PALMAS_GPADC_ID].platform_data = pdata->gpadc_pdata; children[PALMAS_GPADC_ID].pdata_size = sizeof(*pdata->gpadc_pdata); children[PALMAS_RESOURCE_ID].platform_data = pdata->resource_pdata; children[PALMAS_RESOURCE_ID].pdata_size = sizeof(*pdata->resource_pdata); children[PALMAS_USB_ID].platform_data = pdata->usb_pdata; children[PALMAS_USB_ID].pdata_size = sizeof(*pdata->usb_pdata); children[PALMAS_CLK_ID].platform_data = pdata->clk_pdata; children[PALMAS_CLK_ID].pdata_size = sizeof(*pdata->clk_pdata); ret = mfd_add_devices(palmas->dev, -1, children, ARRAY_SIZE(palmas_children), NULL, 0, regmap_irq_get_domain(palmas->irq_data)); kfree(children); if (ret < 0) goto err_devices; return ret; err_devices: mfd_remove_devices(palmas->dev); err_irq: regmap_del_irq_chip(palmas->irq, palmas->irq_data); err: return ret; }
static inline u32 tegra20_das_read(u32 reg) { u32 val; regmap_read(das->regmap, reg, &val); return val; }
static int stm32_i2s_configure_clock(struct snd_soc_dai *cpu_dai, struct snd_pcm_hw_params *params) { struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai); unsigned long i2s_clock_rate; unsigned int tmp, div, real_div, nb_bits, frame_len; unsigned int rate = params_rate(params); int ret; u32 cgfr, cgfr_mask; bool odd; if (!(rate % 11025)) clk_set_parent(i2s->i2sclk, i2s->x11kclk); else clk_set_parent(i2s->i2sclk, i2s->x8kclk); i2s_clock_rate = clk_get_rate(i2s->i2sclk); /* * mckl = mclk_ratio x ws * i2s mode : mclk_ratio = 256 * dsp mode : mclk_ratio = 128 * * mclk on * i2s mode : div = i2s_clk / (mclk_ratio * ws) * dsp mode : div = i2s_clk / (mclk_ratio * ws) * mclk off * i2s mode : div = i2s_clk / (nb_bits x ws) * dsp mode : div = i2s_clk / (nb_bits x ws) */ if (i2s->mclk_rate) { tmp = DIV_ROUND_CLOSEST(i2s_clock_rate, i2s->mclk_rate); } else { frame_len = 32; if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_DSP_A) frame_len = 16; /* master clock not enabled */ ret = regmap_read(i2s->regmap, STM32_I2S_CGFR_REG, &cgfr); if (ret < 0) return ret; nb_bits = frame_len * ((cgfr & I2S_CGFR_CHLEN) + 1); tmp = DIV_ROUND_CLOSEST(i2s_clock_rate, (nb_bits * rate)); } /* Check the parity of the divider */ odd = tmp & 0x1; /* Compute the div prescaler */ div = tmp >> 1; cgfr = I2S_CGFR_I2SDIV_SET(div) | (odd << I2S_CGFR_ODD_SHIFT); cgfr_mask = I2S_CGFR_I2SDIV_MASK | I2S_CGFR_ODD; real_div = ((2 * div) + odd); dev_dbg(cpu_dai->dev, "I2S clk: %ld, SCLK: %d\n", i2s_clock_rate, rate); dev_dbg(cpu_dai->dev, "Divider: 2*%d(div)+%d(odd) = %d\n", div, odd, real_div); if (((div == 1) && odd) || (div > I2S_CGFR_I2SDIV_MAX)) { dev_err(cpu_dai->dev, "Wrong divider setting\n"); return -EINVAL; } if (!div && !odd) dev_warn(cpu_dai->dev, "real divider forced to 1\n"); ret = regmap_update_bits(i2s->regmap, STM32_I2S_CGFR_REG, cgfr_mask, cgfr); if (ret < 0) return ret; /* Set bitclock and frameclock to their inactive state */ return regmap_update_bits(i2s->regmap, STM32_I2S_CFG2_REG, I2S_CFG2_AFCNTR, I2S_CFG2_AFCNTR); }
static int max77693_muic_probe(struct platform_device *pdev) { struct max77693_dev *max77693 = dev_get_drvdata(pdev->dev.parent); struct max77693_platform_data *pdata = dev_get_platdata(max77693->dev); struct max77693_muic_info *info; struct max77693_reg_data *init_data; int num_init_data; int delay_jiffies; int ret; int i; unsigned int id; info = devm_kzalloc(&pdev->dev, sizeof(struct max77693_muic_info), GFP_KERNEL); if (!info) return -ENOMEM; info->dev = &pdev->dev; info->max77693 = max77693; if (info->max77693->regmap_muic) { dev_dbg(&pdev->dev, "allocate register map\n"); } else { info->max77693->regmap_muic = devm_regmap_init_i2c( info->max77693->i2c_muic, &max77693_muic_regmap_config); if (IS_ERR(info->max77693->regmap_muic)) { ret = PTR_ERR(info->max77693->regmap_muic); dev_err(max77693->dev, "failed to allocate register map: %d\n", ret); return ret; } } /* Register input device for button of dock device */ info->dock = devm_input_allocate_device(&pdev->dev); if (!info->dock) { dev_err(&pdev->dev, "%s: failed to allocate input\n", __func__); return -ENOMEM; } info->dock->name = "max77693-muic/dock"; info->dock->phys = "max77693-muic/extcon"; info->dock->dev.parent = &pdev->dev; __set_bit(EV_REP, info->dock->evbit); input_set_capability(info->dock, EV_KEY, KEY_VOLUMEUP); input_set_capability(info->dock, EV_KEY, KEY_VOLUMEDOWN); input_set_capability(info->dock, EV_KEY, KEY_PLAYPAUSE); input_set_capability(info->dock, EV_KEY, KEY_PREVIOUSSONG); input_set_capability(info->dock, EV_KEY, KEY_NEXTSONG); ret = input_register_device(info->dock); if (ret < 0) { dev_err(&pdev->dev, "Cannot register input device error(%d)\n", ret); return ret; } platform_set_drvdata(pdev, info); mutex_init(&info->mutex); INIT_WORK(&info->irq_work, max77693_muic_irq_work); /* Support irq domain for MAX77693 MUIC device */ for (i = 0; i < ARRAY_SIZE(muic_irqs); i++) { struct max77693_muic_irq *muic_irq = &muic_irqs[i]; int virq; virq = regmap_irq_get_virq(max77693->irq_data_muic, muic_irq->irq); if (virq <= 0) return -EINVAL; muic_irq->virq = virq; ret = devm_request_threaded_irq(&pdev->dev, virq, NULL, max77693_muic_irq_handler, IRQF_NO_SUSPEND, muic_irq->name, info); if (ret) { dev_err(&pdev->dev, "failed: irq request (IRQ: %d, error :%d)\n", muic_irq->irq, ret); return ret; } } /* Initialize extcon device */ info->edev = devm_extcon_dev_allocate(&pdev->dev, max77693_extcon_cable); if (IS_ERR(info->edev)) { dev_err(&pdev->dev, "failed to allocate memory for extcon\n"); return -ENOMEM; } ret = devm_extcon_dev_register(&pdev->dev, info->edev); if (ret) { dev_err(&pdev->dev, "failed to register extcon device\n"); return ret; } /* Initialize MUIC register by using platform data or default data */ if (pdata && pdata->muic_data) { init_data = pdata->muic_data->init_data; num_init_data = pdata->muic_data->num_init_data; } else { init_data = default_init_data; num_init_data = ARRAY_SIZE(default_init_data); } for (i = 0; i < num_init_data; i++) { regmap_write(info->max77693->regmap_muic, init_data[i].addr, init_data[i].data); } if (pdata && pdata->muic_data) { struct max77693_muic_platform_data *muic_pdata = pdata->muic_data; /* * Default usb/uart path whether UART/USB or AUX_UART/AUX_USB * h/w path of COMP2/COMN1 on CONTROL1 register. */ if (muic_pdata->path_uart) info->path_uart = muic_pdata->path_uart; else info->path_uart = MAX77693_CONTROL1_SW_UART; if (muic_pdata->path_usb) info->path_usb = muic_pdata->path_usb; else info->path_usb = MAX77693_CONTROL1_SW_USB; /* * Default delay time for detecting cable state * after certain time. */ if (muic_pdata->detcable_delay_ms) delay_jiffies = msecs_to_jiffies(muic_pdata->detcable_delay_ms); else delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT); } else { info->path_usb = MAX77693_CONTROL1_SW_USB; info->path_uart = MAX77693_CONTROL1_SW_UART; delay_jiffies = msecs_to_jiffies(DELAY_MS_DEFAULT); } /* Set initial path for UART */ max77693_muic_set_path(info, info->path_uart, true); /* Check revision number of MUIC device*/ ret = regmap_read(info->max77693->regmap_muic, MAX77693_MUIC_REG_ID, &id); if (ret < 0) { dev_err(&pdev->dev, "failed to read revision number\n"); return ret; } dev_info(info->dev, "device ID : 0x%x\n", id); /* Set ADC debounce time */ max77693_muic_set_debounce_time(info, ADC_DEBOUNCE_TIME_25MS); /* * Detect accessory after completing the initialization of platform * * - Use delayed workqueue to detect cable state and then * notify cable state to notifiee/platform through uevent. * After completing the booting of platform, the extcon provider * driver should notify cable state to upper layer. */ INIT_DELAYED_WORK(&info->wq_detcable, max77693_muic_detect_cable_wq); queue_delayed_work(system_power_efficient_wq, &info->wq_detcable, delay_jiffies); return ret; }
static int __devinit ncp6335d_regulator_probe(struct i2c_client *client, const struct i2c_device_id *id) { int rc; unsigned int val = 0, val1 = 0; struct ncp6335d_info *dd; const struct ncp6335d_platform_data *pdata; pdata = client->dev.platform_data; if (!pdata) { dev_err(&client->dev, "Platform data not specified\n"); return -EINVAL; } dd = devm_kzalloc(&client->dev, sizeof(*dd), GFP_KERNEL); if (!dd) { dev_err(&client->dev, "Unable to allocate memory\n"); return -ENOMEM; } dd->regmap = devm_regmap_init_i2c(client, &ncp6335d_regmap_config); if (IS_ERR(dd->regmap)) { dev_err(&client->dev, "Error allocating regmap\n"); return PTR_ERR(dd->regmap); } rc = regmap_read(dd->regmap, REG_NCP6335D_PID, &val); if (rc) { dev_err(&client->dev, "Unable to identify NCP6335D (PID), rc(%d)\n", rc); return rc; } rc = regmap_read(dd->regmap, REG_NCP6335D_FID, &val1); if (rc) { dev_err(&client->dev, "Unable to identify NCP6335D (FID), rc(%d)\n", rc); return rc; } dev_info(&client->dev, "Detected Regulator NCP6335D PID = %d, FID = %d\n", val, val1); dd->init_data = pdata->init_data; dd->dev = &client->dev; i2c_set_clientdata(client, dd); rc = ncp6335d_init(dd, pdata); if (rc) { dev_err(&client->dev, "Unable to intialize the regulator\n"); return -EINVAL; } dd->regulator = regulator_register(&rdesc, &client->dev, dd->init_data, dd, NULL); if (IS_ERR(dd->regulator)) { dev_err(&client->dev, "Unable to register regulator rc(%ld)", PTR_ERR(dd->regulator)); return PTR_ERR(dd->regulator); } ncp6335d = dd; return 0; }
/** * cs4270_i2c_probe - initialize the I2C interface of the CS4270 * @i2c_client: the I2C client object * @id: the I2C device ID (ignored) * * This function is called whenever the I2C subsystem finds a device that * matches the device ID given via a prior call to i2c_add_driver(). */ static int cs4270_i2c_probe(struct i2c_client *i2c_client, const struct i2c_device_id *id) { struct device_node *np = i2c_client->dev.of_node; struct cs4270_private *cs4270; unsigned int val; int ret, i; cs4270 = devm_kzalloc(&i2c_client->dev, sizeof(struct cs4270_private), GFP_KERNEL); if (!cs4270) return -ENOMEM; /* get the power supply regulators */ for (i = 0; i < ARRAY_SIZE(supply_names); i++) cs4270->supplies[i].supply = supply_names[i]; ret = devm_regulator_bulk_get(&i2c_client->dev, ARRAY_SIZE(cs4270->supplies), cs4270->supplies); if (ret < 0) return ret; /* See if we have a way to bring the codec out of reset */ if (np) { enum of_gpio_flags flags; int gpio = of_get_named_gpio_flags(np, "reset-gpio", 0, &flags); if (gpio_is_valid(gpio)) { ret = devm_gpio_request_one(&i2c_client->dev, gpio, flags & OF_GPIO_ACTIVE_LOW ? GPIOF_OUT_INIT_LOW : GPIOF_OUT_INIT_HIGH, "cs4270 reset"); if (ret < 0) return ret; } } cs4270->regmap = devm_regmap_init_i2c(i2c_client, &cs4270_regmap); if (IS_ERR(cs4270->regmap)) return PTR_ERR(cs4270->regmap); /* Verify that we have a CS4270 */ ret = regmap_read(cs4270->regmap, CS4270_CHIPID, &val); if (ret < 0) { dev_err(&i2c_client->dev, "failed to read i2c at addr %X\n", i2c_client->addr); return ret; } /* The top four bits of the chip ID should be 1100. */ if ((val & 0xF0) != 0xC0) { dev_err(&i2c_client->dev, "device at addr %X is not a CS4270\n", i2c_client->addr); return -ENODEV; } dev_info(&i2c_client->dev, "found device at i2c address %X\n", i2c_client->addr); dev_info(&i2c_client->dev, "hardware revision %X\n", val & 0xF); i2c_set_clientdata(i2c_client, cs4270); ret = devm_snd_soc_register_component(&i2c_client->dev, &soc_component_device_cs4270, &cs4270_dai, 1); return ret; }
static int max77650_regulator_probe(struct platform_device *pdev) { struct max77650_regulator_desc **rdescs; struct max77650_regulator_desc *rdesc; struct regulator_config config = { }; struct device *dev, *parent; struct regulator_dev *rdev; struct regmap *map; unsigned int val; int i, rv; dev = &pdev->dev; parent = dev->parent; if (!dev->of_node) dev->of_node = parent->of_node; rdescs = devm_kcalloc(dev, MAX77650_REGULATOR_NUM_REGULATORS, sizeof(*rdescs), GFP_KERNEL); if (!rdescs) return -ENOMEM; map = dev_get_regmap(parent, NULL); if (!map) return -ENODEV; rv = regmap_read(map, MAX77650_REG_CID, &val); if (rv) return rv; rdescs[MAX77650_REGULATOR_ID_LDO] = &max77650_LDO_desc; rdescs[MAX77650_REGULATOR_ID_SBB0] = &max77650_SBB0_desc; switch (MAX77650_CID_BITS(val)) { case MAX77650_CID_77650A: case MAX77650_CID_77650C: rdescs[MAX77650_REGULATOR_ID_SBB1] = &max77650_SBB1_desc; rdescs[MAX77650_REGULATOR_ID_SBB2] = &max77650_SBB2_desc; break; case MAX77650_CID_77651A: case MAX77650_CID_77651B: rdescs[MAX77650_REGULATOR_ID_SBB1] = &max77651_SBB1_desc; rdescs[MAX77650_REGULATOR_ID_SBB2] = &max77651_SBB2_desc; break; default: return -ENODEV; } config.dev = parent; for (i = 0; i < MAX77650_REGULATOR_NUM_REGULATORS; i++) { rdesc = rdescs[i]; config.driver_data = rdesc; rdev = devm_regulator_register(dev, &rdesc->desc, &config); if (IS_ERR(rdev)) return PTR_ERR(rdev); } return 0; }
static int ds1343_probe(struct spi_device *spi) { struct ds1343_priv *priv; struct regmap_config config = { .reg_bits = 8, .val_bits = 8, .write_flag_mask = 0x80, }; unsigned int data; int res; struct nvmem_config nvmem_cfg = { .name = "ds1343-", .word_size = 1, .stride = 1, .size = DS1343_NVRAM_LEN, .reg_read = ds1343_nvram_read, .reg_write = ds1343_nvram_write, }; priv = devm_kzalloc(&spi->dev, sizeof(struct ds1343_priv), GFP_KERNEL); if (!priv) return -ENOMEM; priv->spi = spi; mutex_init(&priv->mutex); /* RTC DS1347 works in spi mode 3 and * its chip select is active high */ spi->mode = SPI_MODE_3 | SPI_CS_HIGH; spi->bits_per_word = 8; res = spi_setup(spi); if (res) return res; spi_set_drvdata(spi, priv); priv->map = devm_regmap_init_spi(spi, &config); if (IS_ERR(priv->map)) { dev_err(&spi->dev, "spi regmap init failed for rtc ds1343\n"); return PTR_ERR(priv->map); } res = regmap_read(priv->map, DS1343_SECONDS_REG, &data); if (res) return res; regmap_read(priv->map, DS1343_CONTROL_REG, &data); data |= DS1343_INTCN; data &= ~(DS1343_EOSC | DS1343_A1IE | DS1343_A0IE); regmap_write(priv->map, DS1343_CONTROL_REG, data); regmap_read(priv->map, DS1343_STATUS_REG, &data); data &= ~(DS1343_OSF | DS1343_IRQF1 | DS1343_IRQF0); regmap_write(priv->map, DS1343_STATUS_REG, data); priv->rtc = devm_rtc_allocate_device(&spi->dev); if (IS_ERR(priv->rtc)) return PTR_ERR(priv->rtc); priv->rtc->nvram_old_abi = true; priv->rtc->ops = &ds1343_rtc_ops; res = rtc_register_device(priv->rtc); if (res) return res; nvmem_cfg.priv = priv; rtc_nvmem_register(priv->rtc, &nvmem_cfg); priv->irq = spi->irq; if (priv->irq >= 0) { res = devm_request_threaded_irq(&spi->dev, spi->irq, NULL, ds1343_thread, IRQF_ONESHOT, "ds1343", priv); if (res) { priv->irq = -1; dev_err(&spi->dev, "unable to request irq for rtc ds1343\n"); } else { device_init_wakeup(&spi->dev, true); dev_pm_set_wake_irq(&spi->dev, spi->irq); } } res = ds1343_sysfs_register(&spi->dev); if (res) dev_err(&spi->dev, "unable to create sysfs entries for rtc ds1343\n"); return 0; } static int ds1343_remove(struct spi_device *spi) { struct ds1343_priv *priv = spi_get_drvdata(spi); if (spi->irq) { mutex_lock(&priv->mutex); priv->irqen &= ~RTC_AF; mutex_unlock(&priv->mutex); dev_pm_clear_wake_irq(&spi->dev); device_init_wakeup(&spi->dev, false); devm_free_irq(&spi->dev, spi->irq, priv); } spi_set_drvdata(spi, NULL); ds1343_sysfs_unregister(&spi->dev); return 0; } #ifdef CONFIG_PM_SLEEP static int ds1343_suspend(struct device *dev) { struct spi_device *spi = to_spi_device(dev); if (spi->irq >= 0 && device_may_wakeup(dev)) enable_irq_wake(spi->irq); return 0; } static int ds1343_resume(struct device *dev) { struct spi_device *spi = to_spi_device(dev); if (spi->irq >= 0 && device_may_wakeup(dev)) disable_irq_wake(spi->irq); return 0; } #endif static SIMPLE_DEV_PM_OPS(ds1343_pm, ds1343_suspend, ds1343_resume); static struct spi_driver ds1343_driver = { .driver = { .name = "ds1343", .pm = &ds1343_pm, }, .probe = ds1343_probe, .remove = ds1343_remove, .id_table = ds1343_id, }; module_spi_driver(ds1343_driver); MODULE_DESCRIPTION("DS1343 RTC SPI Driver"); MODULE_AUTHOR("Raghavendra Chandra Ganiga <*****@*****.**>," "Ankur Srivastava <*****@*****.**>"); MODULE_LICENSE("GPL v2");
static int wm8400_register_codec(struct wm8400 *wm8400) { struct mfd_cell cell = { .name = "wm8400-codec", .platform_data = wm8400, .pdata_size = sizeof(*wm8400), }; return mfd_add_devices(wm8400->dev, -1, &cell, 1, NULL, 0); } /* * wm8400_init - Generic initialisation * * The WM8400 can be configured as either an I2C or SPI device. Probe * functions for each bus set up the accessors then call into this to * set up the device itself. */ static int wm8400_init(struct wm8400 *wm8400, struct wm8400_platform_data *pdata) { u16 reg; int ret, i; mutex_init(&wm8400->io_lock); dev_set_drvdata(wm8400->dev, wm8400); /* Check that this is actually a WM8400 */ ret = regmap_read(wm8400->regmap, WM8400_RESET_ID, &i); if (ret != 0) { dev_err(wm8400->dev, "Chip ID register read failed\n"); return -EIO; } if (i != reg_data[WM8400_RESET_ID].default_val) { dev_err(wm8400->dev, "Device is not a WM8400, ID is %x\n", reg); return -ENODEV; } /* We don't know what state the hardware is in and since this * is a PMIC we can't reset it safely so initialise the register * cache from the hardware. */ ret = regmap_raw_read(wm8400->regmap, 0, wm8400->reg_cache, ARRAY_SIZE(wm8400->reg_cache)); if (ret != 0) { dev_err(wm8400->dev, "Register cache read failed\n"); return -EIO; } for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++) wm8400->reg_cache[i] = be16_to_cpu(wm8400->reg_cache[i]); /* If the codec is in reset use hard coded values */ if (!(wm8400->reg_cache[WM8400_POWER_MANAGEMENT_1] & WM8400_CODEC_ENA)) for (i = 0; i < ARRAY_SIZE(wm8400->reg_cache); i++) if (reg_data[i].is_codec) wm8400->reg_cache[i] = reg_data[i].default_val; ret = wm8400_read(wm8400, WM8400_ID, 1, ®); if (ret != 0) { dev_err(wm8400->dev, "ID register read failed: %d\n", ret); return ret; } reg = (reg & WM8400_CHIP_REV_MASK) >> WM8400_CHIP_REV_SHIFT; dev_info(wm8400->dev, "WM8400 revision %x\n", reg); ret = wm8400_register_codec(wm8400); if (ret != 0) { dev_err(wm8400->dev, "Failed to register codec\n"); goto err_children; } if (pdata && pdata->platform_init) { ret = pdata->platform_init(wm8400->dev); if (ret != 0) { dev_err(wm8400->dev, "Platform init failed: %d\n", ret); goto err_children; } } else dev_warn(wm8400->dev, "No platform initialisation supplied\n"); return 0; err_children: mfd_remove_devices(wm8400->dev); return ret; }
int __devinit arizona_dev_init(struct arizona *arizona) { struct device *dev = arizona->dev; const char *type_name; unsigned int reg, val; int (*apply_patch)(struct arizona *) = NULL; int ret, i; dev_set_drvdata(arizona->dev, arizona); mutex_init(&arizona->clk_lock); if (dev_get_platdata(arizona->dev)) memcpy(&arizona->pdata, dev_get_platdata(arizona->dev), sizeof(arizona->pdata)); regcache_cache_only(arizona->regmap, true); switch (arizona->type) { case WM5102: case WM5110: for (i = 0; i < ARRAY_SIZE(wm5102_core_supplies); i++) arizona->core_supplies[i].supply = wm5102_core_supplies[i]; arizona->num_core_supplies = ARRAY_SIZE(wm5102_core_supplies); break; default: dev_err(arizona->dev, "Unknown device type %d\n", arizona->type); return -EINVAL; } ret = mfd_add_devices(arizona->dev, -1, early_devs, ARRAY_SIZE(early_devs), NULL, 0); if (ret != 0) { dev_err(dev, "Failed to add early children: %d\n", ret); return ret; } ret = devm_regulator_bulk_get(dev, arizona->num_core_supplies, arizona->core_supplies); if (ret != 0) { dev_err(dev, "Failed to request core supplies: %d\n", ret); goto err_early; } arizona->dcvdd = devm_regulator_get(arizona->dev, "DCVDD"); if (IS_ERR(arizona->dcvdd)) { ret = PTR_ERR(arizona->dcvdd); dev_err(dev, "Failed to request DCVDD: %d\n", ret); goto err_early; } ret = regulator_bulk_enable(arizona->num_core_supplies, arizona->core_supplies); if (ret != 0) { dev_err(dev, "Failed to enable core supplies: %d\n", ret); goto err_early; } ret = regulator_enable(arizona->dcvdd); if (ret != 0) { dev_err(dev, "Failed to enable DCVDD: %d\n", ret); goto err_enable; } if (arizona->pdata.control_init_time) msleep(arizona->pdata.control_init_time); if (arizona->pdata.reset) { /* Start out with /RESET low to put the chip into reset */ ret = gpio_request_one(arizona->pdata.reset, GPIOF_DIR_OUT | GPIOF_INIT_LOW, "arizona /RESET"); if (ret != 0) { dev_err(dev, "Failed to request /RESET: %d\n", ret); goto err_dcvdd; } gpio_set_value_cansleep(arizona->pdata.reset, 1); } regcache_cache_only(arizona->regmap, false); ret = regmap_read(arizona->regmap, ARIZONA_SOFTWARE_RESET, ®); if (ret != 0) { dev_err(dev, "Failed to read ID register: %d\n", ret); goto err_reset; } ret = regmap_read(arizona->regmap, ARIZONA_DEVICE_REVISION, &arizona->rev); if (ret != 0) { dev_err(dev, "Failed to read revision register: %d\n", ret); goto err_reset; } arizona->rev &= ARIZONA_DEVICE_REVISION_MASK; switch (reg) { #ifdef CONFIG_MFD_WM5102 case 0x5102: type_name = "WM5102"; if (arizona->type != WM5102) { dev_err(arizona->dev, "WM5102 registered as %d\n", arizona->type); arizona->type = WM5102; } apply_patch = wm5102_patch; break; #endif #ifdef CONFIG_MFD_WM5110 case 0x5110: type_name = "WM5110"; if (arizona->type != WM5110) { dev_err(arizona->dev, "WM5110 registered as %d\n", arizona->type); arizona->type = WM5110; } apply_patch = wm5110_patch; break; #endif default: dev_err(arizona->dev, "Unknown device ID %x\n", reg); goto err_reset; } dev_info(dev, "%s revision %c\n", type_name, arizona->rev + 'A'); /* If we have a /RESET GPIO we'll already be reset */ if (!arizona->pdata.reset) { ret = regmap_write(arizona->regmap, ARIZONA_SOFTWARE_RESET, 0); if (ret != 0) { dev_err(dev, "Failed to reset device: %d\n", ret); goto err_reset; } } ret = arizona_wait_for_boot(arizona); if (ret != 0) { dev_err(arizona->dev, "Device failed initial boot: %d\n", ret); goto err_reset; } if (apply_patch) { ret = apply_patch(arizona); if (ret != 0) { dev_err(arizona->dev, "Failed to apply patch: %d\n", ret); goto err_reset; } } for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) { if (!arizona->pdata.gpio_defaults[i]) continue; regmap_write(arizona->regmap, ARIZONA_GPIO1_CTRL + i, arizona->pdata.gpio_defaults[i]); } pm_runtime_enable(arizona->dev); /* Chip default */ if (!arizona->pdata.clk32k_src) arizona->pdata.clk32k_src = ARIZONA_32KZ_MCLK2; switch (arizona->pdata.clk32k_src) { case ARIZONA_32KZ_MCLK1: case ARIZONA_32KZ_MCLK2: regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1, ARIZONA_CLK_32K_SRC_MASK, arizona->pdata.clk32k_src - 1); break; case ARIZONA_32KZ_NONE: regmap_update_bits(arizona->regmap, ARIZONA_CLOCK_32K_1, ARIZONA_CLK_32K_SRC_MASK, 2); break; default: dev_err(arizona->dev, "Invalid 32kHz clock source: %d\n", arizona->pdata.clk32k_src); ret = -EINVAL; goto err_reset; } for (i = 0; i < ARIZONA_MAX_MICBIAS; i++) { if (!arizona->pdata.micbias[i].mV && !arizona->pdata.micbias[i].bypass) continue; /* Apply default for bypass mode */ if (!arizona->pdata.micbias[i].mV) arizona->pdata.micbias[i].mV = 2800; val = (arizona->pdata.micbias[i].mV - 1500) / 100; val <<= ARIZONA_MICB1_LVL_SHIFT; if (arizona->pdata.micbias[i].ext_cap) val |= ARIZONA_MICB1_EXT_CAP; if (arizona->pdata.micbias[i].discharge) val |= ARIZONA_MICB1_DISCH; if (arizona->pdata.micbias[i].fast_start) val |= ARIZONA_MICB1_RATE; if (arizona->pdata.micbias[i].bypass) val |= ARIZONA_MICB1_BYPASS; regmap_update_bits(arizona->regmap, ARIZONA_MIC_BIAS_CTRL_1 + i, ARIZONA_MICB1_LVL_MASK | ARIZONA_MICB1_DISCH | ARIZONA_MICB1_BYPASS | ARIZONA_MICB1_RATE, val); } for (i = 0; i < ARIZONA_MAX_INPUT; i++) { /* Default for both is 0 so noop with defaults */ val = arizona->pdata.dmic_ref[i] << ARIZONA_IN1_DMIC_SUP_SHIFT; val |= arizona->pdata.inmode[i] << ARIZONA_IN1_MODE_SHIFT; regmap_update_bits(arizona->regmap, ARIZONA_IN1L_CONTROL + (i * 8), ARIZONA_IN1_DMIC_SUP_MASK | ARIZONA_IN1_MODE_MASK, val); } for (i = 0; i < ARIZONA_MAX_OUTPUT; i++) { /* Default is 0 so noop with defaults */ if (arizona->pdata.out_mono[i]) val = ARIZONA_OUT1_MONO; else val = 0; regmap_update_bits(arizona->regmap, ARIZONA_OUTPUT_PATH_CONFIG_1L + (i * 8), ARIZONA_OUT1_MONO, val); } for (i = 0; i < ARIZONA_MAX_PDM_SPK; i++) { if (arizona->pdata.spk_mute[i]) regmap_update_bits(arizona->regmap, ARIZONA_PDM_SPK1_CTRL_1 + (i * 2), ARIZONA_SPK1_MUTE_ENDIAN_MASK | ARIZONA_SPK1_MUTE_SEQ1_MASK, arizona->pdata.spk_mute[i]); if (arizona->pdata.spk_fmt[i]) regmap_update_bits(arizona->regmap, ARIZONA_PDM_SPK1_CTRL_2 + (i * 2), ARIZONA_SPK1_FMT_MASK, arizona->pdata.spk_fmt[i]); } /* set virtual IRQs */ arizona->virq[0] = arizona->pdata.irq_base; arizona->virq[1] = arizona->pdata.irq_base + ARIZONA_NUM_IRQ; switch (arizona->pdata.mic_spk_clamp) { case ARIZONA_MIC_CLAMP_SPKLN: regmap_update_bits(arizona->regmap, ARIZONA_SPK_CTRL_2, 0x3c, 0xc); break; case ARIZONA_MIC_CLAMP_SPKLP: regmap_update_bits(arizona->regmap, ARIZONA_SPK_CTRL_2, 0x3c, 0x1c); break; case ARIZONA_MIC_CLAMP_SPKRN: regmap_update_bits(arizona->regmap, ARIZONA_SPK_CTRL_3, 0x3c, 0xc); break; case ARIZONA_MIC_CLAMP_SPKRP: regmap_update_bits(arizona->regmap, ARIZONA_SPK_CTRL_3, 0x3c, 0x1c); break; default: break; } /* Set up for interrupts */ ret = arizona_irq_init(arizona); if (ret != 0) goto err_reset; arizona_request_irq(arizona, ARIZONA_IRQ_CLKGEN_ERR, "CLKGEN error", arizona_clkgen_err, arizona); arizona_request_irq(arizona, ARIZONA_IRQ_OVERCLOCKED, "Overclocked", arizona_overclocked, arizona); arizona_request_irq(arizona, ARIZONA_IRQ_UNDERCLOCKED, "Underclocked", arizona_underclocked, arizona); switch (arizona->type) { case WM5102: ret = mfd_add_devices(arizona->dev, -1, wm5102_devs, ARRAY_SIZE(wm5102_devs), NULL, 0); break; case WM5110: ret = mfd_add_devices(arizona->dev, -1, wm5110_devs, ARRAY_SIZE(wm5110_devs), NULL, 0); break; } if (ret != 0) { dev_err(arizona->dev, "Failed to add subdevices: %d\n", ret); goto err_irq; } if (arizona->pdata.init_done) arizona->pdata.init_done(); #ifdef CONFIG_PM_RUNTIME regulator_disable(arizona->dcvdd); #endif return 0; err_irq: arizona_irq_exit(arizona); err_reset: if (arizona->pdata.reset) { gpio_set_value_cansleep(arizona->pdata.reset, 1); gpio_free(arizona->pdata.reset); } err_dcvdd: regulator_disable(arizona->dcvdd); err_enable: regulator_bulk_disable(arizona->num_core_supplies, arizona->core_supplies); err_early: mfd_remove_devices(dev); return ret; }