static void stop_oxnas_usb_ehci(struct oxnas_hcd *oxnas) { reset_control_assert(oxnas->rst_host); reset_control_assert(oxnas->rst_phya); reset_control_assert(oxnas->rst_phyb); if (oxnas->use_pllb) { clk_disable_unprepare(oxnas->phyref); clk_disable_unprepare(oxnas->refsrc); } clk_disable_unprepare(oxnas->clk); }
static void histb_pcie_host_disable(struct histb_pcie *hipcie) { reset_control_assert(hipcie->soft_reset); reset_control_assert(hipcie->sys_reset); reset_control_assert(hipcie->bus_reset); clk_disable_unprepare(hipcie->aux_clk); clk_disable_unprepare(hipcie->pipe_clk); clk_disable_unprepare(hipcie->sys_clk); clk_disable_unprepare(hipcie->bus_clk); if (gpio_is_valid(hipcie->reset_gpio)) gpio_set_value_cansleep(hipcie->reset_gpio, 0); }
static int st_ehci_platform_power_on(struct platform_device *dev) { struct usb_hcd *hcd = platform_get_drvdata(dev); struct st_ehci_platform_priv *priv = hcd_to_ehci_priv(hcd); int clk, ret; ret = reset_control_deassert(priv->pwr); if (ret) return ret; ret = reset_control_deassert(priv->rst); if (ret) goto err_assert_power; /* some SoCs don't have a dedicated 48Mhz clock, but those that do need the rate to be explicitly set */ if (priv->clk48) { ret = clk_set_rate(priv->clk48, 48000000); if (ret) goto err_assert_reset; } for (clk = 0; clk < USB_MAX_CLKS && priv->clks[clk]; clk++) { ret = clk_prepare_enable(priv->clks[clk]); if (ret) goto err_disable_clks; } ret = phy_init(priv->phy); if (ret) goto err_disable_clks; ret = phy_power_on(priv->phy); if (ret) goto err_exit_phy; return 0; err_exit_phy: phy_exit(priv->phy); err_disable_clks: while (--clk >= 0) clk_disable_unprepare(priv->clks[clk]); err_assert_reset: reset_control_assert(priv->rst); err_assert_power: reset_control_assert(priv->pwr); return ret; }
static void tegra_ahci_power_off(struct ahci_host_priv *hpriv) { struct tegra_ahci_priv *tegra = hpriv->plat_data; ahci_platform_disable_resources(hpriv); reset_control_assert(tegra->sata_rst); reset_control_assert(tegra->sata_oob_rst); reset_control_assert(tegra->sata_cold_rst); clk_disable_unprepare(tegra->sata_clk); tegra_powergate_power_off(TEGRA_POWERGATE_SATA); regulator_bulk_disable(ARRAY_SIZE(tegra->supplies), tegra->supplies); }
static int ehci_platform_remove(struct platform_device *dev) { struct usb_hcd *hcd = platform_get_drvdata(dev); struct usb_ehci_pdata *pdata = dev_get_platdata(&dev->dev); struct ehci_platform_priv *priv = hcd_to_ehci_priv(hcd); int clk; usb_remove_hcd(hcd); if (pdata->power_off) pdata->power_off(dev); if (priv->rst) reset_control_assert(priv->rst); for (clk = 0; clk < EHCI_MAX_CLKS && priv->clks[clk]; clk++) clk_put(priv->clks[clk]); usb_put_hcd(hcd); if (pdata == &ehci_platform_defaults) dev->dev.platform_data = NULL; return 0; }
/* Must be called with clk disabled, and returns with clk enabled */ int tegra_powergate_sequence_power_up(int id, struct clk *clk, struct reset_control *rst) { int ret; reset_control_assert(rst); ret = tegra_powergate_power_on(id); if (ret) goto err_power; ret = clk_prepare_enable(clk); if (ret) goto err_clk; udelay(10); ret = tegra_powergate_remove_clamping(id); if (ret) goto err_clamp; udelay(10); reset_control_deassert(rst); return 0; err_clamp: clk_disable_unprepare(clk); err_clk: tegra_powergate_power_off(id); err_power: return ret; }
static int dwc3_core_init_for_resume(struct dwc3 *dwc) { int ret; ret = reset_control_deassert(dwc->reset); if (ret) return ret; ret = clk_bulk_prepare(dwc->num_clks, dwc->clks); if (ret) goto assert_reset; ret = clk_bulk_enable(dwc->num_clks, dwc->clks); if (ret) goto unprepare_clks; ret = dwc3_core_init(dwc); if (ret) goto disable_clks; return 0; disable_clks: clk_bulk_disable(dwc->num_clks, dwc->clks); unprepare_clks: clk_bulk_unprepare(dwc->num_clks, dwc->clks); assert_reset: reset_control_assert(dwc->reset); return ret; }
static int _alt_hps2fpga_enable_set(struct altera_hps2fpga_data *priv, bool enable) { unsigned long flags; int ret; /* bring bridge out of reset */ if (enable) ret = reset_control_deassert(priv->bridge_reset); else ret = reset_control_assert(priv->bridge_reset); if (ret) return ret; /* Allow bridge to be visible to L3 masters or not */ if (priv->remap_mask) { spin_lock_irqsave(&l3_remap_lock, flags); l3_remap_shadow |= ALT_L3_REMAP_MPUZERO_MSK; if (enable) l3_remap_shadow |= priv->remap_mask; else l3_remap_shadow &= ~priv->remap_mask; ret = regmap_write(priv->l3reg, ALT_L3_REMAP_OFST, l3_remap_shadow); spin_unlock_irqrestore(&l3_remap_lock, flags); } return ret; }
static int dwc3_of_simple_remove(struct platform_device *pdev) { struct dwc3_of_simple *simple = platform_get_drvdata(pdev); struct device *dev = &pdev->dev; int i; of_platform_depopulate(dev); for (i = 0; i < simple->num_clocks; i++) { clk_disable_unprepare(simple->clks[i]); clk_put(simple->clks[i]); } simple->num_clocks = 0; if (!simple->pulse_resets) reset_control_assert(simple->resets); reset_control_put(simple->resets); pm_runtime_disable(dev); pm_runtime_put_noidle(dev); pm_runtime_set_suspended(dev); return 0; }
static void img_i2s_out_reset(struct img_i2s_out *i2s) { int i; u32 core_ctl, chan_ctl; core_ctl = img_i2s_out_readl(i2s, IMG_I2S_OUT_CTL) & ~IMG_I2S_OUT_CTL_ME_MASK & ~IMG_I2S_OUT_CTL_DATA_EN_MASK; if (!i2s->force_clk_active) core_ctl &= ~IMG_I2S_OUT_CTL_CLK_EN_MASK; chan_ctl = img_i2s_out_ch_readl(i2s, 0, IMG_I2S_OUT_CH_CTL) & ~IMG_I2S_OUT_CHAN_CTL_ME_MASK; reset_control_assert(i2s->rst); reset_control_deassert(i2s->rst); for (i = 0; i < i2s->max_i2s_chan; i++) img_i2s_out_ch_writel(i2s, i, chan_ctl, IMG_I2S_OUT_CH_CTL); for (i = 0; i < i2s->active_channels; i++) img_i2s_out_ch_enable(i2s, i); img_i2s_out_writel(i2s, core_ctl, IMG_I2S_OUT_CTL); img_i2s_out_enable(i2s); }
static void i2c_dw_prepare_recovery(struct i2c_adapter *adap) { struct dw_i2c_dev *dev = i2c_get_adapdata(adap); i2c_dw_disable(dev); reset_control_assert(dev->rst); i2c_dw_prepare_clk(dev, false); }
static int rockchip_dp_pre_init(struct rockchip_dp_device *dp) { reset_control_assert(dp->rst); usleep_range(10, 20); reset_control_deassert(dp->rst); return 0; }
static int socfpga_dwmac_set_phy_mode(struct socfpga_dwmac *dwmac) { struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr; int phymode = dwmac->interface; u32 reg_offset = dwmac->reg_offset; u32 reg_shift = dwmac->reg_shift; u32 ctrl, val, module; switch (phymode) { case PHY_INTERFACE_MODE_RGMII: case PHY_INTERFACE_MODE_RGMII_ID: val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII; break; case PHY_INTERFACE_MODE_MII: case PHY_INTERFACE_MODE_GMII: val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; break; default: dev_err(dwmac->dev, "bad phy mode %d\n", phymode); return -EINVAL; } /* Overwrite val to GMII if splitter core is enabled. The phymode here * is the actual phy mode on phy hardware, but phy interface from * EMAC core is GMII. */ if (dwmac->splitter_base) val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII; /* Assert reset to the enet controller before changing the phy mode */ if (dwmac->stmmac_rst) reset_control_assert(dwmac->stmmac_rst); regmap_read(sys_mgr_base_addr, reg_offset, &ctrl); ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift); ctrl |= val << reg_shift; if (dwmac->f2h_ptp_ref_clk) { ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2); regmap_read(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG, &module); module |= (SYSMGR_FPGAGRP_MODULE_EMAC << (reg_shift / 2)); regmap_write(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG, module); } else { ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2)); } regmap_write(sys_mgr_base_addr, reg_offset, ctrl); /* Deassert reset for the phy configuration to be sampled by * the enet controller, and operation to start in requested mode */ if (dwmac->stmmac_rst) reset_control_deassert(dwmac->stmmac_rst); return 0; }
static void sun6i_drc_unbind(struct device *dev, struct device *master, void *data) { struct sun6i_drc *drc = dev_get_drvdata(dev); clk_disable_unprepare(drc->mod_clk); clk_disable_unprepare(drc->bus_clk); reset_control_assert(drc->reset); }
/** * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the * DWC_otg driver * * @dev: Platform device * * This routine is called, for example, when the rmmod command is executed. The * device may or may not be electrically present. If it is present, the driver * stops device processing. Any resources used on behalf of this device are * freed. */ static int dwc2_driver_remove(struct platform_device *dev) { struct dwc2_hsotg *hsotg = platform_get_drvdata(dev); dwc2_debugfs_exit(hsotg); if (hsotg->hcd_enabled) dwc2_hcd_remove(hsotg); if (hsotg->gadget_enabled) dwc2_hsotg_remove(hsotg); if (hsotg->ll_hw_enabled) dwc2_lowlevel_hw_disable(hsotg); reset_control_assert(hsotg->reset); reset_control_assert(hsotg->reset_ecc); return 0; }
static void xhci_histb_host_disable(struct xhci_hcd_histb *histb) { reset_control_assert(histb->soft_reset); clk_disable_unprepare(histb->suspend_clk); clk_disable_unprepare(histb->pipe_clk); clk_disable_unprepare(histb->utmi_clk); clk_disable_unprepare(histb->bus_clk); }
static int dwc3_of_simple_suspend(struct device *dev) { struct dwc3_of_simple *simple = dev_get_drvdata(dev); if (simple->need_reset) reset_control_assert(simple->resets); return 0; }
static int p2wi_remove(struct platform_device *dev) { struct p2wi *p2wi = platform_get_drvdata(dev); reset_control_assert(p2wi->rstc); clk_disable_unprepare(p2wi->clk); i2c_del_adapter(&p2wi->adapter); return 0; }
static void socfpga_dwmac_exit(struct platform_device *pdev, void *priv) { struct socfpga_dwmac *dwmac = priv; /* On socfpga platform exit, assert and hold reset to the * enet controller - the default state after a hard reset. */ if (dwmac->stmmac_rst) reset_control_assert(dwmac->stmmac_rst); }
static void st_ehci_platform_power_off(struct platform_device *dev) { struct usb_hcd *hcd = platform_get_drvdata(dev); struct st_ehci_platform_priv *priv = hcd_to_ehci_priv(hcd); int clk; reset_control_assert(priv->pwr); reset_control_assert(priv->rst); phy_power_off(priv->phy); phy_exit(priv->phy); for (clk = USB_MAX_CLKS - 1; clk >= 0; clk--) if (priv->clks[clk]) clk_disable_unprepare(priv->clks[clk]); }
static int dw_wdt_drv_remove(struct platform_device *pdev) { struct dw_wdt *dw_wdt = platform_get_drvdata(pdev); watchdog_unregister_device(&dw_wdt->wdd); reset_control_assert(dw_wdt->rst); clk_disable_unprepare(dw_wdt->clk); return 0; }
static int uniphier_pciephy_exit(struct phy *phy) { struct uniphier_pciephy_priv *priv = phy_get_drvdata(phy); uniphier_pciephy_assert(priv); reset_control_assert(priv->rst); clk_disable_unprepare(priv->clk); return 0; }
static void sun8i_mixer_unbind(struct device *dev, struct device *master, void *data) { struct sun8i_mixer *mixer = dev_get_drvdata(dev); list_del(&mixer->engine.list); clk_disable_unprepare(mixer->mod_clk); clk_disable_unprepare(mixer->bus_clk); reset_control_assert(mixer->reset); }
static int sun6i_spi_runtime_suspend(struct device *dev) { struct spi_master *master = dev_get_drvdata(dev); struct sun6i_spi *sspi = spi_master_get_devdata(master); reset_control_assert(sspi->rstc); clk_disable_unprepare(sspi->mclk); clk_disable_unprepare(sspi->hclk); return 0; }
static int dw_apb_raw_uart_remove(struct platform_device *pdev) { reset_control_assert(dw_apb_port->rst); if (!IS_ERR(dw_apb_port->pclk)) clk_disable_unprepare(dw_apb_port->pclk); clk_disable_unprepare(dw_apb_port->sclk); kfree(dw_apb_port); return 0; }
static int st_rproc_stop(struct rproc *rproc) { struct st_rproc *ddata = rproc->priv; int sw_err = 0, pwr_err = 0; if (ddata->config->sw_reset) { sw_err = reset_control_assert(ddata->sw_reset); if (sw_err) dev_err(&rproc->dev, "Failed to assert S/W Reset\n"); } if (ddata->config->pwr_reset) { pwr_err = reset_control_assert(ddata->pwr_reset); if (pwr_err) dev_err(&rproc->dev, "Failed to assert Power Reset\n"); } clk_disable(ddata->clk); return sw_err ?: pwr_err; }
static int nvkm_device_tegra_power_down(struct nvkm_device_tegra *tdev) { reset_control_assert(tdev->rst); udelay(10); clk_disable_unprepare(tdev->clk_pwr); clk_disable_unprepare(tdev->clk); udelay(10); return regulator_disable(tdev->vdd); }
/* * Release a line */ static int of_platform_serial_remove(struct platform_device *ofdev) { struct of_serial_info *info = platform_get_drvdata(ofdev); serial8250_unregister_port(info->line); reset_control_assert(info->rst); if (info->clk) clk_disable_unprepare(info->clk); kfree(info); return 0; }
static int nvkm_device_tegra_power_up(struct nvkm_device_tegra *tdev) { int ret; if (tdev->vdd) { ret = regulator_enable(tdev->vdd); if (ret) goto err_power; } ret = clk_prepare_enable(tdev->clk); if (ret) goto err_clk; if (tdev->clk_ref) { ret = clk_prepare_enable(tdev->clk_ref); if (ret) goto err_clk_ref; } ret = clk_prepare_enable(tdev->clk_pwr); if (ret) goto err_clk_pwr; clk_set_rate(tdev->clk_pwr, 204000000); udelay(10); reset_control_assert(tdev->rst); udelay(10); if (!tdev->pdev->dev.pm_domain) { ret = tegra_powergate_remove_clamping(TEGRA_POWERGATE_3D); if (ret) goto err_clamp; udelay(10); } reset_control_deassert(tdev->rst); udelay(10); return 0; err_clamp: clk_disable_unprepare(tdev->clk_pwr); err_clk_pwr: if (tdev->clk_ref) clk_disable_unprepare(tdev->clk_ref); err_clk_ref: clk_disable_unprepare(tdev->clk); err_clk: if (tdev->vdd) regulator_disable(tdev->vdd); err_power: return ret; }
void clk_disable_usb_gxbaby(struct platform_device *pdev, const char *s_clock_name, unsigned long usb_peri_reg) { struct reset_control *usb_reset; if (0 == pdev->id) { usb_reset = p_clk_reset[pdev->id].usb_reset_usb_general; reset_control_assert(usb_reset); usb_reset = p_clk_reset[pdev->id].usb_reset_usb; reset_control_assert(usb_reset); usb_reset = p_clk_reset[pdev->id].usb_reset_usb_to_ddr; reset_control_assert(usb_reset); } else if (1 == pdev->id) { usb_reset = p_clk_reset[pdev->id].usb_reset_usb_general; reset_control_assert(usb_reset); usb_reset = p_clk_reset[pdev->id].usb_reset_usb; reset_control_assert(usb_reset); usb_reset = p_clk_reset[pdev->id].usb_reset_usb_to_ddr; reset_control_assert(usb_reset); } else { dev_err(&pdev->dev, "bad usb clk name.\n"); return; } return; }