static void printer_task_acquire(
rtems_printer_task_context *ctx,
rtems_interrupt_lock_context *lock_context
)
{
rtems_interrupt_lock_acquire( &ctx->lock, lock_context );
}
rtems_status_code qoriq_pic_set_priority(
rtems_vector_number vector,
int new_priority,
int *old_priority
)
{
rtems_status_code sc = RTEMS_SUCCESSFUL;
uint32_t old_vpr = 0;
if (bsp_interrupt_is_valid_vector(vector)) {
volatile qoriq_pic_src_cfg *src_cfg = get_src_cfg(vector);
if (QORIQ_PIC_PRIORITY_IS_VALID(new_priority)) {
rtems_interrupt_lock_context lock_context;
rtems_interrupt_lock_acquire(&lock, &lock_context);
old_vpr = src_cfg->vpr;
src_cfg->vpr = VPR_PRIORITY_SET(old_vpr, (uint32_t) new_priority);
rtems_interrupt_lock_release(&lock, &lock_context);
} else if (new_priority < 0) {
old_vpr = src_cfg->vpr;
} else {
sc = RTEMS_INVALID_PRIORITY;
}
} else {
sc = RTEMS_INVALID_ID;
}
if (old_priority != NULL) {
*old_priority = (int) VPR_PRIORITY_GET(old_vpr);
}
return sc;
}
static void test_interrupt_locks( void )
{
rtems_mode normal_interrupt_level = get_interrupt_level();
rtems_interrupt_lock initialized = RTEMS_INTERRUPT_LOCK_INITIALIZER;
rtems_interrupt_lock lock;
rtems_interrupt_lock_context lock_context;
rtems_interrupt_lock_initialize( &lock );
rtems_test_assert( memcmp( &lock, &initialized, sizeof( lock ) ) == 0 );
rtems_interrupt_lock_acquire( &lock, &lock_context );
rtems_test_assert( normal_interrupt_level != get_interrupt_level() );
rtems_interrupt_lock_release( &lock, &lock_context );
rtems_test_assert( normal_interrupt_level == get_interrupt_level() );
rtems_interrupt_lock_acquire_isr( &lock, &lock_context );
rtems_test_assert( normal_interrupt_level == get_interrupt_level() );
rtems_interrupt_lock_release_isr( &lock, &lock_context );
rtems_test_assert( normal_interrupt_level == get_interrupt_level() );
rtems_interrupt_lock_destroy( &lock );
rtems_interrupt_lock_destroy( &initialized );
}
void _Malloc_Deferred_free( void *p )
{
rtems_interrupt_lock_context lock_context;
rtems_interrupt_lock_acquire( &_Malloc_GC_lock, &lock_context );
rtems_chain_append_unprotected( &_Malloc_GC_list, (rtems_chain_node *) p );
rtems_interrupt_lock_release( &_Malloc_GC_lock, &lock_context );
}
void
rtems_trace_buffering_resume (void)
{
rtems_interrupt_lock_context lcontext;
rtems_interrupt_lock_acquire(&__rtld_tbg_lock, &lcontext);
__rtld_tbg_finished = false;
rtems_interrupt_lock_release(&__rtld_tbg_lock, &lcontext);
}
void
rtems_trace_buffering_start (void)
{
rtems_interrupt_lock_context lcontext;
rtems_interrupt_lock_acquire(&__rtld_tbg_lock, &lcontext);
__rtld_tbg_triggered = false;
__rtld_tbg_buffer_in = 0;
__rtld_tbg_finished = false;
rtems_interrupt_lock_release(&__rtld_tbg_lock, &lcontext);
}
bool
rtems_trace_buffering_finished (void)
{
rtems_interrupt_lock_context lcontext;
bool finished;
rtems_interrupt_lock_acquire(&__rtld_tbg_lock, &lcontext);
finished = __rtld_tbg_finished;
rtems_interrupt_lock_release(&__rtld_tbg_lock, &lcontext);
return finished;
}
bool
rtems_trace_buffering_triggered (void)
{
rtems_interrupt_lock_context lcontext;
bool triggered;
rtems_interrupt_lock_acquire(&__rtld_tbg_lock, &lcontext);
triggered = __rtld_tbg_triggered;
rtems_interrupt_lock_release(&__rtld_tbg_lock, &lcontext);
return triggered;
}
uint32_t
rtems_trace_buffering_buffer_in (void)
{
rtems_interrupt_lock_context lcontext;
uint32_t in;
rtems_interrupt_lock_acquire(&__rtld_tbg_lock, &lcontext);
in = __rtld_tbg_buffer_in;
rtems_interrupt_lock_release(&__rtld_tbg_lock, &lcontext);
return in;
}
static void *_Malloc_Get_deferred_free( void )
{
rtems_interrupt_lock_context lock_context;
void *p;
rtems_interrupt_lock_acquire( &_Malloc_GC_lock, &lock_context );
p = rtems_chain_get_unprotected( &_Malloc_GC_list );
rtems_interrupt_lock_release( &_Malloc_GC_lock, &lock_context );
return p;
}
static rtems_status_code pic_vector_enable(rtems_vector_number vector, uint32_t msk)
{
rtems_status_code sc = RTEMS_SUCCESSFUL;
if (bsp_interrupt_is_valid_vector(vector)) {
volatile qoriq_pic_src_cfg *src_cfg = get_src_cfg(vector);
rtems_interrupt_lock_context lock_context;
rtems_interrupt_lock_acquire(&lock, &lock_context);
src_cfg->vpr = (src_cfg->vpr & ~VPR_MSK) | msk;
rtems_interrupt_lock_release(&lock, &lock_context);
}
return sc;
}
void rtems_test_fatal_extension(
rtems_fatal_source source,
bool is_internal,
rtems_fatal_code code
)
{
#if defined(RTEMS_PROFILING)
rtems_interrupt_lock_context lock_context;
rtems_printer printer;
rtems_print_printer_printk( &printer );
/*
* Ensures to report only once on SMP machines and ensures that the report is
* output completely.
*/
rtems_interrupt_lock_acquire( &report_lock, &lock_context );
if ( !report_done ) {
report_done = true;
printk(
"\n*** PROFILING REPORT BEGIN %s ***\n",
rtems_test_name
);
rtems_profiling_report_xml(
rtems_test_name,
&printer,
1,
" "
);
printk(
"*** PROFILING REPORT END %s ***\n",
rtems_test_name
);
}
rtems_interrupt_lock_release( &report_lock, &lock_context );
#endif
(void) source;
(void) is_internal;
(void) code;
}
static void test_by_function_level(int fl, bool dirty)
{
rtems_interrupt_lock lock;
rtems_interrupt_lock_context lock_context;
int s;
uint64_t min;
uint64_t q1;
uint64_t q2;
uint64_t q3;
uint64_t max;
rtems_interrupt_lock_initialize(&lock, "test");
rtems_interrupt_lock_acquire(&lock, &lock_context);
for (s = 0; s < SAMPLES; ++s) {
call_at_level(fl, fl, s, dirty);
}
rtems_interrupt_lock_release(&lock, &lock_context);
rtems_interrupt_lock_destroy(&lock);
sort_t();
min = t[0];
q1 = t[(1 * SAMPLES) / 4];
q2 = t[SAMPLES / 2];
q3 = t[(3 * SAMPLES) / 4];
max = t[SAMPLES - 1];
printf(
" <Sample functionNestLevel=\"%i\">\n"
" <Min unit=\"ns\">%" PRIu64 "</Min>"
"<Q1 unit=\"ns\">%" PRIu64 "</Q1>"
"<Q2 unit=\"ns\">%" PRIu64 "</Q2>"
"<Q3 unit=\"ns\">%" PRIu64 "</Q3>"
"<Max unit=\"ns\">%" PRIu64 "</Max>\n"
" </Sample>\n",
fl,
rtems_counter_ticks_to_nanoseconds(min),
rtems_counter_ticks_to_nanoseconds(q1),
rtems_counter_ticks_to_nanoseconds(q2),
rtems_counter_ticks_to_nanoseconds(q3),
rtems_counter_ticks_to_nanoseconds(max)
);
}
static void bsp_interrupt_server_trigger(void *arg)
{
rtems_interrupt_lock_context lock_context;
bsp_interrupt_server_entry *e = arg;
bsp_interrupt_vector_disable(e->vector);
rtems_interrupt_lock_acquire(&bsp_interrupt_server_lock, &lock_context);
if (rtems_chain_is_node_off_chain(&e->node)) {
rtems_chain_append_unprotected(&bsp_interrupt_server_chain, &e->node);
} else {
++bsp_interrupt_server_errors;
}
rtems_interrupt_lock_release(&bsp_interrupt_server_lock, &lock_context);
rtems_event_system_send(bsp_interrupt_server_id, RTEMS_EVENT_SYSTEM_SERVER);
}
rtems_status_code
rtems_disk_release(rtems_disk_device *dd)
{
rtems_interrupt_level level;
dev_t dev = dd->dev;
unsigned uses = 0;
bool deleted = false;
rtems_interrupt_lock_acquire(&diskdevs_lock, level);
uses = --dd->uses;
deleted = dd->deleted;
rtems_interrupt_lock_release(&diskdevs_lock, level);
if (uses == 0 && deleted) {
rtems_disk_delete(dev);
}
return RTEMS_SUCCESSFUL;
}
NS16550_STATIC int ns16550_negate_DTR(int minor)
{
uint32_t pNS16550;
rtems_interrupt_lock_context lock_context;
NS16550Context *pns16550Context;
setRegister_f setReg;
pns16550Context=(NS16550Context *) Console_Port_Data[minor].pDeviceContext;
pNS16550 = Console_Port_Tbl[minor]->ulCtrlPort1;
setReg = Console_Port_Tbl[minor]->setRegister;
/*
* Negate DTR
*/
rtems_interrupt_lock_acquire(&ns16550_lock, &lock_context);
pns16550Context->ucModemCtrl&=~SP_MODEM_DTR;
(*setReg)(pNS16550, NS16550_MODEM_CONTROL,pns16550Context->ucModemCtrl);
rtems_interrupt_lock_release(&ns16550_lock, &lock_context);
return 0;
}
/**
* @brief Polled write for NS16550.
*/
void ns16550_outch_polled(console_tbl *c, char out)
{
uintptr_t port = c->ulCtrlPort1;
getRegister_f get = c->getRegister;
setRegister_f set = c->setRegister;
uint32_t status = 0;
rtems_interrupt_lock_context lock_context;
/* Save port interrupt mask */
uint32_t interrupt_mask = get( port, NS16550_INTERRUPT_ENABLE);
/* Disable port interrupts */
ns16550_enable_interrupts( c, NS16550_DISABLE_ALL_INTR);
while (true) {
/* Try to transmit the character in a critical section */
rtems_interrupt_lock_acquire(&ns16550_lock, &lock_context);
/* Read the transmitter holding register and check it */
status = get( port, NS16550_LINE_STATUS);
if ((status & SP_LSR_THOLD) != 0) {
/* Transmit character */
set( port, NS16550_TRANSMIT_BUFFER, out);
/* Finished */
rtems_interrupt_lock_release(&ns16550_lock, &lock_context);
break;
} else {
rtems_interrupt_lock_release(&ns16550_lock, &lock_context);
}
/* Wait for transmitter holding register to be empty */
do {
status = get( port, NS16550_LINE_STATUS);
} while ((status & SP_LSR_THOLD) == 0);
}
/* Restore port interrupt mask */
set( port, NS16550_INTERRUPT_ENABLE, interrupt_mask);
}
rtems_disk_device *
rtems_disk_obtain(dev_t dev)
{
rtems_status_code sc = RTEMS_SUCCESSFUL;
rtems_disk_device *dd = NULL;
rtems_interrupt_level level;
rtems_interrupt_lock_acquire(&diskdevs_lock, level);
if (!diskdevs_protected) {
/* Frequent and quickest case */
dd = get_disk_entry(dev, false);
rtems_interrupt_lock_release(&diskdevs_lock, level);
} else {
rtems_interrupt_lock_release(&diskdevs_lock, level);
sc = disk_lock();
if (sc == RTEMS_SUCCESSFUL) {
dd = get_disk_entry(dev, false);
disk_unlock();
}
}
return dd;
}
static void test_timing(void)
{
rtems_interrupt_lock lock;
rtems_interrupt_lock_context lock_context;
size_t data_size = sizeof(data);
uint64_t d[3];
uint32_t cache_level;
size_t cache_size;
rtems_interrupt_lock_initialize(&lock, "test");
printf(
"data cache line size %zi bytes\n"
"data cache size %zi bytes\n",
rtems_cache_get_data_line_size(),
rtems_cache_get_data_cache_size(0)
);
cache_level = 1;
cache_size = rtems_cache_get_data_cache_size(cache_level);
while (cache_size > 0) {
printf(
"data cache level %" PRIu32 " size %zi bytes\n",
cache_level,
cache_size
);
++cache_level;
cache_size = rtems_cache_get_data_cache_size(cache_level);
}
rtems_interrupt_lock_acquire(&lock, &lock_context);
d[0] = load();
d[1] = load();
rtems_cache_flush_entire_data();
d[2] = load();
rtems_interrupt_lock_release(&lock, &lock_context);
printf(
"load %zi bytes with flush entire data\n"
" duration with normal cache %" PRIu64 " ns\n"
" duration with warm cache %" PRIu64 " ns\n"
" duration with flushed cache %" PRIu64 " ns\n",
data_size,
d[0],
d[1],
d[2]
);
rtems_interrupt_lock_acquire(&lock, &lock_context);
d[0] = load();
d[1] = load();
rtems_cache_flush_multiple_data_lines(&data[0], sizeof(data));
d[2] = load();
rtems_interrupt_lock_release(&lock, &lock_context);
printf(
"load %zi bytes with flush multiple data\n"
" duration with normal cache %" PRIu64 " ns\n"
" duration with warm cache %" PRIu64 " ns\n"
" duration with flushed cache %" PRIu64 " ns\n",
data_size,
d[0],
d[1],
d[2]
);
rtems_interrupt_lock_acquire(&lock, &lock_context);
d[0] = load();
d[1] = load();
rtems_cache_invalidate_multiple_data_lines(&data[0], sizeof(data));
d[2] = load();
rtems_interrupt_lock_release(&lock, &lock_context);
printf(
"load %zi bytes with invalidate multiple data\n"
" duration with normal cache %" PRIu64 " ns\n"
" duration with warm cache %" PRIu64 " ns\n"
" duration with invalidated cache %" PRIu64 " ns\n",
data_size,
d[0],
d[1],
d[2]
);
rtems_interrupt_lock_acquire(&lock, &lock_context);
d[0] = store();
d[1] = store();
rtems_cache_flush_entire_data();
d[2] = store();
rtems_interrupt_lock_release(&lock, &lock_context);
printf(
"store %zi bytes with flush entire data\n"
" duration with normal cache %" PRIu64 " ns\n"
" duration with warm cache %" PRIu64 " ns\n"
" duration with flushed cache %" PRIu64 " ns\n",
data_size,
d[0],
d[1],
d[2]
);
rtems_interrupt_lock_acquire(&lock, &lock_context);
d[0] = store();
d[1] = store();
rtems_cache_flush_multiple_data_lines(&data[0], sizeof(data));
d[2] = store();
rtems_interrupt_lock_release(&lock, &lock_context);
printf(
"store %zi bytes with flush multiple data\n"
" duration with normal cache %" PRIu64 " ns\n"
" duration with warm cache %" PRIu64 " ns\n"
" duration with flushed cache %" PRIu64 " ns\n",
data_size,
d[0],
d[1],
d[2]
);
rtems_interrupt_lock_acquire(&lock, &lock_context);
d[0] = store();
d[1] = store();
rtems_cache_invalidate_multiple_data_lines(&data[0], sizeof(data));
d[2] = store();
rtems_interrupt_lock_release(&lock, &lock_context);
printf(
"store %zi bytes with invalidate multiple data\n"
" duration with normal cache %" PRIu64 " ns\n"
" duration with warm cache %" PRIu64 " ns\n"
" duration with invalidated cache %" PRIu64 " ns\n",
data_size,
d[0],
d[1],
d[2]
);
printf(
"instruction cache line size %zi bytes\n"
"instruction cache size %zi bytes\n",
rtems_cache_get_instruction_line_size(),
rtems_cache_get_instruction_cache_size(0)
);
cache_level = 1;
cache_size = rtems_cache_get_instruction_cache_size(cache_level);
while (cache_size > 0) {
printf(
"instruction cache level %" PRIu32 " size %zi bytes\n",
cache_level,
cache_size
);
++cache_level;
cache_size = rtems_cache_get_instruction_cache_size(cache_level);
}
rtems_interrupt_lock_acquire(&lock, &lock_context);
d[0] = do_some_work();
d[1] = do_some_work();
rtems_cache_invalidate_entire_instruction();
d[2] = do_some_work();
rtems_interrupt_lock_release(&lock, &lock_context);
printf(
"invalidate entire instruction\n"
" duration with normal cache %" PRIu64 " ns\n"
" duration with warm cache %" PRIu64 " ns\n"
" duration with invalidated cache %" PRIu64 " ns\n",
d[0],
d[1],
d[2]
);
rtems_interrupt_lock_acquire(&lock, &lock_context);
d[0] = do_some_work();
d[1] = do_some_work();
rtems_cache_invalidate_multiple_instruction_lines(do_some_work, 4096);
d[2] = do_some_work();
rtems_interrupt_lock_release(&lock, &lock_context);
printf(
"invalidate multiple instruction\n"
" duration with normal cache %" PRIu64 " ns\n"
" duration with warm cache %" PRIu64 " ns\n"
" duration with invalidated cache %" PRIu64 " ns\n",
d[0],
d[1],
d[2]
);
rtems_interrupt_lock_destroy(&lock);
}
static void test_data_flush_and_invalidate(void)
{
if (rtems_cache_get_data_line_size() > 0) {
rtems_interrupt_lock lock;
rtems_interrupt_lock_context lock_context;
volatile int *vdata = &data[0];
int n = 32;
int i;
size_t data_size = n * sizeof(data[0]);
bool write_through;
printf("data cache flush and invalidate test\n");
rtems_interrupt_lock_initialize(&lock, "test");
rtems_interrupt_lock_acquire(&lock, &lock_context);
for (i = 0; i < n; ++i) {
vdata[i] = i;
}
rtems_cache_flush_multiple_data_lines(&data[0], data_size);
for (i = 0; i < n; ++i) {
rtems_test_assert(vdata[i] == i);
}
for (i = 0; i < n; ++i) {
vdata[i] = ~i;
}
rtems_cache_invalidate_multiple_data_lines(&data[0], data_size);
write_through = vdata[0] == ~0;
if (write_through) {
for (i = 0; i < n; ++i) {
rtems_test_assert(vdata[i] == ~i);
}
} else {
for (i = 0; i < n; ++i) {
rtems_test_assert(vdata[i] == i);
}
}
for (i = 0; i < n; ++i) {
vdata[i] = ~i;
}
rtems_cache_flush_multiple_data_lines(&data[0], data_size);
rtems_cache_invalidate_multiple_data_lines(&data[0], data_size);
for (i = 0; i < n; ++i) {
rtems_test_assert(vdata[i] == ~i);
}
rtems_interrupt_lock_release(&lock, &lock_context);
rtems_interrupt_lock_destroy(&lock);
printf(
"data cache operations by line passed the test (%s cache detected)\n",
write_through ? "write-through" : "copy-back"
);
} else {
printf(
"skip data cache flush and invalidate test"
" due to cache line size of zero\n"
);
}
/* Make sure these are nops */
rtems_cache_flush_multiple_data_lines(NULL, 0);
rtems_cache_invalidate_multiple_data_lines(NULL, 0);
}
int ns16550_set_attributes(
int minor,
const struct termios *t
)
{
uint32_t pNS16550;
uint32_t ulBaudDivisor;
uint8_t ucLineControl;
uint32_t baud_requested;
setRegister_f setReg;
rtems_interrupt_lock_context lock_context;
const console_tbl *c = Console_Port_Tbl [minor];
pNS16550 = c->ulCtrlPort1;
setReg = c->setRegister;
/*
* Calculate the baud rate divisor
*
* Assert ensures there is no division by 0.
*/
baud_requested = rtems_termios_baud_to_number(t->c_cflag);
_Assert( baud_requested != 0 );
ulBaudDivisor = NS16550_GetBaudDivisor(c, baud_requested);
ucLineControl = 0;
/*
* Parity
*/
if (t->c_cflag & PARENB) {
ucLineControl |= SP_LINE_PAR;
if (!(t->c_cflag & PARODD))
ucLineControl |= SP_LINE_ODD;
}
/*
* Character Size
*/
if (t->c_cflag & CSIZE) {
switch (t->c_cflag & CSIZE) {
case CS5: ucLineControl |= FIVE_BITS; break;
case CS6: ucLineControl |= SIX_BITS; break;
case CS7: ucLineControl |= SEVEN_BITS; break;
case CS8: ucLineControl |= EIGHT_BITS; break;
}
} else {
ucLineControl |= EIGHT_BITS; /* default to 9600,8,N,1 */
}
/*
* Stop Bits
*/
if (t->c_cflag & CSTOPB) {
ucLineControl |= SP_LINE_STOP; /* 2 stop bits */
} else {
; /* 1 stop bit */
}
/*
* Now actually set the chip
*/
rtems_interrupt_lock_acquire(&ns16550_lock, &lock_context);
/*
* Set the baud rate
*
* NOTE: When the Divisor Latch Access Bit (DLAB) is set to 1,
* the transmit buffer and interrupt enable registers
* turn into the LSB and MSB divisor latch registers.
*/
(*setReg)(pNS16550, NS16550_LINE_CONTROL, SP_LINE_DLAB);
(*setReg)(pNS16550, NS16550_TRANSMIT_BUFFER, ulBaudDivisor&0xff);
(*setReg)(pNS16550, NS16550_INTERRUPT_ENABLE, (ulBaudDivisor>>8)&0xff);
/*
* Now write the line control
*/
(*setReg)(pNS16550, NS16550_LINE_CONTROL, ucLineControl );
rtems_interrupt_lock_release(&ns16550_lock, &lock_context);
return 0;
}
static void chain_acquire( rtems_interrupt_lock_context *lock_context )
{
rtems_interrupt_lock_acquire( &chain_lock, lock_context );
}