static int __init ip22_setup(void) { char *ctype; #ifdef CONFIG_KGDB char *kgdb_ttyd; #endif board_be_init = ip22_be_init; ip22_time_init(); /* Init the INDY HPC I/O controller. Need to call this before * f*****g with the memory controller because it needs to know the * boardID and whether this is a Guiness or a FullHouse machine. */ sgihpc_init(); /* Init INDY memory controller. */ sgimc_init(); #ifdef CONFIG_BOARD_SCACHE /* Now enable boardcaches, if any. */ indy_sc_init(); #endif /* Set EISA IO port base for Indigo2 */ set_io_port_base(KSEG1ADDR(0x00080000)); /* ARCS console environment variable is set to "g?" for * graphics console, it is set to "d" for the first serial * line and "d2" for the second serial line. */ ctype = ArcGetEnvironmentVariable("console"); if (ctype && *ctype == 'd') { static char options[8]; char *baud = ArcGetEnvironmentVariable("dbaud"); if (baud) strcpy(options, baud); add_preferred_console("ttyS", *(ctype + 1) == '2' ? 1 : 0, baud ? options : NULL); } else if (!ctype || *ctype != 'g') { /* Use ARC if we don't want serial ('d') or Newport ('g'). */ prom_flags |= PROM_FLAG_USE_AS_CONSOLE; add_preferred_console("arc", 0, NULL); } #ifdef CONFIG_KGDB kgdb_ttyd = prom_getcmdline(); if ((kgdb_ttyd = strstr(kgdb_ttyd, "kgdb=ttyd")) != NULL) { int line; kgdb_ttyd += strlen("kgdb=ttyd"); if (*kgdb_ttyd != '1' && *kgdb_ttyd != '2') printk(KERN_INFO "KGDB: Uknown serial line /dev/ttyd%c" ", falling back to /dev/ttyd1\n", *kgdb_ttyd); line = *kgdb_ttyd == '2' ? 0 : 1; printk(KERN_INFO "KGDB: Using serial line /dev/ttyd%d for " "session\n", line ? 1 : 2); rs_kgdb_hook(line); printk(KERN_INFO "KGDB: Using serial line /dev/ttyd%d for " "session, please connect your debugger\n", line ? 1:2); remote_debug = 1; /* Breakpoints and stuff are in sgi_irq_setup() */ } #endif #ifdef CONFIG_VT #ifdef CONFIG_SGI_NEWPORT_CONSOLE if (ctype && *ctype == 'g'){ ULONG *gfxinfo; ULONG * (*__vec)(void) = (void *) (long) *((_PULONG *)(long)((PROMBLOCK)->pvector + 0x20)); gfxinfo = __vec(); sgi_gfxaddr = ((gfxinfo[1] >= 0xa0000000 && gfxinfo[1] <= 0xc0000000) ? gfxinfo[1] - 0xa0000000 : 0); /* newport addresses? */ if (sgi_gfxaddr == 0x1f0f0000 || sgi_gfxaddr == 0x1f4f0000) { conswitchp = &newport_con; } } #endif #endif return 0; }
void __init prom_init(void) { mips_display_message("LINUX"); /* * early setup of _pcictrl_bonito so that we can determine * the system controller on a CORE_EMUL board */ _pcictrl_bonito = (unsigned long)ioremap(BONITO_REG_BASE, BONITO_REG_SIZE); mips_revision_corid = MIPS_REVISION_CORID; if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) { if (BONITO_PCIDID == 0x0001df53 || BONITO_PCIDID == 0x0003df53) mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON; else mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC; } mips_revision_sconid = MIPS_REVISION_SCONID; if (mips_revision_sconid == MIPS_REVISION_SCON_OTHER) { switch (mips_revision_corid) { case MIPS_REVISION_CORID_QED_RM5261: case MIPS_REVISION_CORID_CORE_LV: case MIPS_REVISION_CORID_CORE_FPGA: case MIPS_REVISION_CORID_CORE_FPGAR2: mips_revision_sconid = MIPS_REVISION_SCON_GT64120; break; case MIPS_REVISION_CORID_CORE_EMUL_BON: case MIPS_REVISION_CORID_BONITO64: case MIPS_REVISION_CORID_CORE_20K: mips_revision_sconid = MIPS_REVISION_SCON_BONITO; break; case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: case MIPS_REVISION_CORID_CORE_24K: /* * SOCit/ROCit support is essentially identical * but make an attempt to distinguish them */ mips_revision_sconid = MIPS_REVISION_SCON_SOCIT; break; case MIPS_REVISION_CORID_CORE_FPGA3: case MIPS_REVISION_CORID_CORE_FPGA4: case MIPS_REVISION_CORID_CORE_FPGA5: case MIPS_REVISION_CORID_CORE_EMUL_MSC: default: /* See above */ mips_revision_sconid = MIPS_REVISION_SCON_ROCIT; break; } } switch (mips_revision_sconid) { u32 start, map, mask, data; case MIPS_REVISION_SCON_GT64120: /* * Setup the North bridge to do Master byte-lane swapping * when running in bigendian. */ _pcictrl_gt64120 = (unsigned long)ioremap(MIPS_GT_BASE, 0x2000); #ifdef CONFIG_CPU_LITTLE_ENDIAN GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT | GT_PCI0_CMD_SBYTESWAP_BIT); #else GT_WRITE(GT_PCI0_CMD_OFS, 0); #endif /* Fix up PCI I/O mapping if necessary (for Atlas). */ start = GT_READ(GT_PCI0IOLD_OFS); map = GT_READ(GT_PCI0IOREMAP_OFS); if ((start & map) != 0) { map &= ~start; GT_WRITE(GT_PCI0IOREMAP_OFS, map); } set_io_port_base(MALTA_GT_PORT_BASE); break; case MIPS_REVISION_SCON_BONITO: _pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE); /* * Disable Bonito IOBC. */ BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); /* * Setup the North bridge to do Master byte-lane swapping * when running in bigendian. */ #ifdef CONFIG_CPU_LITTLE_ENDIAN BONITO_BONGENCFG = BONITO_BONGENCFG & ~(BONITO_BONGENCFG_MSTRBYTESWAP | BONITO_BONGENCFG_BYTESWAP); #else BONITO_BONGENCFG = BONITO_BONGENCFG | BONITO_BONGENCFG_MSTRBYTESWAP | BONITO_BONGENCFG_BYTESWAP; #endif set_io_port_base(MALTA_BONITO_PORT_BASE); break; case MIPS_REVISION_SCON_SOCIT: case MIPS_REVISION_SCON_ROCIT: _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); mips_pci_controller: mb(); MSC_READ(MSC01_PCI_CFG, data); MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT); wmb(); /* Fix up lane swapping. */ #ifdef CONFIG_CPU_LITTLE_ENDIAN MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); #else MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF | MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF | MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF); #endif /* Fix up target memory mapping. */ MSC_READ(MSC01_PCI_BAR0, mask); MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK); /* Don't handle target retries indefinitely. */ if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) == MSC01_PCI_CFG_MAXRTRY_MSK) data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK << MSC01_PCI_CFG_MAXRTRY_SHF)) | ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) << MSC01_PCI_CFG_MAXRTRY_SHF); wmb(); MSC_WRITE(MSC01_PCI_CFG, data); mb(); set_io_port_base(MALTA_MSC_PORT_BASE); break; case MIPS_REVISION_SCON_SOCITSC: case MIPS_REVISION_SCON_SOCITSCP: _pcictrl_msc = (unsigned long)ioremap(MIPS_SOCITSC_PCI_REG_BASE, 0x2000); goto mips_pci_controller; default: /* Unknown system controller */ mips_display_message("SC Error"); while (1); /* We die here... */ } board_nmi_handler_setup = mips_nmi_setup; board_ejtag_handler_setup = mips_ejtag_setup; fw_init_cmdline(); fw_meminit(); #ifdef CONFIG_SERIAL_8250_CONSOLE console_config(); #endif /* Early detection of CMP support */ if (gcmp_probe(GCMP_BASE_ADDR, GCMP_ADDRSPACE_SZ)) if (!register_cmp_smp_ops()) return; if (!register_vsmp_smp_ops()) return; #ifdef CONFIG_MIPS_MT_SMTC register_smp_ops(&msmtc_smp_ops); #endif }
/* * Initialize the Octeon PCI controller */ static int __init octeon_pci_setup(void) { union cvmx_npi_mem_access_subidx mem_access; int index; /* Disable PCI if instructed on the command line */ if (pci_disable) return 0; /* Only these chips have PCI */ if (octeon_has_feature(OCTEON_FEATURE_PCIE)) return 0; /* Point pcibios_map_irq() to the PCI version of it */ octeon_pcibios_map_irq = octeon_pci_pcibios_map_irq; /* Only use the big bars on chips that support it */ if (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_SMALL; else octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG; /* PCI I/O and PCI MEM values */ set_io_port_base(OCTEON_PCI_IOSPACE_BASE); ioport_resource.start = 0; ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1; if (!octeon_is_pci_host()) { pr_notice("Not in host mode, PCI Controller not initialized\n"); return 0; } pr_notice("%s Octeon big bar support\n", (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) ? "Enabling" : "Disabling"); octeon_pci_initialize(); mem_access.u64 = 0; mem_access.s.esr = 1; /* Endian-Swap on read. */ mem_access.s.esw = 1; /* Endian-Swap on write. */ mem_access.s.nsr = 0; /* No-Snoop on read. */ mem_access.s.nsw = 0; /* No-Snoop on write. */ mem_access.s.ror = 0; /* Relax Read on read. */ mem_access.s.row = 0; /* Relax Order on write. */ mem_access.s.ba = 0; /* PCI Address bits [63:36]. */ cvmx_write_csr(CVMX_NPI_MEM_ACCESS_SUBID3, mem_access.u64); /* * Remap the Octeon BAR 2 above all 32 bit devices * (0x8000000000ul). This is done here so it is remapped * before the readl()'s below. We don't want BAR2 overlapping * with BAR0/BAR1 during these reads. */ octeon_npi_write32(CVMX_NPI_PCI_CFG08, (u32)(OCTEON_BAR2_PCI_ADDRESS & 0xffffffffull)); octeon_npi_write32(CVMX_NPI_PCI_CFG09, (u32)(OCTEON_BAR2_PCI_ADDRESS >> 32)); if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) { /* Remap the Octeon BAR 0 to 0-2GB */ octeon_npi_write32(CVMX_NPI_PCI_CFG04, 0); octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0); /* * Remap the Octeon BAR 1 to map 2GB-4GB (minus the * BAR 1 hole). */ octeon_npi_write32(CVMX_NPI_PCI_CFG06, 2ul << 30); octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0); /* BAR1 movable mappings set for identity mapping */ octeon_bar1_pci_phys = 0x80000000ull; for (index = 0; index < 32; index++) { union cvmx_pci_bar1_indexx bar1_index; bar1_index.u32 = 0; /* Address bits[35:22] sent to L2C */ bar1_index.s.addr_idx = (octeon_bar1_pci_phys >> 22) + index; /* Don't put PCI accesses in L2. */ bar1_index.s.ca = 1; /* Endian Swap Mode */ bar1_index.s.end_swp = 1; /* Set '1' when the selected address range is valid. */ bar1_index.s.addr_v = 1; octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), bar1_index.u32); } /* Devices go after BAR1 */ octeon_pci_mem_resource.start = OCTEON_PCI_MEMSPACE_OFFSET + (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20); octeon_pci_mem_resource.end = octeon_pci_mem_resource.start + (1ul << 30); } else {
void __init prom_init(void) { prom_argc = fw_arg0; _prom_argv = (int *) fw_arg1; _prom_envp = (int *) fw_arg2; mips_display_message("LINUX"); #ifdef CONFIG_MIPS_SEAD set_io_port_base(KSEG1); #else /* * early setup of _pcictrl_bonito so that we can determine * the system controller on a CORE_EMUL board */ _pcictrl_bonito = (unsigned long)ioremap(BONITO_REG_BASE, BONITO_REG_SIZE); mips_revision_corid = MIPS_REVISION_CORID; if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) { if (BONITO_PCIDID == 0x0001df53 || BONITO_PCIDID == 0x0003df53) mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON; else mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC; } switch(mips_revision_corid) { u32 start, map, mask, data; case MIPS_REVISION_CORID_QED_RM5261: case MIPS_REVISION_CORID_CORE_LV: case MIPS_REVISION_CORID_CORE_FPGA: case MIPS_REVISION_CORID_CORE_FPGAR2: /* * Setup the North bridge to do Master byte-lane swapping * when running in bigendian. */ _pcictrl_gt64120 = (unsigned long)ioremap(MIPS_GT_BASE, 0x2000); #ifdef CONFIG_CPU_LITTLE_ENDIAN GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT | GT_PCI0_CMD_SBYTESWAP_BIT); #else GT_WRITE(GT_PCI0_CMD_OFS, 0); #endif /* Fix up PCI I/O mapping if necessary (for Atlas). */ start = GT_READ(GT_PCI0IOLD_OFS); map = GT_READ(GT_PCI0IOREMAP_OFS); if ((start & map) != 0) { map &= ~start; GT_WRITE(GT_PCI0IOREMAP_OFS, map); } set_io_port_base(MALTA_GT_PORT_BASE); break; case MIPS_REVISION_CORID_CORE_EMUL_BON: case MIPS_REVISION_CORID_BONITO64: case MIPS_REVISION_CORID_CORE_20K: _pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE); /* * Disable Bonito IOBC. */ BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); /* * Setup the North bridge to do Master byte-lane swapping * when running in bigendian. */ #ifdef CONFIG_CPU_LITTLE_ENDIAN BONITO_BONGENCFG = BONITO_BONGENCFG & ~(BONITO_BONGENCFG_MSTRBYTESWAP | BONITO_BONGENCFG_BYTESWAP); #else BONITO_BONGENCFG = BONITO_BONGENCFG | BONITO_BONGENCFG_MSTRBYTESWAP | BONITO_BONGENCFG_BYTESWAP; #endif set_io_port_base(MALTA_BONITO_PORT_BASE); break; case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: case MIPS_REVISION_CORID_CORE_FPGA3: case MIPS_REVISION_CORID_CORE_24K: case MIPS_REVISION_CORID_CORE_EMUL_MSC: _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); mb(); MSC_READ(MSC01_PCI_CFG, data); MSC_WRITE(MSC01_PCI_CFG, data & ~MSC01_PCI_CFG_EN_BIT); wmb(); /* Fix up lane swapping. */ #ifdef CONFIG_CPU_LITTLE_ENDIAN MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); #else MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF | MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF | MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF); #endif /* Fix up target memory mapping. */ MSC_READ(MSC01_PCI_BAR0, mask); MSC_WRITE(MSC01_PCI_P2SCMSKL, mask & MSC01_PCI_BAR0_SIZE_MSK); /* Don't handle target retries indefinitely. */ if ((data & MSC01_PCI_CFG_MAXRTRY_MSK) == MSC01_PCI_CFG_MAXRTRY_MSK) data = (data & ~(MSC01_PCI_CFG_MAXRTRY_MSK << MSC01_PCI_CFG_MAXRTRY_SHF)) | ((MSC01_PCI_CFG_MAXRTRY_MSK - 1) << MSC01_PCI_CFG_MAXRTRY_SHF); wmb(); MSC_WRITE(MSC01_PCI_CFG, data); mb(); set_io_port_base(MALTA_MSC_PORT_BASE); break; default: /* Unknown Core card */ mips_display_message("CC Error"); while(1); /* We die here... */ } #endif board_nmi_handler_setup = mips_nmi_setup; board_ejtag_handler_setup = mips_ejtag_setup; pr_info("\nLINUX started...\n"); prom_init_cmdline(); prom_meminit(); #ifdef CONFIG_SERIAL_8250_CONSOLE console_config(); #endif }
static int __init vr41xx_pciu_init(void) { struct pci_controller_unit_setup *setup; struct pci_master_address_conversion *master; struct pci_target_address_conversion *target; struct pci_mailbox_address *mailbox; struct pci_target_address_window *window; unsigned long vtclock, pci_clock_max; uint32_t val; setup = &vr41xx_pci_controller_unit_setup; if (request_mem_region(PCIU_BASE, PCIU_SIZE, "PCIU") == NULL) return -EBUSY; pciu_base = ioremap(PCIU_BASE, PCIU_SIZE); if (pciu_base == NULL) { release_mem_region(PCIU_BASE, PCIU_SIZE); return -EBUSY; } /* Disable PCI interrupt */ vr41xx_disable_pciint(); /* Supply VTClock to PCIU */ vr41xx_supply_clock(PCIU_CLOCK); /* Dummy write, waiting for supply of VTClock. */ vr41xx_disable_pciint(); /* Select PCI clock */ if (setup->pci_clock_max != 0) pci_clock_max = setup->pci_clock_max; else pci_clock_max = PCI_CLOCK_MAX; vtclock = vr41xx_get_vtclock_frequency(); if (vtclock < pci_clock_max) pciu_write(PCICLKSELREG, EQUAL_VTCLOCK); else if ((vtclock / 2) < pci_clock_max) pciu_write(PCICLKSELREG, HALF_VTCLOCK); else if (current_cpu_data.processor_id >= PRID_VR4131_REV2_1 && (vtclock / 3) < pci_clock_max) pciu_write(PCICLKSELREG, ONE_THIRD_VTCLOCK); else if ((vtclock / 4) < pci_clock_max) pciu_write(PCICLKSELREG, QUARTER_VTCLOCK); else { printk(KERN_ERR "PCI Clock is over 33MHz.\n"); iounmap(pciu_base); return -EINVAL; } /* Supply PCI clock by PCI bus */ vr41xx_supply_clock(PCI_CLOCK); if (setup->master_memory1 != NULL) { master = setup->master_memory1; val = IBA(master->bus_base_address) | MASTER_MSK(master->address_mask) | WINEN | PCIA(master->pci_base_address); pciu_write(PCIMMAW1REG, val); } else { val = pciu_read(PCIMMAW1REG); val &= ~WINEN; pciu_write(PCIMMAW1REG, val); } if (setup->master_memory2 != NULL) { master = setup->master_memory2; val = IBA(master->bus_base_address) | MASTER_MSK(master->address_mask) | WINEN | PCIA(master->pci_base_address); pciu_write(PCIMMAW2REG, val); } else { val = pciu_read(PCIMMAW2REG); val &= ~WINEN; pciu_write(PCIMMAW2REG, val); } if (setup->target_memory1 != NULL) { target = setup->target_memory1; val = TARGET_MSK(target->address_mask) | WINEN | ITA(target->bus_base_address); pciu_write(PCITAW1REG, val); } else { val = pciu_read(PCITAW1REG); val &= ~WINEN; pciu_write(PCITAW1REG, val); } if (setup->target_memory2 != NULL) { target = setup->target_memory2; val = TARGET_MSK(target->address_mask) | WINEN | ITA(target->bus_base_address); pciu_write(PCITAW2REG, val); } else { val = pciu_read(PCITAW2REG); val &= ~WINEN; pciu_write(PCITAW2REG, val); } if (setup->master_io != NULL) { master = setup->master_io; val = IBA(master->bus_base_address) | MASTER_MSK(master->address_mask) | WINEN | PCIIA(master->pci_base_address); pciu_write(PCIMIOAWREG, val); } else { val = pciu_read(PCIMIOAWREG); val &= ~WINEN; pciu_write(PCIMIOAWREG, val); } if (setup->exclusive_access == CANNOT_LOCK_FROM_DEVICE) pciu_write(PCIEXACCREG, UNLOCK); else pciu_write(PCIEXACCREG, 0); if (current_cpu_type() == CPU_VR4122) pciu_write(PCITRDYVREG, TRDYV(setup->wait_time_limit_from_irdy_to_trdy)); pciu_write(LATTIMEREG, MLTIM(setup->master_latency_timer)); if (setup->mailbox != NULL) { mailbox = setup->mailbox; val = MBADD(mailbox->base_address) | TYPE_32BITSPACE | MSI_MEMORY | PREF_APPROVAL; pciu_write(MAILBAREG, val); } if (setup->target_window1) { window = setup->target_window1; val = PMBA(window->base_address) | TYPE_32BITSPACE | MSI_MEMORY | PREF_APPROVAL; pciu_write(PCIMBA1REG, val); } if (setup->target_window2) { window = setup->target_window2; val = PMBA(window->base_address) | TYPE_32BITSPACE | MSI_MEMORY | PREF_APPROVAL; pciu_write(PCIMBA2REG, val); } val = pciu_read(RETVALREG); val &= ~RTYVAL_MASK; val |= RTYVAL(setup->retry_limit); pciu_write(RETVALREG, val); val = pciu_read(PCIAPCNTREG); val &= ~(TKYGNT | PAPC); switch (setup->arbiter_priority_control) { case PCI_ARBITRATION_MODE_ALTERNATE_0: val |= PAPC_ALTERNATE_0; break; case PCI_ARBITRATION_MODE_ALTERNATE_B: val |= PAPC_ALTERNATE_B; break; default: val |= PAPC_FAIR; break; } if (setup->take_away_gnt_mode == PCI_TAKE_AWAY_GNT_ENABLE) val |= TKYGNT_ENABLE; pciu_write(PCIAPCNTREG, val); pciu_write(COMMANDREG, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_PARITY | PCI_COMMAND_SERR); /* Clear bus error */ pciu_read(BUSERRADREG); pciu_write(PCIENREG, PCIU_CONFIG_DONE); if (setup->mem_resource != NULL) vr41xx_pci_controller.mem_resource = setup->mem_resource; if (setup->io_resource != NULL) { vr41xx_pci_controller.io_resource = setup->io_resource; } else { set_io_port_base(IO_PORT_BASE); ioport_resource.start = IO_PORT_RESOURCE_START; ioport_resource.end = IO_PORT_RESOURCE_END; } if (setup->master_io) { void __iomem *io_map_base; struct resource *res = vr41xx_pci_controller.io_resource; master = setup->master_io; io_map_base = ioremap(master->bus_base_address, resource_size(res)); if (!io_map_base) return -EBUSY; vr41xx_pci_controller.io_map_base = (unsigned long)io_map_base; } register_pci_controller(&vr41xx_pci_controller); return 0; }
void __init plat_mem_setup(void) { char *argptr; set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO); _machine_restart = jmr3927_machine_restart; _machine_halt = jmr3927_machine_halt; pm_power_off = jmr3927_machine_power_off; /* * IO/MEM resources. */ ioport_resource.start = pci_io_resource.start; ioport_resource.end = pci_io_resource.end; iomem_resource.start = 0; iomem_resource.end = 0xffffffff; /* Reboot on panic */ panic_timeout = 180; /* cache setup */ { unsigned int conf; #ifdef DO_ENABLE_CACHE int mips_ic_disable = 0, mips_dc_disable = 0; #else int mips_ic_disable = 1, mips_dc_disable = 1; #endif #ifdef DO_WRITE_THROUGH int mips_config_cwfon = 0; int mips_config_wbon = 0; #else int mips_config_cwfon = 1; int mips_config_wbon = 1; #endif conf = read_c0_conf(); conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON); conf |= mips_ic_disable ? 0 : TX39_CONF_ICE; conf |= mips_dc_disable ? 0 : TX39_CONF_DCE; conf |= mips_config_wbon ? TX39_CONF_WBON : 0; conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0; write_c0_conf(conf); write_c0_cache(0); } /* initialize board */ jmr3927_board_init(); argptr = prom_getcmdline(); if ((argptr = strstr(argptr, "toeon")) != NULL) jmr3927_ccfg_toeon = 1; argptr = prom_getcmdline(); if ((argptr = strstr(argptr, "ip=")) == NULL) { argptr = prom_getcmdline(); strcat(argptr, " ip=bootp"); } #ifdef CONFIG_SERIAL_TXX9 { extern int early_serial_txx9_setup(struct uart_port *port); int i; struct uart_port req; for(i = 0; i < 2; i++) { memset(&req, 0, sizeof(req)); req.line = i; req.iotype = UPIO_MEM; req.membase = (unsigned char __iomem *)TX3927_SIO_REG(i); req.mapbase = TX3927_SIO_REG(i); req.irq = i == 0 ? JMR3927_IRQ_IRC_SIO0 : JMR3927_IRQ_IRC_SIO1; if (i == 0) req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/; req.uartclk = JMR3927_IMCLK; early_serial_txx9_setup(&req); } } #ifdef CONFIG_SERIAL_TXX9_CONSOLE argptr = prom_getcmdline(); if ((argptr = strstr(argptr, "console=")) == NULL) { argptr = prom_getcmdline(); strcat(argptr, " console=ttyS1,115200"); } #endif #endif }
void __init plat_setup(void) { int i; char* argptr; board_setup(); /* board specific setup */ _machine_restart = pnx8550_machine_restart; _machine_halt = pnx8550_machine_halt; pm_power_off = pnx8550_machine_power_off; board_time_init = pnx8550_time_init; board_timer_setup = pnx8550_timer_setup; /* Clear the Global 2 Register, PCI Inta Output Enable Registers Bit 1:Enable DAC Powerdown -> 0:DACs are enabled and are working normally 1:DACs are powerdown Bit 0:Enable of PCI inta output -> 0 = Disable PCI inta output 1 = Enable PCI inta output */ PNX8550_GLB2_ENAB_INTA_O = 0; /* IO/MEM resources. */ set_io_port_base(KSEG1); ioport_resource.start = 0; ioport_resource.end = ~0; iomem_resource.start = 0; iomem_resource.end = ~0; /* Request I/O space for devices on this board */ for (i = 0; i < STANDARD_IO_RESOURCES; i++) request_resource(&ioport_resource, standard_io_resources + i); /* Place the Mode Control bit for GPIO pin 16 in primary function */ /* Pin 16 is used by UART1, UA1_TX */ outl((PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_16_BIT) | (PNX8550_GPIO_MODE_PRIMOP << PNX8550_GPIO_MC_17_BIT), PNX8550_GPIO_MC1); argptr = prom_getcmdline(); if ((argptr = strstr(argptr, "console=ttyS")) != NULL) { argptr += strlen("console=ttyS"); pnx8550_console_port = *argptr == '0' ? 0 : 1; /* We must initialize the UART (console) before prom_printf */ /* Set LCR to 8-bit and BAUD to 38400 (no 5) */ ip3106_lcr(UART_BASE, pnx8550_console_port) = IP3106_UART_LCR_8BIT; ip3106_baud(UART_BASE, pnx8550_console_port) = 5; } #ifdef CONFIG_KGDB argptr = prom_getcmdline(); if ((argptr = strstr(argptr, "kgdb=ttyS")) != NULL) { int line; argptr += strlen("kgdb=ttyS"); line = *argptr == '0' ? 0 : 1; rs_kgdb_hook(line); prom_printf("KGDB: Using ttyS%i for session, " "please connect your debugger\n", line ? 1 : 0); } #endif return; }
void __init plat_mem_setup(void) { unsigned short dsr; char *argptr; argptr = prom_getcmdline(); #ifdef CONFIG_SERIAL_CONSOLE if ((argptr = strstr(argptr, "console=")) == NULL) { argptr = prom_getcmdline(); strcat(argptr, " console=ttyS0,115200"); } #endif clear_c0_status(ST0_FR); board_time_init = it8172_time_init; _machine_restart = it8172_restart; _machine_halt = it8172_halt; pm_power_off = it8172_power_off; /* * IO/MEM resources. * * revisit this area. */ set_io_port_base(KSEG1); ioport_resource.start = it8172_resources.pci_io.start; ioport_resource.end = it8172_resources.pci_io.end; #ifdef CONFIG_IT8172_REVC iomem_resource.start = it8172_resources.pci_mem.start; iomem_resource.end = it8172_resources.pci_mem.end; #else iomem_resource.start = it8172_resources.pci_mem0.start; iomem_resource.end = it8172_resources.pci_mem3.end; #endif #ifdef CONFIG_BLK_DEV_INITRD ROOT_DEV = Root_RAM0; #endif /* * Pull enabled devices out of standby */ IT_IO_READ16(IT_PM_DSR, dsr); /* * Fixme: This breaks when these drivers are modules!!! */ #ifdef CONFIG_SOUND_IT8172 dsr &= ~IT_PM_DSR_ACSB; #else dsr |= IT_PM_DSR_ACSB; #endif #ifdef CONFIG_BLK_DEV_IT8172 dsr &= ~IT_PM_DSR_IDESB; #else dsr |= IT_PM_DSR_IDESB; #endif IT_IO_WRITE16(IT_PM_DSR, dsr); InitLPCInterface(); #ifdef CONFIG_MIPS_ITE8172 if (SearchIT8712()) { printk("Found IT8712 Super IO\n"); /* enable IT8712 serial port */ LPCSetConfig(LDN_SERIAL1, 0x30, 0x01); /* enable */ LPCSetConfig(LDN_SERIAL1, 0x23, 0x01); /* clock selection */ #ifdef CONFIG_SERIO_I8042 if (init_8712_keyboard()) { printk("Unable to initialize keyboard\n"); LPCSetConfig(LDN_KEYBOARD, 0x30, 0x0); /* disable keyboard */ } else { LPCSetConfig(LDN_KEYBOARD, 0x30, 0x1); /* enable keyboard */ LPCSetConfig(LDN_KEYBOARD, 0xf0, 0x2); LPCSetConfig(LDN_KEYBOARD, 0x71, 0x3); LPCSetConfig(LDN_MOUSE, 0x30, 0x1); /* enable mouse */ LPCSetConfig(0x4, 0x30, 0x1); LPCSetConfig(0x4, 0xf4, LPCGetConfig(0x4, 0xf4) | 0x80); if ((LPCGetConfig(LDN_KEYBOARD, 0x30) == 0) || (LPCGetConfig(LDN_MOUSE, 0x30) == 0)) printk("Error: keyboard or mouse not enabled\n"); } #endif } else { printk("IT8712 Super IO not found\n"); } #endif #ifdef CONFIG_IT8172_CIR { unsigned long data; //printk("Enabling CIR0\n"); IT_IO_READ16(IT_PM_DSR, data); data &= ~IT_PM_DSR_CIR0SB; IT_IO_WRITE16(IT_PM_DSR, data); //printk("DSR register: %x\n", (unsigned)IT_IO_READ16(IT_PM_DSR, data)); } #endif #ifdef CONFIG_IT8172_SCR0 { unsigned i; /* Enable Smart Card Reader 0 */ /* First power it up */ IT_IO_READ16(IT_PM_DSR, i); i &= ~IT_PM_DSR_SCR0SB; IT_IO_WRITE16(IT_PM_DSR, i); /* Then initialize its registers */ outb(( IT_SCR_SFR_GATE_UART_OFF << IT_SCR_SFR_GATE_UART_BIT |IT_SCR_SFR_FET_CHARGE_213_US << IT_SCR_SFR_FET_CHARGE_BIT |IT_SCR_SFR_CARD_FREQ_3_5_MHZ << IT_SCR_SFR_CARD_FREQ_BIT |IT_SCR_SFR_FET_ACTIVE_INVERT << IT_SCR_SFR_FET_ACTIVE_BIT |IT_SCR_SFR_ENABLE_ON << IT_SCR_SFR_ENABLE_BIT), IT8172_PCI_IO_BASE + IT_SCR0_BASE + IT_SCR_SFR); outb(IT_SCR_SCDR_RESET_MODE_ASYNC << IT_SCR_SCDR_RESET_MODE_BIT, IT8172_PCI_IO_BASE + IT_SCR0_BASE + IT_SCR_SCDR); } #endif /* CONFIG_IT8172_SCR0 */ #ifdef CONFIG_IT8172_SCR1 { unsigned i; /* Enable Smart Card Reader 1 */ /* First power it up */ IT_IO_READ16(IT_PM_DSR, i); i &= ~IT_PM_DSR_SCR1SB; IT_IO_WRITE16(IT_PM_DSR, i); /* Then initialize its registers */ outb(( IT_SCR_SFR_GATE_UART_OFF << IT_SCR_SFR_GATE_UART_BIT |IT_SCR_SFR_FET_CHARGE_213_US << IT_SCR_SFR_FET_CHARGE_BIT |IT_SCR_SFR_CARD_FREQ_3_5_MHZ << IT_SCR_SFR_CARD_FREQ_BIT |IT_SCR_SFR_FET_ACTIVE_INVERT << IT_SCR_SFR_FET_ACTIVE_BIT |IT_SCR_SFR_ENABLE_ON << IT_SCR_SFR_ENABLE_BIT), IT8172_PCI_IO_BASE + IT_SCR1_BASE + IT_SCR_SFR); outb(IT_SCR_SCDR_RESET_MODE_ASYNC << IT_SCR_SCDR_RESET_MODE_BIT, IT8172_PCI_IO_BASE + IT_SCR1_BASE + IT_SCR_SCDR); } #endif /* CONFIG_IT8172_SCR1 */ }
void __init sni_rm200_init(void) { set_io_port_base(SNI_PORT_BASE + 0x02000000); ioport_resource.end += 0x02000000; }
void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc) { struct bcma_bus *bus = pc->core->bus; struct bcma_drv_pci_host *pc_host; u32 tmp; u32 pci_membase_1G; unsigned long io_map_base; bcma_info(bus, "PCIEcore in host mode found\n"); if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) { bcma_info(bus, "This PCIE core is disabled and not working\n"); return; } pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL); if (!pc_host) { bcma_err(bus, "can not allocate memory"); return; } spin_lock_init(&pc_host->cfgspace_lock); pc->host_controller = pc_host; pc_host->pci_controller.io_resource = &pc_host->io_resource; pc_host->pci_controller.mem_resource = &pc_host->mem_resource; pc_host->pci_controller.pci_ops = &pc_host->pci_ops; pc_host->pdev = pc; pci_membase_1G = BCMA_SOC_PCI_DMA; pc_host->host_cfg_addr = BCMA_SOC_PCI_CFG; pc_host->pci_ops.read = bcma_core_pci_hostmode_read_config; pc_host->pci_ops.write = bcma_core_pci_hostmode_write_config; pc_host->mem_resource.name = "BCMA PCIcore external memory", pc_host->mem_resource.start = BCMA_SOC_PCI_DMA; pc_host->mem_resource.end = BCMA_SOC_PCI_DMA + BCMA_SOC_PCI_DMA_SZ - 1; pc_host->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED; pc_host->io_resource.name = "BCMA PCIcore external I/O", pc_host->io_resource.start = 0x100; pc_host->io_resource.end = 0x7FF; pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED; /* Reset RC */ usleep_range(3000, 5000); pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE); msleep(50); pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST | BCMA_CORE_PCI_CTL_RST_OE); /* 64 MB I/O access window. On 4716, use * sbtopcie0 to access the device registers. We * can't use address match 2 (1 GB window) region * as mips can't generate 64-bit address on the * backplane. */ if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4716 || bus->chipinfo.id == BCMA_CHIP_ID_BCM4748) { pc_host->mem_resource.start = BCMA_SOC_PCI_MEM; pc_host->mem_resource.end = BCMA_SOC_PCI_MEM + BCMA_SOC_PCI_MEM_SZ - 1; pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0, BCMA_CORE_PCI_SBTOPCI_MEM | BCMA_SOC_PCI_MEM); } else if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706) { tmp = BCMA_CORE_PCI_SBTOPCI_MEM; tmp |= BCMA_CORE_PCI_SBTOPCI_PREF; tmp |= BCMA_CORE_PCI_SBTOPCI_BURST; if (pc->core->core_unit == 0) { pc_host->mem_resource.start = BCMA_SOC_PCI_MEM; pc_host->mem_resource.end = BCMA_SOC_PCI_MEM + BCMA_SOC_PCI_MEM_SZ - 1; pc_host->io_resource.start = 0x100; pc_host->io_resource.end = 0x47F; pci_membase_1G = BCMA_SOC_PCIE_DMA_H32; pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0, tmp | BCMA_SOC_PCI_MEM); } else if (pc->core->core_unit == 1) { pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM; pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM + BCMA_SOC_PCI_MEM_SZ - 1; pc_host->io_resource.start = 0x480; pc_host->io_resource.end = 0x7FF; pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32; pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG; pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0, tmp | BCMA_SOC_PCI1_MEM); } } else pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0, BCMA_CORE_PCI_SBTOPCI_IO); /* 64 MB configuration access window */ pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0); /* 1 GB memory access window */ pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI2, BCMA_CORE_PCI_SBTOPCI_MEM | pci_membase_1G); /* As per PCI Express Base Spec 1.1 we need to wait for * at least 100 ms from the end of a reset (cold/warm/hot) * before issuing configuration requests to PCI Express * devices. */ msleep(100); bcma_core_pci_enable_crs(pc); if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706 || bus->chipinfo.id == BCMA_CHIP_ID_BCM4716) { u16 val16; bcma_extpci_read_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL, &val16, sizeof(val16)); val16 |= (2 << 5); /* Max payload size of 512 */ val16 |= (2 << 12); /* MRRS 512 */ bcma_extpci_write_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL, &val16, sizeof(val16)); } /* Enable PCI bridge BAR0 memory & master access */ tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp)); /* Enable PCI interrupts */ pcicore_write32(pc, BCMA_CORE_PCI_IMASK, BCMA_CORE_PCI_IMASK_INTA); /* Ok, ready to run, register it to the system. * The following needs change, if we want to port hostmode * to non-MIPS platform. */ io_map_base = (unsigned long)ioremap_nocache(pc_host->mem_resource.start, resource_size(&pc_host->mem_resource)); pc_host->pci_controller.io_map_base = io_map_base; set_io_port_base(pc_host->pci_controller.io_map_base); /* Give some time to the PCI controller to configure itself with the new * values. Not waiting at this point causes crashes of the machine. */ usleep_range(10000, 15000); register_pci_controller(&pc_host->pci_controller); return; }
static void __init rbtx4938_mem_setup(void) { unsigned long long pcfg; if (txx9_master_clock == 0) txx9_master_clock = 25000000; /* 25MHz */ tx4938_setup(); #ifdef CONFIG_PCI txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0); txx9_board_pcibios_setup = tx4927_pcibios_setup; #else set_io_port_base(RBTX4938_ETHER_BASE); #endif tx4938_sio_init(7372800, 0); #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61 pr_info("PIOSEL: disabling both ATA and NAND selection\n"); txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL); #endif #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND pr_info("PIOSEL: enabling NAND selection\n"); txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL); txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL); #endif #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA pr_info("PIOSEL: enabling ATA selection\n"); txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL); txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL); #endif #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_KEEP pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg); pr_info("PIOSEL: NAND %s, ATA %s\n", (pcfg & TX4938_PCFG_NDF_SEL) ? "enabled" : "disabled", (pcfg & TX4938_PCFG_ATA_SEL) ? "enabled" : "disabled"); #endif rbtx4938_spi_setup(); pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg); /* updated */ /* fixup piosel */ if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) == TX4938_PCFG_ATA_SEL) writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x04, rbtx4938_piosel_addr); else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) == TX4938_PCFG_NDF_SEL) writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x08, rbtx4938_piosel_addr); else writeb(readb(rbtx4938_piosel_addr) & ~(0x08 | 0x04), rbtx4938_piosel_addr); rbtx4938_fpga_resource.name = "FPGA Registers"; rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR); rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff; rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY; if (request_resource(&txx9_ce_res[2], &rbtx4938_fpga_resource)) printk(KERN_ERR "request resource for fpga failed\n"); _machine_restart = rbtx4938_machine_restart; writeb(0xff, rbtx4938_led_addr); printk(KERN_INFO "RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n", readb(rbtx4938_fpga_rev_addr), readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr)); }
void __init au1500_setup(void) { char *argptr; u32 pin_func, static_cfg0; u32 sys_freqctrl, sys_clksrc; argptr = prom_getcmdline(); /* NOTE: The memory map is established by YAMON 2.08+ */ /* Various early Au1500 Errata corrected by this */ set_cp0_config(1<<19); /* Config[OD] */ #ifdef CONFIG_AU1000_SERIAL_CONSOLE if ((argptr = strstr(argptr, "console=")) == NULL) { argptr = prom_getcmdline(); strcat(argptr, " console=ttyS0,115200"); } #endif #ifdef CONFIG_SOUND_AU1000 strcat(argptr, " au1000_audio=vra"); argptr = prom_getcmdline(); #endif __wbflush = au1500_wbflush; _machine_restart = au1000_restart; _machine_halt = au1000_halt; _machine_power_off = au1000_power_off; // IO/MEM resources. set_io_port_base(0); ioport_resource.start = 0x10000000; ioport_resource.end = 0xffffffff; iomem_resource.start = 0x10000000; iomem_resource.end = 0xffffffff; #ifdef CONFIG_BLK_DEV_INITRD ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0); initrd_start = (unsigned long)&__rd_start; initrd_end = (unsigned long)&__rd_end; #endif // set AUX clock to 12MHz * 8 = 96 MHz writel(8, SYS_AUXPLL); outl(0, SYS_PINSTATERD); udelay(100); #if defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1000_USB_DEVICE) #ifdef CONFIG_USB_OHCI if ((argptr = strstr(argptr, "usb_ohci=")) == NULL) { char usb_args[80]; argptr = prom_getcmdline(); memset(usb_args, 0, sizeof(usb_args)); sprintf(usb_args, " usb_ohci=base:0x%x,len:0x%x,irq:%d", USB_OHCI_BASE, USB_OHCI_LEN, AU1000_USB_HOST_INT); strcat(argptr, usb_args); } #endif /* zero and disable FREQ2 */ sys_freqctrl = readl(SYS_FREQCTRL0); sys_freqctrl &= ~0xFFF00000; writel(sys_freqctrl, SYS_FREQCTRL0); /* zero and disable USBH/USBD clocks */ sys_clksrc = readl(SYS_CLKSRC); sys_clksrc &= ~0x00007FE0; writel(sys_clksrc, SYS_CLKSRC); sys_freqctrl = readl(SYS_FREQCTRL0); sys_freqctrl &= ~0xFFF00000; sys_clksrc = readl(SYS_CLKSRC); sys_clksrc &= ~0x00007FE0; // FREQ2 = aux/2 = 48 MHz sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20)); writel(sys_freqctrl, SYS_FREQCTRL0); /* * Route 48MHz FREQ2 into USB Host and/or Device */ #ifdef CONFIG_USB_OHCI sys_clksrc |= ((4<<12) | (0<<11) | (0<<10)); #endif #ifdef CONFIG_AU1000_USB_DEVICE sys_clksrc |= ((4<<7) | (0<<6) | (0<<5)); #endif writel(sys_clksrc, SYS_CLKSRC); pin_func = readl(SYS_PINFUNC) & (u32)(~0x8000); #ifndef CONFIG_AU1000_USB_DEVICE // 2nd USB port is USB host pin_func |= 0x8000; #endif writel(pin_func, SYS_PINFUNC); #endif // defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1000_USB_DEVICE) #ifdef CONFIG_USB_OHCI // enable host controller and wait for reset done writel(0x08, USB_HOST_CONFIG); udelay(1000); writel(0x0c, USB_HOST_CONFIG); udelay(1000); readl(USB_HOST_CONFIG); while (!(readl(USB_HOST_CONFIG) & 0x10)) ; readl(USB_HOST_CONFIG); #endif #ifdef CONFIG_FB conswitchp = &dummy_con; #endif #ifdef CONFIG_FB_E1356 if ((argptr = strstr(argptr, "video=")) == NULL) { argptr = prom_getcmdline(); strcat(argptr, " video=e1356fb:system:pb1500,mmunalign:1"); } #endif // CONFIG_FB_E1356 #ifndef CONFIG_SERIAL_NONSTANDARD /* don't touch the default serial console */ writel(0, UART0_ADDR + UART_CLK); #endif writel(0, UART3_ADDR + UART_CLK); #ifdef CONFIG_BLK_DEV_IDE ide_ops = &std_ide_ops; #endif #ifdef CONFIG_PCI // Setup PCI bus controller writel(0, Au1500_PCI_CMEM); writel(0x00003fff, Au1500_CFG_BASE); writel(0xf, Au1500_PCI_CFG); writel(0xf0000000, Au1500_PCI_MWMASK_DEV); writel(0, Au1500_PCI_MWBASE_REV_CCL); writel(0x02a00356, Au1500_PCI_STATCMD); writel(0x00003c04, Au1500_PCI_HDRTYPE); writel(0x00000008, Au1500_PCI_MBAR); au_sync(); #endif while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_E0S); writel(SYS_CNTRL_E0 | SYS_CNTRL_EN0, SYS_COUNTER_CNTRL); au_sync(); while (readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S); outl(0, SYS_TOYTRIM); /* Enable BCLK switching */ writel(0x00000060, 0xb190003c); #ifdef CONFIG_RTC rtc_ops = &pb1500_rtc_ops; // Enable the RTC if not already enabled if (!(readb(0xac000028) & 0x20)) { writeb(readb(0xac000028) | 0x20, 0xac000028); } // Put the clock in BCD mode if (readb(0xac00002C) & 0x4) { /* reg B */ writeb(readb(0xac00002c) & ~0x4, 0xac00002c); au_sync(); } #endif }
void __init plat_mem_setup(void) { char *ctype; char *cserial; board_be_init = ip22_be_init; /* Init the INDY HPC I/O controller. Need to call this before * f*****g with the memory controller because it needs to know the * boardID and whether this is a Guiness or a FullHouse machine. */ sgihpc_init(); /* Init INDY memory controller. */ sgimc_init(); #ifdef CONFIG_BOARD_SCACHE /* Now enable boardcaches, if any. */ indy_sc_init(); #endif /* Set EISA IO port base for Indigo2 * ioremap cannot fail */ set_io_port_base((unsigned long)ioremap(0x00080000, 0x1fffffff - 0x00080000)); /* ARCS console environment variable is set to "g?" for * graphics console, it is set to "d" for the first serial * line and "d2" for the second serial line. * * Need to check if the case is 'g' but no keyboard: * (ConsoleIn/Out = serial) */ ctype = ArcGetEnvironmentVariable("console"); cserial = ArcGetEnvironmentVariable("ConsoleOut"); if ((ctype && *ctype == 'd') || (cserial && *cserial == 's')) { static char options[8]; char *baud = ArcGetEnvironmentVariable("dbaud"); if (baud) strcpy(options, baud); add_preferred_console("ttyS", *(ctype + 1) == '2' ? 1 : 0, baud ? options : NULL); } else if (!ctype || *ctype != 'g') { /* Use ARC if we don't want serial ('d') or graphics ('g'). */ prom_flags |= PROM_FLAG_USE_AS_CONSOLE; add_preferred_console("arc", 0, NULL); } #if defined(CONFIG_VT) && defined(CONFIG_SGI_NEWPORT_CONSOLE) { ULONG *gfxinfo; ULONG * (*__vec)(void) = (void *) (long) *((_PULONG *)(long)((PROMBLOCK)->pvector + 0x20)); gfxinfo = __vec(); sgi_gfxaddr = ((gfxinfo[1] >= 0xa0000000 && gfxinfo[1] <= 0xc0000000) ? gfxinfo[1] - 0xa0000000 : 0); /* newport addresses? */ if (sgi_gfxaddr == 0x1f0f0000 || sgi_gfxaddr == 0x1f4f0000) { conswitchp = &newport_con; } } #endif }
void __init plat_mem_setup(void) { set_io_port_base(0xbfd00000); serial_init(); }
void __init it8172_setup(void) { unsigned short dsr; char *argptr; u32 it_ver; unsigned long config; argptr = prom_getcmdline(); #ifdef CONFIG_SERIAL_CONSOLE if ((argptr = strstr(argptr, "console=")) == NULL) { argptr = prom_getcmdline(); strcat(argptr, " console=ttyS0,115200"); } #endif config = read_32bit_cp0_register(CP0_CONFIG); printk("SysClock frequency multiplier: %d\n", ((config>>28)&0x7) + 2); clear_cp0_status(ST0_FR); rtc_ops = &it8172_rtc_ops; board_time_init = it8172_time_init; board_timer_setup = it8172_timer_setup; rtc_get_time = it8172_rtc_get_time; //rtc_set_time = it8172_rtc_set_time; _machine_restart = it8172_restart; _machine_halt = it8172_halt; _machine_power_off = it8172_power_off; /* * IO/MEM resources. * * revisit this area. */ set_io_port_base(KSEG1); ioport_resource.start = it8172_resources.pci_io.start; ioport_resource.end = it8172_resources.pci_io.end; #ifdef CONFIG_IT8172_REVC iomem_resource.start = it8172_resources.pci_mem.start; iomem_resource.end = it8172_resources.pci_mem.end; #else iomem_resource.start = it8172_resources.pci_mem0.start; iomem_resource.end = it8172_resources.pci_mem3.end; #endif #ifdef CONFIG_BLK_DEV_INITRD ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0); #endif /* * Pull enabled devices out of standby */ IT_IO_READ16(IT_PM_DSR, dsr); #ifdef CONFIG_SOUND_IT8172 dsr &= ~IT_PM_DSR_ACSB; #else dsr |= IT_PM_DSR_ACSB; #endif #ifdef CONFIG_BLK_DEV_IT8172 dsr &= ~IT_PM_DSR_IDESB; ide_ops = &std_ide_ops; #else dsr |= IT_PM_DSR_IDESB; #endif IT_IO_WRITE16(IT_PM_DSR, dsr); #ifdef CONFIG_FB conswitchp = &dummy_con; #endif InitLPCInterface(); #if defined(CONFIG_MIPS_ITE8172) || defined(CONFIG_MIPS_SNSC_MPU210) if (SearchIT8712()) { printk("Found IT8712 Super IO\n"); // enable IT8712 serial port LPCSetConfig(LDN_SERIAL1, 0x30, 0x01); /* enable */ LPCSetConfig(LDN_SERIAL1, 0x23, 0x01); /* clock selection */ #if defined(CONFIG_MIPS_SNSC_MPU210) // enable IT8712 serial port LPCSetConfig(LDN_SERIAL2, 0x30, 0x01); /* enable */ LPCSetConfig(LDN_SERIAL2, 0x23, 0x01); /* clock selection */ #endif // defined(CONFIG_MIPS_SNSC_MPU210) #ifdef CONFIG_PC_KEYB if (init_8712_keyboard()) { printk("Unable to initialize keyboard\n"); LPCSetConfig(LDN_KEYBOARD, 0x30, 0x0); /* disable keyboard */ } else { LPCSetConfig(LDN_KEYBOARD, 0x30, 0x1); /* enable keyboard */ LPCSetConfig(LDN_KEYBOARD, 0xf0, 0x2); LPCSetConfig(LDN_KEYBOARD, 0x71, 0x3); LPCSetConfig(LDN_MOUSE, 0x30, 0x1); /* enable mouse */ LPCSetConfig(0x4, 0x30, 0x1); LPCSetConfig(0x4, 0xf4, LPCGetConfig(0x4, 0xf4) | 0x80); if ((LPCGetConfig(LDN_KEYBOARD, 0x30) == 0) || (LPCGetConfig(LDN_MOUSE, 0x30) == 0)) printk("Error: keyboard or mouse not enabled\n"); kbd_ops = &std_kbd_ops; } #endif } else { printk("IT8712 Super IO not found\n"); } #endif #ifdef CONFIG_IT8172_CIR { unsigned long data; //printk("Enabling CIR0\n"); IT_IO_READ16(IT_PM_DSR, data); data &= ~IT_PM_DSR_CIR0SB; IT_IO_WRITE16(IT_PM_DSR, data); //printk("DSR register: %x\n", (unsigned)IT_IO_READ16(IT_PM_DSR, data)); } #endif #ifdef CONFIG_IT8172_SCR0 { unsigned i; /* Enable Smart Card Reader 0 */ /* First power it up */ IT_IO_READ16(IT_PM_DSR, i); i &= ~IT_PM_DSR_SCR0SB; IT_IO_WRITE16(IT_PM_DSR, i); /* Then initialize its registers */ outb(( IT_SCR_SFR_GATE_UART_OFF << IT_SCR_SFR_GATE_UART_BIT |IT_SCR_SFR_FET_CHARGE_213_US << IT_SCR_SFR_FET_CHARGE_BIT |IT_SCR_SFR_CARD_FREQ_3_5_MHZ << IT_SCR_SFR_CARD_FREQ_BIT |IT_SCR_SFR_FET_ACTIVE_INVERT << IT_SCR_SFR_FET_ACTIVE_BIT |IT_SCR_SFR_ENABLE_ON << IT_SCR_SFR_ENABLE_BIT), IT8172_PCI_IO_BASE + IT_SCR0_BASE + IT_SCR_SFR); outb(IT_SCR_SCDR_RESET_MODE_ASYNC << IT_SCR_SCDR_RESET_MODE_BIT, IT8172_PCI_IO_BASE + IT_SCR0_BASE + IT_SCR_SCDR); } #endif /* CONFIG_IT8172_SCR0 */ #ifdef CONFIG_IT8172_SCR1 { unsigned i; /* Enable Smart Card Reader 1 */ /* First power it up */ IT_IO_READ16(IT_PM_DSR, i); i &= ~IT_PM_DSR_SCR1SB; IT_IO_WRITE16(IT_PM_DSR, i); /* Then initialize its registers */ outb(( IT_SCR_SFR_GATE_UART_OFF << IT_SCR_SFR_GATE_UART_BIT |IT_SCR_SFR_FET_CHARGE_213_US << IT_SCR_SFR_FET_CHARGE_BIT |IT_SCR_SFR_CARD_FREQ_3_5_MHZ << IT_SCR_SFR_CARD_FREQ_BIT |IT_SCR_SFR_FET_ACTIVE_INVERT << IT_SCR_SFR_FET_ACTIVE_BIT |IT_SCR_SFR_ENABLE_ON << IT_SCR_SFR_ENABLE_BIT), IT8172_PCI_IO_BASE + IT_SCR1_BASE + IT_SCR_SFR); outb(IT_SCR_SCDR_RESET_MODE_ASYNC << IT_SCR_SCDR_RESET_MODE_BIT, IT8172_PCI_IO_BASE + IT_SCR1_BASE + IT_SCR_SCDR); } #endif /* CONFIG_IT8172_SCR1 */ }
int misc_init_r(void) { set_io_port_base(0); return 0; }
static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc) { u32 val; if (WARN_ON(extpci_core)) return; extpci_core = pc; ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n"); /* Reset devices on the external PCI bus */ val = SSB_PCICORE_CTL_RST_OE; val |= SSB_PCICORE_CTL_CLK_OE; pcicore_write32(pc, SSB_PCICORE_CTL, val); val |= SSB_PCICORE_CTL_CLK; /* Clock on */ pcicore_write32(pc, SSB_PCICORE_CTL, val); udelay(150); /* Assertion time demanded by the PCI standard */ val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */ pcicore_write32(pc, SSB_PCICORE_CTL, val); val = SSB_PCICORE_ARBCTL_INTERN; pcicore_write32(pc, SSB_PCICORE_ARBCTL, val); udelay(1); /* Assertion time demanded by the PCI standard */ if (pc->dev->bus->has_cardbus_slot) { ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n"); pc->cardbusmode = 1; /* GPIO 1 resets the bridge */ ssb_gpio_out(pc->dev->bus, 1, 1); ssb_gpio_outen(pc->dev->bus, 1, 1); pcicore_write16(pc, SSB_PCICORE_SPROM(0), pcicore_read16(pc, SSB_PCICORE_SPROM(0)) | 0x0400); } /* 64MB I/O window */ pcicore_write32(pc, SSB_PCICORE_SBTOPCI0, SSB_PCICORE_SBTOPCI_IO); /* 64MB config space */ pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, SSB_PCICORE_SBTOPCI_CFG0); /* 1GB memory window */ pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA); /* Enable PCI bridge BAR0 prefetch and burst */ val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2); /* Clear error conditions */ val = 0; ssb_extpci_write_config(pc, 0, 0, 0, PCI_STATUS, &val, 2); /* Enable PCI interrupts */ pcicore_write32(pc, SSB_PCICORE_IMASK, SSB_PCICORE_IMASK_INTA); /* Ok, ready to run, register it to the system. * The following needs change, if we want to port hostmode * to non-MIPS platform. */ ssb_pcicore_controller.io_map_base = (unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000); set_io_port_base(ssb_pcicore_controller.io_map_base); /* Give some time to the PCI controller to configure itself with the new * values. Not waiting at this point causes crashes of the machine. */ mdelay(10); register_pci_controller(&ssb_pcicore_controller); }
struct serial_device *default_serial_console(void) { set_io_port_base(CKSEG1ADDR(0)); return &sio_device; }
static void __init jmr3927_setup(void) { char *argptr; set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO); board_time_init = jmr3927_time_init; board_timer_setup = jmr3927_timer_setup; _machine_restart = jmr3927_machine_restart; _machine_halt = jmr3927_machine_halt; _machine_power_off = jmr3927_machine_power_off; /* * IO/MEM resources. */ ioport_resource.start = pci_io_resource.start; ioport_resource.end = pci_io_resource.end; iomem_resource.start = pci_mem_resource.start; iomem_resource.end = pci_mem_resource.end; /* Reboot on panic */ panic_timeout = 180; { unsigned int conf; conf = read_c0_conf(); } #if 1 /* cache setup */ { unsigned int conf; #ifdef DO_ENABLE_CACHE int mips_ic_disable = 0, mips_dc_disable = 0; #else int mips_ic_disable = 1, mips_dc_disable = 1; #endif #ifdef DO_WRITE_THROUGH int mips_config_cwfon = 0; int mips_config_wbon = 0; #else int mips_config_cwfon = 1; int mips_config_wbon = 1; #endif conf = read_c0_conf(); conf &= ~(TX39_CONF_ICE | TX39_CONF_DCE | TX39_CONF_WBON | TX39_CONF_CWFON); conf |= mips_ic_disable ? 0 : TX39_CONF_ICE; conf |= mips_dc_disable ? 0 : TX39_CONF_DCE; conf |= mips_config_wbon ? TX39_CONF_WBON : 0; conf |= mips_config_cwfon ? TX39_CONF_CWFON : 0; write_c0_conf(conf); write_c0_cache(0); } #endif /* initialize board */ jmr3927_board_init(); argptr = prom_getcmdline(); if ((argptr = strstr(argptr, "toeon")) != NULL) { jmr3927_ccfg_toeon = 1; } argptr = prom_getcmdline(); if ((argptr = strstr(argptr, "ip=")) == NULL) { argptr = prom_getcmdline(); strcat(argptr, " ip=bootp"); } #ifdef CONFIG_TXX927_SERIAL_CONSOLE argptr = prom_getcmdline(); if ((argptr = strstr(argptr, "console=")) == NULL) { argptr = prom_getcmdline(); strcat(argptr, " console=ttyS1,115200"); } #endif }
void __init prom_init(void) { prom_argc = fw_arg0; _prom_argv = (int *) fw_arg1; _prom_envp = (int *) fw_arg2; #if defined(CONFIG_MIPS_AVALANCHE_PSPBOOT) sys_initenv(); #endif #if !defined(CONFIG_MIPS_AVALANCHE_SOC) mips_display_message("LINUX"); #ifdef CONFIG_MIPS_SEAD set_io_port_base(KSEG1); #else /* * early setup of _pcictrl_bonito so that we can determine * the system controller on a CORE_EMUL board */ _pcictrl_bonito = (unsigned long)ioremap(BONITO_REG_BASE, BONITO_REG_SIZE); mips_revision_corid = MIPS_REVISION_CORID; if (mips_revision_corid == MIPS_REVISION_CORID_CORE_EMUL) { if (BONITO_PCIDID == 0x0001df53 || BONITO_PCIDID == 0x0003df53) mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_BON; else mips_revision_corid = MIPS_REVISION_CORID_CORE_EMUL_MSC; } switch(mips_revision_corid) { case MIPS_REVISION_CORID_QED_RM5261: case MIPS_REVISION_CORID_CORE_LV: case MIPS_REVISION_CORID_CORE_FPGA: case MIPS_REVISION_CORID_CORE_FPGAR2: /* * Setup the North bridge to do Master byte-lane swapping * when running in bigendian. */ _pcictrl_gt64120 = (unsigned long)ioremap(MIPS_GT_BASE, 0x2000); #ifdef CONFIG_CPU_LITTLE_ENDIAN GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT | GT_PCI0_CMD_SBYTESWAP_BIT); #else GT_WRITE(GT_PCI0_CMD_OFS, 0); #endif #ifdef CONFIG_MIPS_MALTA set_io_port_base(MALTA_GT_PORT_BASE); #else set_io_port_base((unsigned long)ioremap(0, 0x20000000)); #endif break; case MIPS_REVISION_CORID_CORE_EMUL_BON: case MIPS_REVISION_CORID_BONITO64: case MIPS_REVISION_CORID_CORE_20K: _pcictrl_bonito_pcicfg = (unsigned long)ioremap(BONITO_PCICFG_BASE, BONITO_PCICFG_SIZE); /* * Disable Bonito IOBC. */ BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); /* * Setup the North bridge to do Master byte-lane swapping * when running in bigendian. */ #ifdef CONFIG_CPU_LITTLE_ENDIAN BONITO_BONGENCFG = BONITO_BONGENCFG & ~(BONITO_BONGENCFG_MSTRBYTESWAP | BONITO_BONGENCFG_BYTESWAP); #else BONITO_BONGENCFG = BONITO_BONGENCFG | BONITO_BONGENCFG_MSTRBYTESWAP | BONITO_BONGENCFG_BYTESWAP; #endif #ifdef CONFIG_MIPS_MALTA set_io_port_base(MALTA_BONITO_PORT_BASE); #else set_io_port_base((unsigned long)ioremap(0, 0x20000000)); #endif break; case MIPS_REVISION_CORID_CORE_MSC: case MIPS_REVISION_CORID_CORE_FPGA2: case MIPS_REVISION_CORID_CORE_EMUL_MSC: _pcictrl_msc = (unsigned long)ioremap(MIPS_MSC01_PCI_REG_BASE, 0x2000); #ifdef CONFIG_CPU_LITTLE_ENDIAN MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); #else MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF | MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF | MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF); #endif #ifdef CONFIG_MIPS_MALTA set_io_port_base(MALTA_MSC_PORT_BASE); #else set_io_port_base((unsigned long)ioremap(0, 0x20000000)); #endif break; default: /* Unknown Core card */ mips_display_message("CC Error"); while(1); /* We die here... */ } #endif #endif #if defined(CONFIG_MIPS_AVALANCHE_SOC) set_io_port_base(0); setup_prom_printf(0); #endif /* CONFIG_MIPS_AVALANCHE_SOC */ prom_printf("\nLINUX started...\n"); prom_init_cmdline(); prom_meminit(); #ifdef CONFIG_SERIAL_8250_CONSOLE console_config(); #endif }
void __init plat_mem_setup(void) { extern int rac_setting(int); extern int panic_timeout; #ifdef CONFIG_MIPS_BRCM #if defined( CONFIG_MIPS_BCM7038A0 ) set_io_port_base(0xe0000000); /* start of PCI IO space. */ #elif defined( CONFIG_MIPS_BCM7038B0 ) || defined( CONFIG_MIPS_BCM7038C0 ) \ || defined( CONFIG_MIPS_BCM7400 ) || defined( CONFIG_MIPS_BCM3560 ) \ || defined( CONFIG_MIPS_BCM7401 ) || defined( CONFIG_MIPS_BCM7402 ) \ || defined( CONFIG_MIPS_BCM7118 ) || defined( CONFIG_MIPS_BCM7440 ) \ || defined( CONFIG_MIPS_BCM7403 ) || defined( CONFIG_MIPS_BCM7405 ) \ || defined( CONFIG_MIPS_BCM7335 ) || defined( CONFIG_MIPS_BCM7325 ) \ || defined( CONFIG_MIPS_BCM3548 ) set_io_port_base(0xf0000000); /* start of PCI IO space. */ #elif defined( CONFIG_MIPS_BCM7329 ) set_io_port_base(KSEG1ADDR(0x1af90000)); #elif defined ( CONFIG_BCM93730 ) set_io_port_base(KSEG1ADDR(0x13000000)); #else set_io_port_base(0); #endif #endif #ifndef CONFIG_TIVO _machine_restart = brcm_machine_restart; _machine_halt = brcm_machine_halt; //_machine_power_off = brcm_machine_power_off; pm_power_off = brcm_machine_power_off; board_time_init = brcm_time_init; panic_timeout = 180; #else _machine_restart = (void(*)(char *))tivo_machine_restart; _machine_halt = tivo_machine_restart; pm_power_off = tivo_machine_restart; board_time_init = brcm_time_init; panic_timeout = 3; #endif // Set RAC on 7400 #if defined( CONFIG_MIPS_BCM7400A0 ) rac_setting(1); #endif #if defined( CONFIG_MIPS_BCM7440B0 ) || defined( CONFIG_MIPS_BCM7325A0 ) \ || defined( CONFIG_MIPS_BCM7443A0 ) // Set externalize IO sync bit (CP0 $16, sel 7, bit 8) { uint32_t extIO = __read_32bit_c0_register($16, 7); __write_32bit_c0_register($16, 7, extIO | 0x100); extIO = __read_32bit_c0_register($16, 7); } #endif #ifdef CONFIG_PC_KEYB kbd_ops = &brcm_kbd_ops; #endif #ifdef CONFIG_VT conswitchp = &dummy_con; #endif #ifdef CONFIG_DISCONTIGMEM brcm_numa_init(); #endif }
int __init prom_init(int argc, char **argv, char **envp) { prom_argc = argc; _prom_argv = (int *)argv; _prom_envp = (int *)envp; mips_display_message("LINUX"); #ifdef CONFIG_MIPS_SEAD set_io_port_base(KSEG1); #else mips_revision_corid = MIPS_REVISION_CORID; switch(mips_revision_corid) { case MIPS_REVISION_CORID_QED_RM5261: case MIPS_REVISION_CORID_CORE_LV: case MIPS_REVISION_CORID_CORE_FPGA: /* * Setup the North bridge to do Master byte-lane swapping * when running in bigendian. */ #ifdef CONFIG_CPU_LITTLE_ENDIAN GT_WRITE(GT_PCI0_CMD_OFS, GT_PCI0_CMD_MBYTESWAP_BIT | GT_PCI0_CMD_SBYTESWAP_BIT); #else GT_WRITE(GT_PCI0_CMD_OFS, 0); #endif #ifdef CONFIG_MIPS_MALTA set_io_port_base(MALTA_GT_PORT_BASE); #else set_io_port_base(KSEG1); #endif break; case MIPS_REVISION_CORID_BONITO64: case MIPS_REVISION_CORID_CORE_20K: /* * Disable Bonito IOBC. */ BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); /* * Setup the North bridge to do Master byte-lane swapping * when running in bigendian. */ #ifdef CONFIG_CPU_LITTLE_ENDIAN BONITO_BONGENCFG = BONITO_BONGENCFG & ~(BONITO_BONGENCFG_MSTRBYTESWAP | BONITO_BONGENCFG_BYTESWAP); #else BONITO_BONGENCFG = BONITO_BONGENCFG | BONITO_BONGENCFG_MSTRBYTESWAP | BONITO_BONGENCFG_BYTESWAP; #endif #ifdef CONFIG_MIPS_MALTA set_io_port_base(MALTA_BONITO_PORT_BASE); #else set_io_port_base(KSEG1); #endif break; case MIPS_REVISION_CORID_CORE_MSC: #ifdef CONFIG_MIPS_MALTA set_io_port_base(MALTA_MSC_PORT_BASE); #endif #ifdef CONFIG_CPU_LITTLE_ENDIAN MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_NOSWAP); #else MSC_WRITE(MSC01_PCI_SWAP, MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_IO_SHF | MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_MEM_SHF | MSC01_PCI_SWAP_BYTESWAP << MSC01_PCI_SWAP_BAR0_SHF); #endif break; default: /* Unknown Core card */ mips_display_message("CC Error"); while(1); /* We die here... */ } #endif prom_printf("\nLINUX started...\n"); prom_init_cmdline(); prom_meminit(); return 0; }