static void gpio_configure(void) { immap_t *im; gpio512x_t *gpioregs; im = (immap_t *) CONFIG_SYS_IMMR; gpioregs = &im->gpio; out_be32(&gpioregs->gpodr, 0x00290000); /* open drain */ out_be32(&gpioregs->gpdat, 0x80001040); /* data (when output) */ /* * out_be32(&gpioregs->gpdir, 0xC2293020); * workaround for a hardware effect: configure direction in pieces, * setting all outputs at once drops the reset line too low and * makes us lose the MII connection (breaks ethernet for us) */ out_be32(&gpioregs->gpdir, 0x02003060); /* direction */ setbits_be32(&gpioregs->gpdir, 0x00200000); /* += reset asi */ udelay(10); setbits_be32(&gpioregs->gpdir, 0x00080000); /* += reset safety */ udelay(10); setbits_be32(&gpioregs->gpdir, 0x00010000); /* += reset comm */ udelay(10); setbits_be32(&gpioregs->gpdir, 0xC0000000); /* += backlight, KB sel */ /* to turn from red to yellow when U-Boot runs */ setbits_be32(&gpioregs->gpdat, 0x00002020); out_be32(&gpioregs->gpimr, 0x00000000); /* interrupt mask */ out_be32(&gpioregs->gpicr1, 0x00000004); /* interrupt sense part 1 */ out_be32(&gpioregs->gpicr2, 0x00A80000); /* interrupt sense part 2 */ out_be32(&gpioregs->gpier, 0xFFFFFFFF); /* interrupt events, clear */ }
int misc_init_r(void) { struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) { clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM | MPC85xx_PMUXCR_CAN1_UART | MPC85xx_PMUXCR_CAN2_TDM | MPC85xx_PMUXCR_CAN2_UART); out_8(&cpld_data->tdm_can_sel, MUX_CPLD_CAN_UART); } else if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "tdm")) { clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_UART | MPC85xx_PMUXCR_CAN1_UART); setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN2_TDM | MPC85xx_PMUXCR_CAN1_TDM); clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_GPIO); setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_TDM); out_8(&cpld_data->tdm_can_sel, MUX_CPLD_TDM); out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_SLIC); } else { /* defaultly spi_cs_sel to flash */ out_8(&cpld_data->spi_cs0_sel, MUX_CPLD_SPICS0_FLASH); } return 0; }
int misc_init_r(void) { int i; struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE; struct pmc405de_cpld *cpld = (struct pmc405de_cpld *)CONFIG_SYS_CPLD_BASE; if (!is_monarch()) { /* PCI configuration done: release EREADY */ setbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EREADY); setbits_be32(&gpio0->tcr, CONFIG_SYS_GPIO_EREADY); } /* turn off POST LED */ out_8(&cpld->control, CPLD_CONTROL_POSTLED_N | CPLD_CONTROL_POSTLED_GATE); /* turn on LEDs: RUN, A, B */ clrbits_be32(&gpio0->or, CONFIG_SYS_GPIO_LEDRUN_N | CONFIG_SYS_GPIO_LEDA_N | CONFIG_SYS_GPIO_LEDB_N); for (i=0; i < 200; i++) udelay(1000); /* turn off LEDs: A, B */ setbits_be32(&gpio0->or, CONFIG_SYS_GPIO_LEDA_N | CONFIG_SYS_GPIO_LEDB_N); return (0); }
/* * Miscellaneous late-boot configurations * * If a VSC7385 microcode image is present, then upload it. */ int misc_init_r(void) { #ifdef CONFIG_MPC8XXX_SPI immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; sysconf83xx_t *sysconf = &immr->sysconf; /* * Set proper bits in SICRH to allow SPI on header J8 * * NOTE: this breaks the TSEC2 interface, attached to the Vitesse * switch. The pinmux configuration does not have a fine enough * granularity to support both simultaneously. */ clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO); puts("WARNING: SPI enabled, TSEC2 support is broken\n"); /* Set header J8 SPI chip select output, disabled */ setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK); setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK); #endif #ifdef CONFIG_VSC7385_IMAGE if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE, CONFIG_VSC7385_IMAGE_SIZE)) { puts("Failure uploading VSC7385 microcode.\n"); return 1; } #endif return 0; }
int board_early_init_f(void) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); bool cpuwd_flag = false; /* configure mode for uP reset request */ qrio_uprstreq(UPREQ_CORE_RST); /* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */ setbits_be32(&gur->ddrclkdr, 0x001f000f); /* set reset reason according CPU register */ if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) == RSTRQSR1_WDT_RR) cpuwd_flag = true; qrio_cpuwd_flag(cpuwd_flag); /* clear CPU bits by writing 1 */ setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR); /* set the BFTIC's prstcfg to reset at power-up and unit reset only */ qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST); /* and enable WD on it */ qrio_wdmask(BFTIC4_RST, true); /* set the ZL30138's prstcfg to reset at power-up only */ qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST); /* and take it out of reset as soon as possible (needed for Hooper) */ qrio_prst(ZL30158_RST, false, false); return 0; }
void board_init_f(ulong bootflag) { u32 plat_ratio; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; console_init_f(); /* Clock configuration to access CPLD using IFC(GPCM) */ setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); #ifdef CONFIG_TARGET_P1010RDB_PB setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS); #endif /* initialize selected port with appropriate baud rate */ plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; plat_ratio >>= 1; gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, gd->bus_clk / 16 / CONFIG_BAUDRATE); #ifdef CONFIG_SPL_MMC_BOOT puts("\nSD boot...\n"); #elif defined(CONFIG_SPL_SPI_BOOT) puts("\nSPI Flash boot...\n"); #endif /* copy code to RAM and jump to it - this should not return */ /* NOTE - code has to be copied out of NAND buffer before * other blocks can be read. */ relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); }
static void phy_change(struct eth_device *dev) { uec_private_t *uec = (uec_private_t *)dev->priv; #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); /* QE9 and QE12 need to be set for enabling QE MII managment signals */ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9); setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); #endif /* Update the link, speed, duplex */ uec->mii_info->phyinfo->read_status(uec->mii_info); #if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025) /* * QE12 is muxed with LBCTL, it needs to be released for enabling * LBCTL signal for LBC usage. */ clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12); #endif /* Adjust the interface according to speed */ adjust_link(dev); }
void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); struct fsl_pci_info pci_info[2]; u32 devdisr, pordevsr, io_sel; int first_free_busno = 0; int num = 0; int pcie_ep, pcie_configured; devdisr = in_be32(&gur->devdisr); pordevsr = in_be32(&gur->pordevsr); io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; debug (" pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel); if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)) printf (" eTSEC2 is in sgmii mode.\n"); puts("\n"); #ifdef CONFIG_PCIE2 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ SET_STD_PCIE_INFO(pci_info[num], 2); pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); printf(" PCIE2 connected to Slot 1 as %s (base addr %lx)\n", pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie2_hose, first_free_busno); } else { printf (" PCIE2: disabled\n"); } puts("\n"); #else setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ #endif #ifdef CONFIG_PCIE1 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ SET_STD_PCIE_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n", pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie1_hose, first_free_busno); } else { printf (" PCIE1: disabled\n"); } puts("\n"); #else setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ #endif }
void mpc8308_setup_hw(void) { immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; /* * set "startup-finished"-gpios */ setbits_be32(&immr->gpio[0].dir, (1 << (31-11)) | (1 << (31-12))); setbits_be32(&immr->gpio[0].dat, 1 << (31-12)); }
int misc_init_r(void) { serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; __maybe_unused ccsr_gur_t *gur; u32 actual[NUM_SRDS_BANKS]; unsigned int i; u8 sw3; gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #ifdef CONFIG_SRIO1 if (is_serdes_configured(SRIO1)) { set_next_law(CONFIG_SYS_RIO1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_RIO_1); } else { printf (" SRIO1: disabled\n"); } #else setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); /* disable */ #endif #ifdef CONFIG_SRIO2 if (is_serdes_configured(SRIO2)) { set_next_law(CONFIG_SYS_RIO2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_RIO_2); } else { printf (" SRIO2: disabled\n"); } #else setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); /* disable */ #endif /* Warn if the expected SERDES reference clocks don't match the * actual reference clocks. This needs to be done after calling * p4080_erratum_serdes8(), since that function may modify the clocks. */ sw3 = in_8(&PIXIS_SW(3)); actual[0] = (sw3 & 0x40) ? SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100; actual[1] = (sw3 & 0x20) ? SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; actual[2] = (sw3 & 0x10) ? SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; for (i = 0; i < NUM_SRDS_BANKS; i++) { u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; if (expected != actual[i]) { printf("Warning: SERDES bank %u expects reference clock" " %sMHz, but actual is %sMHz\n", i + 1, serdes_clock_to_string(expected), serdes_clock_to_string(actual[i])); } } return 0; }
static void set_pin(int state, unsigned long mask, int port) { ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, port); if (state) setbits_be32(&iop->pdat, mask); else clrbits_be32(&iop->pdat, mask); setbits_be32(&iop->pdir, mask); }
int interrupt_init(void) { int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE); /* Make sure all interrupts are disabled */ setbits_be32(&intp->imrh0, 0xffffffff); setbits_be32(&intp->imrl0, 0xffffffff); enable_interrupts(); return 0; }
int misc_init_r(void) { #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; ccsr_gpio_t *gpio = (void *)CONFIG_SYS_MPC85xx_GPIO_ADDR; setbits_be32(&gpio->gpdir, USB2_PORT_OUT_EN); setbits_be32(&gpio->gpdat, USB2_PORT_OUT_EN); setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_ELBC_OFF_USB2_ON); #endif return 0; }
int board_early_init_f(void) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); setbits_be32(&gur->pmuxcr, (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP)); /* All the device are enable except for SRIO12 */ setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_SRIO); return 0; }
static int fm_eth_open(struct eth_device *dev, bd_t *bd) { struct fm_eth *fm_eth; struct fsl_enet_mac *mac; #ifdef CONFIG_PHYLIB int ret; #endif fm_eth = (struct fm_eth *)dev->priv; mac = fm_eth->mac; /* setup the MAC address */ if (dev->enetaddr[0] & 0x01) { printf("%s: MacAddress is multcast address\n", __func__); return 1; } mac->set_mac_addr(mac, dev->enetaddr); /* enable bmi Rx port */ setbits_be32(&fm_eth->rx_port->fmbm_rcfg, FMBM_RCFG_EN); /* enable MAC rx/tx port */ mac->enable_mac(mac); /* enable bmi Tx port */ setbits_be32(&fm_eth->tx_port->fmbm_tcfg, FMBM_TCFG_EN); /* re-enable transmission of frame */ fmc_tx_port_graceful_stop_disable(fm_eth); #ifdef CONFIG_PHYLIB if (fm_eth->phydev) { ret = phy_startup(fm_eth->phydev); if (ret) { printf("%s: Could not initialize\n", fm_eth->phydev->dev->name); return ret; } } else { return 0; } #else fm_eth->phydev->speed = SPEED_1000; fm_eth->phydev->link = 1; fm_eth->phydev->duplex = DUPLEX_FULL; #endif /* set the MAC-PHY mode */ mac->set_if_mode(mac, fm_eth->enet_if, fm_eth->phydev->speed); if (!fm_eth->phydev->link) printf("%s: No link.\n", fm_eth->phydev->dev->name); return fm_eth->phydev->link ? 0 : -1; }
static void setports(int gpio) { ioport_t *iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3); if (gpio) { clrbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK)); clrbits_be32(&iop->podr, (SDA_MASK | SCL_MASK)); } else { setbits_be32(&iop->ppar, (SDA_MASK | SCL_MASK)); clrbits_be32(&iop->pdir, (SDA_MASK | SCL_MASK)); setbits_be32(&iop->podr, (SDA_MASK | SCL_MASK)); } }
static void checkboard(void) { u32 val_gpdat, board_rev_gpio; void __iomem *gpio_regs = (void __iomem *)MPC85xx_GPIO_ADDR; val_gpdat = in_be32(gpio_regs + MPC85xx_GPIO_GPDAT); board_rev_gpio = val_gpdat & BOARDREV_MASK; if ((board_rev_gpio != BOARDREV_C) && (board_rev_gpio != BOARDREV_B) && (board_rev_gpio != BOARDREV_D)) panic("Unexpected Board REV %x detected!!\n", board_rev_gpio); setbits_be32((gpio_regs + MPC85xx_GPIO_GPDIR), GPIO_DIR); /* * Bringing the following peripherals out of reset via GPIOs * 0 = reset and 1 = out of reset * GPIO12 - Reset to Ethernet Switch * GPIO13 - Reset to SLIC/SLAC devices * GPIO14 - Reset to SGMII_PHY_N * GPIO15 - Reset to PCIe slots * GPIO6 - Reset to RGMII PHY * GPIO5 - Reset to USB3300 devices 1 = reset and 0 = out of reset */ clrsetbits_be32((gpio_regs + MPC85xx_GPIO_GPDAT), USB_RST_CLR, BOARD_PERI_RST_SET); }
int board_early_init_f(void) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); setbits_be32(&gur->pmuxcr, (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP)); clrbits_be32(&gur->sdhcdcr, SDHCDCR_CD_INV); clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA); setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TDM_ENA); board_gpio_init(); board_cpld_init(); return 0; }
int fm_memac_mdio_init(bd_t *bis, struct memac_mdio_info *info) { struct mii_dev *bus = mdio_alloc(); if (!bus) { printf("Failed to allocate FM TGEC MDIO bus\n"); return -1; } bus->read = memac_mdio_read; bus->write = memac_mdio_write; bus->reset = memac_mdio_reset; sprintf(bus->name, info->name); bus->priv = info->regs; /* * On some platforms like B4860, default value of MDIO_CLK_DIV bits * in mdio_stat(mdio_cfg) register generates MDIO clock too high * (much higher than 2.5MHz), violating the IEEE specs. * On other platforms like T1040, default value of MDIO_CLK_DIV bits * is zero, so MDIO clock is disabled. * So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to * be properly initialized. * NEG bit default should be '1' as per FMAN-v3 RM, but on platform * like T2080QDS, this bit default is '0', which leads to MDIO failure * on XAUI PHY, so set this bit definitely. */ setbits_be32(&((struct memac_mdio_controller *)info->regs)->mdio_stat, MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG); return mdio_register(bus); }
void spi_cs_deactivate(struct spi_slave *slave) { immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; /* inactive high */ setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK); }
/* Input: <dev_addr> I2C address of EEPROM device to enable. * <state> -1: deliver current state * 0: disable write * 1: enable write * Returns: -1: wrong device address * 0: dis-/en- able done * 0/1: current state if <state> was -1. */ int eeprom_write_enable(unsigned dev_addr, int state) { struct ppc4xx_gpio *gpio0 = (struct ppc4xx_gpio *)GPIO_BASE; if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { return -1; } else { switch (state) { case 1: /* Enable write access, clear bit GPIO0. */ clrbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EEPROM_WP); state = 0; break; case 0: /* Disable write access, set bit GPIO0. */ setbits_be32(&gpio0->or, CONFIG_SYS_GPIO_EEPROM_WP); state = 0; break; default: /* Read current status back. */ state = (0 == (in_be32(&gpio0->or) & CONFIG_SYS_GPIO_EEPROM_WP)); break; } } return state; }
int board_eth_init(bd_t *bis) { ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR; struct fsl_pq_mdio_info dtsec_mdio_info; /* * Need to set dTSEC 1 pin multiplexing to TSEC. The default setting * is not correct. */ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1); dtsec_mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; /* Register the 1G MDIO bus */ fsl_pq_mdio_init(bis, &dtsec_mdio_info); fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); fm_info_set_mdio(FM1_DTSEC1, miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); fm_info_set_mdio(FM1_DTSEC2, miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); #ifdef CONFIG_FMAN_ENET cpu_eth_init(bis); #endif return pci_eth_init(bis); }
static void cpm_interrupt_init(void) { immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; uint cicr; /* * Initialize the CPM interrupt controller. */ cicr = CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1 | ((CPM_INTERRUPT / 2) << 13) | CICR_HP_MASK; out_be32(&immr->im_cpic.cpic_cicr, cicr); out_be32(&immr->im_cpic.cpic_cimr, 0); /* * Install the error handler. */ irq_install_handler(CPMVEC_ERROR, cpm_error_interrupt, NULL); setbits_be32(&immr->im_cpic.cpic_cicr, CICR_IEN); /* * Install the cpm interrupt handler */ irq_install_handler(CPM_INTERRUPT, cpm_interrupt, NULL); }
void fsl_lsch2_early_init_f(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR; struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; #ifdef CONFIG_LAYERSCAPE_NS_ACCESS enable_layerscape_ns_access(); #endif #ifdef CONFIG_FSL_IFC init_early_memctl_regs(); /* tighten IFC timing */ #endif #if defined(CONFIG_FSL_QSPI) && !defined(CONFIG_QSPI_BOOT) out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL); #endif /* Make SEC reads and writes snoopable */ setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SECRDSNP | SCFG_SNPCNFGCR_SECWRSNP | SCFG_SNPCNFGCR_SATARDSNP | SCFG_SNPCNFGCR_SATAWRSNP); /* * Enable snoop requests and DVM message requests for * Slave insterface S4 (A53 core cluster) */ out_le32(&cci->slave[4].snoop_ctrl, CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); /* Erratum */ erratum_a008850_early(); /* part 1 of 2 */ erratum_a009929(); erratum_a009660(); erratum_a010539(); }
/* * CPM interrupt handler */ static void cpm_interrupt(void *regs) { immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR; uint vec; /* * Get the vector by setting the ACK bit * and then reading the register. */ out_be16(&immr->im_cpic.cpic_civr, 1); vec = in_be16(&immr->im_cpic.cpic_civr); vec >>= 11; if (cpm_vecs[vec].handler != NULL) { (*cpm_vecs[vec].handler) (cpm_vecs[vec].arg); } else { clrbits_be32(&immr->im_cpic.cpic_cimr, 1 << vec); printf("Masking bogus CPM interrupt vector 0x%x\n", vec); } /* * After servicing the interrupt, * we have to remove the status indicator. */ setbits_be32(&immr->im_cpic.cpic_cisr, 1 << vec); }
int checkboard (void) { u32 val_gpdat, board_rev_gpio; volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); char board_rev = 0; struct cpu_type *cpu; val_gpdat = pgpio->gpdat; board_rev_gpio = val_gpdat & BOARDREV_MASK; if (board_rev_gpio == BOARDREV_C) board_rev = 'C'; else if (board_rev_gpio == BOARDREV_B) board_rev = 'B'; else panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio); cpu = gd->cpu; printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev); setbits_be32(&pgpio->gpdir, GPIO_DIR); /* * Bringing the following peripherals out of reset via GPIOs * 0 = reset and 1 = out of reset * GPIO12 - Reset to Ethernet Switch * GPIO13 - Reset to SLIC/SLAC devices * GPIO14 - Reset to SGMII_PHY_N * GPIO15 - Reset to PCIe slots * GPIO6 - Reset to RGMII PHY * GPIO5 - Reset to USB3300 devices 1 = reset and 0 = out of reset */ clrsetbits_be32(&pgpio->gpdat, USB_RST_CLR, BOARD_PERI_RST_SET); return 0; }
void dtimer_intr_setup(void) { intctrl_t *intp = (intctrl_t *) (CONFIG_SYS_INTR_BASE); clrbits_be32(&intp->int_icr1, INT_ICR1_TMR3MASK); setbits_be32(&intp->int_icr1, CONFIG_SYS_TMRINTR_PRI); }
/* Set up the buffers and their descriptors, and bring up the * interface */ static void startup_tsec(struct eth_device *dev) { int i; struct tsec_private *priv = (struct tsec_private *)dev->priv; tsec_t *regs = priv->regs; /* reset the indices to zero */ rxIdx = 0; txIdx = 0; #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 uint svr; #endif /* Point to the buffer descriptors */ out_be32(®s->tbase, (unsigned int)(&rtx.txbd[txIdx])); out_be32(®s->rbase, (unsigned int)(&rtx.rxbd[rxIdx])); /* Initialize the Rx Buffer descriptors */ for (i = 0; i < PKTBUFSRX; i++) { rtx.rxbd[i].status = RXBD_EMPTY; rtx.rxbd[i].length = 0; rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i]; } rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP; /* Initialize the TX Buffer Descriptors */ for (i = 0; i < TX_BUF_CNT; i++) { rtx.txbd[i].status = 0; rtx.txbd[i].length = 0; rtx.txbd[i].bufPtr = 0; } rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP; #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129 svr = get_svr(); if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) redundant_init(dev); #endif /* Enable Transmit and Receive */ setbits_be32(®s->maccfg1, MACCFG1_RX_EN | MACCFG1_TX_EN); /* Tell the DMA it is clear to go */ setbits_be32(®s->dmactrl, DMACTRL_INIT_SETTINGS); out_be32(®s->tstat, TSTAT_CLEAR_THALT); out_be32(®s->rstat, RSTAT_CLEAR_RHALT); clrbits_be32(®s->dmactrl, DMACTRL_GRS | DMACTRL_GTS); }
int board_early_init_f(void) { ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); #ifndef CONFIG_SDCARD struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR; /* Clock configuration to access CPLD using IFC(GPCM) */ setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); #endif /* * Reset PCIe slots via GPIO4 */ setbits_be32(&pgpio->gpdir, GPIO4_PCIE_RESET_SET); setbits_be32(&pgpio->gpdat, GPIO4_PCIE_RESET_SET); return 0; }
static int gfar_open(struct eth_device *edev) { int ix; struct gfar_private *priv = edev->priv; struct gfar_phy *phy = priv->gfar_mdio; void __iomem *regs = priv->regs; int ret; ret = phy_device_connect(edev, &phy->miibus, priv->phyaddr, gfar_adjust_link, 0, PHY_INTERFACE_MODE_NA); if (ret) return ret; /* Point to the buffer descriptors */ out_be32(regs + GFAR_TBASE0_OFFSET, (unsigned int)priv->txbd); out_be32(regs + GFAR_RBASE0_OFFSET, (unsigned int)priv->rxbd); /* Initialize the Rx Buffer descriptors */ for (ix = 0; ix < RX_BUF_CNT; ix++) { out_be16(&priv->rxbd[ix].status, RXBD_EMPTY); out_be16(&priv->rxbd[ix].length, 0); out_be32(&priv->rxbd[ix].bufPtr, (uint) NetRxPackets[ix]); } out_be16(&priv->rxbd[RX_BUF_CNT - 1].status, RXBD_EMPTY | RXBD_WRAP); /* Initialize the TX Buffer Descriptors */ for (ix = 0; ix < TX_BUF_CNT; ix++) { out_be16(&priv->txbd[ix].status, 0); out_be16(&priv->txbd[ix].length, 0); out_be32(&priv->txbd[ix].bufPtr, 0); } out_be16(&priv->txbd[TX_BUF_CNT - 1].status, TXBD_WRAP); /* Enable Transmit and Receive */ setbits_be32(regs + GFAR_MACCFG1_OFFSET, GFAR_MACCFG1_RX_EN | GFAR_MACCFG1_TX_EN); /* Tell the DMA it is clear to go */ setbits_be32(regs + GFAR_DMACTRL_OFFSET, DMACTRL_INIT_SETTINGS); out_be32(regs + GFAR_TSTAT_OFFSET, GFAR_TSTAT_CLEAR_THALT); out_be32(regs + GFAR_RSTAT_OFFSET, GFAR_RSTAT_CLEAR_RHALT); clrbits_be32(regs + GFAR_DMACTRL_OFFSET, GFAR_DMACTRL_GRS | GFAR_DMACTRL_GTS); return 0; }