void __init sh73a0_add_standard_devices_dt(void) { struct platform_device_info devinfo = { .name = "cpufreq-cpu0", .id = -1, }; /* clocks are setup late during boot in the case of DT */ sh73a0_clock_init(); platform_add_devices(sh73a0_devices_dt, ARRAY_SIZE(sh73a0_devices_dt)); of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); /* Instantiate cpufreq-cpu0 */ platform_device_register_full(&devinfo); } static const char *sh73a0_boards_compat_dt[] __initdata = { "renesas,sh73a0", NULL, }; DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)") .smp = smp_ops(sh73a0_smp_ops), .map_io = sh73a0_map_io, .init_early = sh73a0_init_delay, .nr_irqs = NR_IRQS_LEGACY, .init_machine = sh73a0_add_standard_devices_dt, .dt_compat = sh73a0_boards_compat_dt, MACHINE_END
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include <linux/init.h> #include <linux/irqchip.h> #include <linux/of_platform.h> #include <asm/mach/arch.h> #include "common.h" static void __init msm_dt_init(void) { of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } static const char * const msm8960_dt_match[] __initconst = { "qcom,msm8960-cdp", NULL }; DT_MACHINE_START(MSM8960_DT, "Qualcomm MSM (Flattened Device Tree)") .smp = smp_ops(msm_smp_ops), .map_io = msm_map_msm8960_io, .init_irq = irqchip_init, .init_time = msm_dt_timer_init, .init_machine = msm_dt_init, .dt_compat = msm8960_dt_match, MACHINE_END
}; #endif void __init mt_map_io(void) { iotable_init(mt_io_desc, ARRAY_SIZE(mt_io_desc)); } static void __init mt_dt_init_irq(void) { irqchip_init(); mt_init_irq(); } #ifdef CONFIG_OF DT_MACHINE_START(MT6580_DT, "MT6580") .map_io = mt_map_io, .smp = smp_ops(mt_smp_ops), /*.init_irq = mt_dt_init_irq,*/ /*.init_time = mt_timer_init,*/ .init_machine = mt_init, // .fixup = mt_dt_fixup, /* FIXME: need to implement the restart function */ .restart = arm_machine_restart, .reserve = mt_reserve, .dt_compat = mt_dt_match, MACHINE_END #endif
// ARM10C 20131005 // ARM10C 20131012 /* //static const struct machine_desc __mach_desc_EXYNOS5_DT \ // __used \ // __attribute__((__section__(".arch.info.init"))) = { \ // .nr = ~0, \ // .name = "SAMSUNG EXYNOS5 (Flattened Device Tree)", // .smp = smp_ops(exynos_smp_ops), // .map_io = exynos_init_io, // .init_machine = exynos5_dt_machine_init, // .init_late = exynos_init_late, // .init_time = exynos_init_time, // .dt_compat = exynos5_dt_compat, // .restart = exynos5_restart, // .reserve = exynos5_reserve, // }; */ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)") /* Maintainer: Kukjin Kim <*****@*****.**> */ .smp = smp_ops(exynos_smp_ops), // ARM10C 20131116 .map_io = exynos_init_io, .init_machine = exynos5_dt_machine_init, .init_late = exynos_init_late, .init_time = exynos_init_time, .dt_compat = exynos5_dt_compat, .restart = exynos5_restart, .reserve = exynos5_reserve, MACHINE_END
platform_device_register(&v2m_flash_device); platform_device_register(&v2m_cf_device); platform_device_register(&v2m_eth_device); platform_device_register(&v2m_usb_device); for (i = 0; i < ARRAY_SIZE(v2m_amba_devs); i++) amba_device_register(v2m_amba_devs[i], &iomem_resource); pm_power_off = v2m_power_off; ct_desc->init_tile(); } MACHINE_START(VEXPRESS, "ARM-Versatile Express") .atag_offset = 0x100, .smp = smp_ops(vexpress_smp_ops), .map_io = v2m_map_io, .init_early = v2m_init_early, .init_irq = v2m_init_irq, .timer = &v2m_timer, .handle_irq = gic_handle_irq, .init_machine = v2m_init, .restart = v2m_restart, MACHINE_END static struct map_desc v2m_rs1_io_desc __initdata = { .virtual = V2M_PERIPH, .pfn = __phys_to_pfn(0x1c000000), .length = SZ_2M, .type = MT_DEVICE, };
gpio_request(GPIO_FN_SD0_WP, NULL); /* HSPI 0 */ gpio_request(GPIO_FN_HSPI_CLK0, NULL); gpio_request(GPIO_FN_HSPI_CS0, NULL); gpio_request(GPIO_FN_HSPI_TX0, NULL); gpio_request(GPIO_FN_HSPI_RX0, NULL); /* USB (CN21) */ gpio_request(GPIO_FN_USB_OVC0, NULL); gpio_request(GPIO_FN_USB_OVC1, NULL); gpio_request(GPIO_FN_USB_OVC2, NULL); /* USB (CN22) */ gpio_request(GPIO_FN_USB_PENC2, NULL); r8a7779_add_standard_devices(); platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices)); } MACHINE_START(MARZEN, "marzen") .smp = smp_ops(r8a7779_smp_ops), .map_io = r8a7779_map_io, .init_early = r8a7779_add_early_devices, .nr_irqs = NR_IRQS_LEGACY, .init_irq = r8a7779_init_irq, .init_machine = marzen_init, .init_late = marzen_init_late, .init_time = r8a7779_earlytimer_init, MACHINE_END
}, }; static void __init sh73a0_map_io(void) { debug_ll_io_init(); iotable_init(sh73a0_io_desc, ARRAY_SIZE(sh73a0_io_desc)); } static void __init sh73a0_generic_init(void) { #ifdef CONFIG_CACHE_L2X0 /* Shared attribute override enable, 64K*8way */ l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff); #endif } static const char *const sh73a0_boards_compat_dt[] __initconst = { "renesas,sh73a0", NULL, }; DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)") .smp = smp_ops(sh73a0_smp_ops), .map_io = sh73a0_map_io, .init_early = shmobile_init_delay, .init_machine = sh73a0_generic_init, .init_late = shmobile_init_late, .dt_compat = sh73a0_boards_compat_dt, MACHINE_END
* You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. */ #include <linux/irqchip.h> #include <linux/of_irq.h> #include <linux/of_platform.h> #include <linux/smp.h> #include <asm/mach/arch.h> static void __init virt_init(void) { of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } static const char *virt_dt_match[] = { "linux,dummy-virt", "xen,xenvm", NULL }; extern struct smp_operations virt_smp_ops; DT_MACHINE_START(VIRT, "Dummy Virtual Machine") .init_irq = irqchip_init, .init_machine = virt_init, .smp = smp_ops(virt_smp_ops), .dt_compat = virt_dt_match, MACHINE_END
if (!np) { pr_err("failed to find hisilicon,sysctrl node\n"); return; } base = of_iomap(np, 0); if (!base) { pr_err("failed to map address in hisilicon,sysctrl node\n"); return; } if (of_property_read_u32(np, "reboot-offset", &offset) < 0) { pr_err("failed to find reboot-offset property\n"); return; } writel_relaxed(0xdeadbeef, base + offset); while (1) cpu_do_idle(); } static const char *hi3xxx_compat[] __initconst = { "hisilicon,hi3620-hi4511", NULL, }; DT_MACHINE_START(HI3620, "Hisilicon Hi3620 (Flattened Device Tree)") .map_io = hi3620_map_io, .dt_compat = hi3xxx_compat, .smp = smp_ops(hi3xxx_smp_ops), .restart = hi3xxx_restart, MACHINE_END
#endif }; void __init mt_map_io(void) { iotable_init(mt_io_desc, ARRAY_SIZE(mt_io_desc)); } #ifdef CONFIG_MTK_TABLET_HARDWARE MACHINE_START(MT8127, "MT8117") #else MACHINE_START(MT8127, "MT8127") #endif .atag_offset = 0x00000100, .map_io = mt_map_io, .init_irq = mt_init_irq, #if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0) .timer = &mt6582_timer, #else .smp = smp_ops(mt65xx_smp_ops), .init_time = mt6582_timer_init, #endif #if defined(CONFIG_TRUSTONIC_TEE_SUPPORT) || defined(CONFIG_MTK_IN_HOUSE_TEE_SUPPORT) .init_early = mt_init_early, #endif .init_machine = mt_init, .fixup = mt_fixup, .restart = arm_machine_restart, .reserve = mt_reserve, MACHINE_END
ARMADA_370_XP_MBUS_WINS_SIZE, ARMADA_370_XP_SDRAM_WINS_BASE, ARMADA_370_XP_SDRAM_WINS_SIZE); #ifdef CONFIG_CACHE_L2X0 l2x0_of_init(0, ~0UL); #endif } static void __init armada_370_xp_dt_init(void) { of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); coherency_init(); } static const char * const armada_370_xp_dt_compat[] = { "marvell,armada-370-xp", NULL, }; DT_MACHINE_START(ARMADA_XP_DT, "Marvell Armada 370/XP (Device Tree)") .smp = smp_ops(armada_xp_smp_ops), .init_machine = armada_370_xp_dt_init, .map_io = armada_370_xp_map_io, .init_early = armada_370_xp_init_early, .init_irq = irqchip_init, .init_time = armada_370_xp_timer_and_clk_init, .restart = mvebu_restart, .dt_compat = armada_370_xp_dt_compat, MACHINE_END
*/ static const struct clk_name clk_names[] __initconst = { { "du0", "du.0", "rcar-du-r8a7791" }, { "du1", "du.1", "rcar-du-r8a7791" }, { "lvds0", "lvds.0", "rcar-du-r8a7791" }, }; static void __init koelsch_add_standard_devices(void) { shmobile_clk_workaround(clk_names, ARRAY_SIZE(clk_names), false); of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); koelsch_add_du_device(); } static const char * const koelsch_boards_compat_dt[] __initconst = { "renesas,koelsch", "renesas,koelsch-reference", NULL, }; DT_MACHINE_START(KOELSCH_DT, "koelsch") .smp = smp_ops(r8a7791_smp_ops), .init_early = shmobile_init_delay, .init_time = rcar_gen2_timer_init, .init_machine = koelsch_add_standard_devices, .init_late = shmobile_init_late, .reserve = rcar_gen2_reserve, .dt_compat = koelsch_boards_compat_dt, MACHINE_END
writel(0, SEC_CTRL_ALTERNATIVE_SEL); writel(0, SEC_CTRL_PULLUP_SEL); /* No need to save any state, as the ROM loader can determine whether * reset is due to power cycling or programatic action, just hit the * (self-clearing) CPU reset bit of the block reset register */ value = BIT(SYS_CTRL_RST_SCU) | BIT(SYS_CTRL_RST_ARM0) | BIT(SYS_CTRL_RST_ARM1); writel(value, SYS_CTRL_RST_SET_CTRL); } static const char * const ox820_dt_board_compat[] = { "plxtech,nas7820", "plxtech,nas7821", "plxtech,nas7825", NULL }; DT_MACHINE_START(OX820_DT, "PLXTECH NAS782X SoC (Flattened Device Tree)") .map_io = ox820_map_common_io, .smp = smp_ops(ox820_smp_ops), .init_early = ox820_init_early, .init_time = ox820_timer_init, .init_machine = ox820_dt_init, .restart = ox820_assert_system_reset, .dt_compat = ox820_dt_board_compat, MACHINE_END
} void __init emev2_init_delay(void) { shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */ } static void __init emev2_add_standard_devices_dt(void) { #ifdef CONFIG_COMMON_CLK of_clk_init(NULL); #else emev2_clock_init(); #endif of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } static const char *emev2_boards_compat_dt[] __initdata = { "renesas,emev2", NULL, }; DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)") .smp = smp_ops(emev2_smp_ops), .map_io = emev2_map_io, .init_early = emev2_init_delay, .init_machine = emev2_add_standard_devices_dt, .init_late = shmobile_init_late, .dt_compat = emev2_boards_compat_dt, MACHINE_END
}; /* * Following will create 16MB static virtual/physical mappings * PHYSICAL VIRTUAL * 0xD8000000 0xFA000000 */ struct map_desc spear1310_io_desc[] __initdata = { { .virtual = VA_SPEAR1310_RAS_GRP1_BASE, .pfn = __phys_to_pfn(SPEAR1310_RAS_GRP1_BASE), .length = SZ_16M, .type = MT_DEVICE }, }; static void __init spear1310_map_io(void) { iotable_init(spear1310_io_desc, ARRAY_SIZE(spear1310_io_desc)); spear13xx_map_io(); } DT_MACHINE_START(SPEAR1310_DT, "ST SPEAr1310 SoC with Flattened Device Tree") .smp = smp_ops(spear13xx_smp_ops), .map_io = spear1310_map_io, .init_time = spear13xx_timer_init, .init_machine = spear1310_dt_init, .restart = spear_restart, .dt_compat = spear1310_dt_board_compat, MACHINE_END
void __init stih41x_l2x0_init(void) { u32 way_size = 0x4; u32 aux_ctrl; /* may be this can be encoded in macros like BIT*() */ aux_ctrl = (0x1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) | (0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) | (0x1 << L2X0_AUX_CTRL_INSTR_PREFETCH_SHIFT) | (way_size << L2X0_AUX_CTRL_WAY_SIZE_SHIFT); l2x0_of_init(aux_ctrl, L2X0_AUX_CTRL_MASK); } static void __init stih41x_machine_init(void) { stih41x_l2x0_init(); of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); } static const char *stih41x_dt_match[] __initdata = { "st,stih415", "st,stih416", NULL }; DT_MACHINE_START(STM, "STiH415/416 SoC with Flattened Device Tree") .init_machine = stih41x_machine_init, .smp = smp_ops(sti_smp_ops), .dt_compat = stih41x_dt_match, MACHINE_END
if (phys) { memblock_remove(phys, SZ_1M); memblock_reserve(phys, SZ_1M); ramoops_phys_addr = phys; ramoops_mem_size = SZ_1M; } else { ramoops_phys_addr = 0; ramoops_mem_size = 0; pr_err("no memory reserve for ramoops.\n"); } #endif return; } DT_MACHINE_START(IMX6Q, "Freescale i.MX6 Quad/DualLite (Device Tree)") /* * i.MX6Q/DL maps system memory at 0x10000000 (offset 256MiB), and * GPU has a limit on physical address that it accesses, which must * be below 2GiB. */ .dma_zone_size = (SZ_2G - SZ_256M), .smp = smp_ops(imx_smp_ops), .map_io = imx6q_map_io, .init_irq = imx6q_init_irq, .init_machine = imx6q_init_machine, .init_late = imx6q_init_late, .dt_compat = imx6q_dt_compat, .reserve = imx6q_reserve, .restart = mxc_restart, MACHINE_END
/* disable remap */ writel_relaxed(1 << (12 + 16), RK_GRF_VIRT + RK3188_GRF_SOC_CON0); /* pll enter slow mode */ writel_relaxed(RK3188_PLL_MODE_SLOW(RK3188_APLL_ID) | RK3188_PLL_MODE_SLOW(RK3188_CPLL_ID) | RK3188_PLL_MODE_SLOW(RK3188_GPLL_ID), RK_CRU_VIRT + RK3188_CRU_MODE_CON); dsb(); writel_relaxed(0xeca8, RK_CRU_VIRT + RK3188_CRU_GLB_SRST_SND); dsb(); } #ifdef CONFIG_PM static void __init rk3188_init_suspend(void); #endif DT_MACHINE_START(RK3188_DT, "RK30board") .smp = smp_ops(rockchip_smp_ops), .map_io = rk3188_dt_map_io, .init_time = rk3188_dt_init_timer, .dt_compat = rk3188_dt_compat, #ifdef CONFIG_PM .init_late = rk3188_init_suspend, #endif .reserve = rk3188_reserve, .restart = rk3188_restart, MACHINE_END #define CPU 3188 char PIE_DATA(sram_stack)[1024]; EXPORT_PIE_SYMBOL(DATA(sram_stack)); static int __init rk3188_pie_init(void)
* bounce on and off after each packet, which we apparently want to avoid. */ static int lager_ksz8041_fixup(struct phy_device *phydev) { u16 phyctrl1 = phy_read(phydev, 0x1e); phyctrl1 &= ~0xc000; phyctrl1 |= 0x4000; return phy_write(phydev, 0x1e, phyctrl1); } static void __init lager_init(void) { lager_add_standard_devices(); phy_register_fixup_for_id("r8a7790-ether-ff:01", lager_ksz8041_fixup); } static const char * const lager_boards_compat_dt[] __initconst = { "renesas,lager", NULL, }; DT_MACHINE_START(LAGER_DT, "lager") .smp = smp_ops(r8a7790_smp_ops), .init_early = r8a7790_init_early, .init_time = rcar_gen2_timer_init, .init_machine = lager_init, .dt_compat = lager_boards_compat_dt, MACHINE_END
#endif #ifdef CONFIG_ARCH_PRIMA2 static const char *const prima2_dt_match[] __initconst = { "sirf,prima2", NULL }; DT_MACHINE_START(PRIMA2_DT, "Generic PRIMA2 (Flattened Device Tree)") /* Maintainer: Barry Song <*****@*****.**> */ .l2c_aux_val = 0, .l2c_aux_mask = ~0, .dma_zone_size = SZ_256M, .init_late = sirfsoc_init_late, .dt_compat = prima2_dt_match, MACHINE_END #endif #ifdef CONFIG_ARCH_ATLAS7 static const char *const atlas7_dt_match[] __initconst = { "sirf,atlas7", NULL }; DT_MACHINE_START(ATLAS7_DT, "Generic ATLAS7 (Flattened Device Tree)") /* Maintainer: Barry Song <*****@*****.**> */ .smp = smp_ops(sirfsoc_smp_ops), .dt_compat = atlas7_dt_match, MACHINE_END #endif
.init_late = am33xx_init_late, .init_time = omap3_gptimer_timer_init, .dt_compat = am33xx_boards_compat, .restart = am33xx_restart, MACHINE_END #endif #ifdef CONFIG_ARCH_OMAP4 static const char *omap4_boards_compat[] __initdata = { "ti,omap4", NULL, }; DT_MACHINE_START(OMAP4_DT, "Generic OMAP4 (Flattened Device Tree)") .reserve = omap_reserve, .smp = smp_ops(omap4_smp_ops), .map_io = omap4_map_io, .init_early = omap4430_init_early, .init_irq = omap_gic_of_init, .init_machine = omap_generic_init, .init_late = omap4430_init_late, .init_time = omap4_local_timer_init, .dt_compat = omap4_boards_compat, .restart = omap44xx_restart, MACHINE_END #endif #ifdef CONFIG_SOC_OMAP5 static const char *omap5_boards_compat[] __initdata = { "ti,omap5", NULL,
realview_flash_register(realview_pb11mp_flash_resource, ARRAY_SIZE(realview_pb11mp_flash_resource)); realview_eth_register(NULL, realview_pb11mp_smsc911x_resources); platform_device_register(&realview_i2c_device); platform_device_register(&realview_cf_device); realview_usb_register(realview_pb11mp_isp1761_resources); platform_device_register(&pmu_device); for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { struct amba_device *d = amba_devs[i]; amba_device_register(d, &iomem_resource); } } MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore") /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ .atag_offset = 0x100, .smp = smp_ops(realview_smp_ops), .fixup = realview_fixup, .map_io = realview_pb11mp_map_io, .init_early = realview_init_early, .init_irq = gic_init_irq, .init_time = realview_pb11mp_timer_init, .init_machine = realview_pb11mp_init, #ifdef CONFIG_ZONE_DMA .dma_zone_size = SZ_256M, #endif .restart = realview_pb11mp_restart, MACHINE_END
i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES; i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs); i2c_register_board_info(2, mop500_i2c2_devices, ARRAY_SIZE(mop500_i2c2_devices)); /* This board has full regulator constraints */ regulator_has_full_constraints(); } MACHINE_START(U8500, "ST-Ericsson MOP500 platform") /* Maintainer: Srinidhi Kasagar <*****@*****.**> */ .atag_offset = 0x100, .smp = smp_ops(ux500_smp_ops), .map_io = u8500_map_io, .init_irq = ux500_init_irq, /* we re-use nomadik timer here */ .timer = &ux500_timer, .handle_irq = gic_handle_irq, .init_machine = mop500_init_machine, .init_late = ux500_init_late, MACHINE_END MACHINE_START(U8520, "ST-Ericsson U8520 Platform HREFP520") .atag_offset = 0x100, .map_io = u8500_map_io, .init_irq = ux500_init_irq, .timer = &ux500_timer, .handle_irq = gic_handle_irq,
(u64)mem_start, (u64)mem_end); return 0; } offset = KEYSTONE_HIGH_PHYS_START - KEYSTONE_LOW_PHYS_START; /* Populate the arch idmap hook */ arch_phys_to_idmap_offset = -offset; return offset; } static const char *const keystone_match[] __initconst = { "ti,k2hk", "ti,k2e", "ti,k2l", "ti,k2g", "ti,keystone", NULL, }; DT_MACHINE_START(KEYSTONE, "Keystone") #if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE) .dma_zone_size = SZ_2G, #endif .smp = smp_ops(keystone_smp_ops), .init_machine = keystone_init, .dt_compat = keystone_match, .pv_fixup = keystone_pv_fixup, MACHINE_END
"allwinner,sun6i-a31", NULL, }; extern void __init sun6i_reset_init(void); static void __init sun6i_timer_init(void) { of_clk_init(NULL); sun6i_reset_init(); clocksource_of_init(); } DT_MACHINE_START(SUN6I_DT, "Allwinner sun6i (A31) Family") .init_machine = sunxi_dt_init, .init_time = sun6i_timer_init, .dt_compat = sun6i_board_dt_compat, .restart = sun6i_restart, .smp = smp_ops(sun6i_smp_ops), MACHINE_END static const char * const sun7i_board_dt_compat[] = { "allwinner,sun7i-a20", NULL, }; DT_MACHINE_START(SUN7I_DT, "Allwinner sun7i (A20) Family") .init_machine = sunxi_dt_init, .dt_compat = sun7i_board_dt_compat, .restart = sun4i_restart, MACHINE_END
clocksource_of_init(); }else{ sci_clock_init(); sci_enable_timer_early(); sci_timer_init(); } } static const char *sprd_boards_compat[] __initdata = { "sprd,sp8835eb", NULL, }; #endif extern struct smp_operations sprd_smp_ops; MACHINE_START(SCPHONE, "sc8830") .smp = smp_ops(sprd_smp_ops), .reserve = sci_reserve, .map_io = sci_map_io, .init_early = sc8830_init_early, .init_irq = sci_init_irq, #ifdef CONFIG_OF .init_time = sprd_init_time, #else .init_time = sci_timer_init, #endif .init_machine = sc8830_init_machine, .init_late = sc8830_init_late, #ifdef CONFIG_OF .dt_compat = sprd_boards_compat, #endif MACHINE_END
tegra_init_suspend(); tegra_cpuidle_init(); tegra_powergate_debugfs_init(); for (i = 0; i < ARRAY_SIZE(board_init_funcs); i++) { if (of_machine_is_compatible(board_init_funcs[i].machine)) { board_init_funcs[i].init(); break; } } } static const char * const tegra_dt_board_compat[] = { "nvidia,tegra124", "nvidia,tegra114", "nvidia,tegra30", "nvidia,tegra20", NULL }; DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)") .map_io = tegra_map_common_io, .smp = smp_ops(tegra_smp_ops), .init_early = tegra_init_early, .init_irq = tegra_dt_init_irq, .init_machine = tegra_dt_init, .init_late = tegra_dt_init_late, .restart = tegra_pmc_restart, .dt_compat = tegra_dt_board_compat, MACHINE_END
static void __init koelsch_add_rsnd_device(void) { struct resource rsnd_resources[] = { [RSND_GEN2_SCU] = DEFINE_RES_MEM(0xec500000, 0x1000), [RSND_GEN2_ADG] = DEFINE_RES_MEM(0xec5a0000, 0x100), [RSND_GEN2_SSIU] = DEFINE_RES_MEM(0xec540000, 0x1000), [RSND_GEN2_SSI] = DEFINE_RES_MEM(0xec541000, 0x1280), }; struct platform_device_info cardinfo = { .parent = &platform_bus, .name = "asoc-simple-card", .id = -1, .data = &rsnd_card_info, .size_data = sizeof(struct asoc_simple_card_info), .dma_mask = DMA_BIT_MASK(32), }; platform_device_register_resndata( &platform_bus, "rcar_sound", -1, rsnd_resources, ARRAY_SIZE(rsnd_resources), &rsnd_info, sizeof(rsnd_info)); platform_device_register_full(&cardinfo); } /* * This is a really crude hack to provide clkdev support to platform * devices until they get moved to DT. */ static const struct clk_name clk_names[] __initconst = { { "cmt0", NULL, "sh_cmt.0" }, { "cmt0", "fck", "sh-cmt-48-gen2.0" }, { "du0", "du.0", "rcar-du-r8a7791" }, { "du1", "du.1", "rcar-du-r8a7791" }, { "lvds0", "lvds.0", "rcar-du-r8a7791" }, { "hsusb", NULL, "usb_phy_rcar_gen2" }, { "ssi0", "ssi.0", "rcar_sound" }, { "ssi1", "ssi.1", "rcar_sound" }, { "src0", "src.0", "rcar_sound" }, { "src1", "src.1", "rcar_sound" }, { "dvc0", "dvc.0", "rcar_sound" }, { "vin0", NULL, "r8a7791-vin.0" }, { "vin1", NULL, "r8a7791-vin.1" }, { "vsps", NULL, NULL }, #if defined(CONFIG_VIDEO_RENESAS_VSP1) { "vsp1-du0", NULL, "vsp1.2" }, { "vsp1-du1", NULL, "vsp1.3" }, #else { "vsp1-du0", NULL, NULL }, { "vsp1-du1", NULL, NULL }, #endif { "vcp0", NULL, NULL }, { "vpc0", NULL, NULL }, { "tddmac", NULL, NULL }, { "fdp1", NULL, NULL }, { "fdp0", NULL, NULL }, }; /* * This is a really crude hack to work around core platform clock issues */ static const struct clk_name clk_enables[] __initconst = { { "hsusb", NULL, "renesas_usbhs" }, { "ehci", NULL, "pci-rcar-gen2.1" }, { "ssi", NULL, "rcar_sound" }, { "scu", NULL, "rcar_sound" }, { "dmal", NULL, "sh-dma-engine.0" }, { "dmah", NULL, "sh-dma-engine.1" }, { "pvrsrvkm", NULL, "pvrsrvkm" }, { "ssp_dev", NULL, "ssp_dev" }, }; #define DMAE_CHANNEL(a, b) \ { \ .offset = (a) - 0x20, \ .dmars = (a) - 0x20 + 0x40, \ .chclr_bit = (b), \ .chclr_offset = 0x80 - 0x20, \ } /* Sys-DMAC */ #define SYS_DMAC_SLAVE(_id, _bit, _addr, toffset, roffset, t, r) \ { \ .slave_id = SYS_DMAC_SLAVE_## _id ##_TX, \ .addr = _addr + toffset, \ .chcr = CHCR_TX(XMIT_SZ_## _bit ##BIT), \ .mid_rid = t, \ }, { \ .slave_id = SYS_DMAC_SLAVE_## _id ##_RX, \ .addr = _addr + roffset, \ .chcr = CHCR_RX(XMIT_SZ_## _bit ##BIT), \ .mid_rid = r, \ } static const struct sh_dmae_slave_config r8a7791_sys_dmac_slaves[] = { SYS_DMAC_SLAVE(SDHI0, 256, 0xee100000, 0x60, 0x2060, 0xcd, 0xce), SYS_DMAC_SLAVE(SDHI1, 256, 0xee140000, 0x30, 0x2030, 0xc1, 0xc2), SYS_DMAC_SLAVE(SDHI2, 256, 0xee160000, 0x30, 0x2030, 0xd3, 0xd4), }; static const struct sh_dmae_channel r8a7791_sys_dmac_channels[] = { DMAE_CHANNEL(0x8000, 0), DMAE_CHANNEL(0x8080, 1), DMAE_CHANNEL(0x8100, 2), DMAE_CHANNEL(0x8180, 3), DMAE_CHANNEL(0x8200, 4), DMAE_CHANNEL(0x8280, 5), DMAE_CHANNEL(0x8300, 6), DMAE_CHANNEL(0x8380, 7), DMAE_CHANNEL(0x8400, 8), DMAE_CHANNEL(0x8480, 9), DMAE_CHANNEL(0x8500, 10), DMAE_CHANNEL(0x8580, 11), DMAE_CHANNEL(0x8600, 12), DMAE_CHANNEL(0x8680, 13), DMAE_CHANNEL(0x8700, 14), }; static struct sh_dmae_pdata r8a7791_sys_dmac_platform_data = { .slave = r8a7791_sys_dmac_slaves, .slave_num = ARRAY_SIZE(r8a7791_sys_dmac_slaves), .channel = r8a7791_sys_dmac_channels, .channel_num = ARRAY_SIZE(r8a7791_sys_dmac_channels), .ts_low_shift = TS_LOW_SHIFT, .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT, .ts_high_shift = TS_HI_SHIFT, .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT, .ts_shift = dma_ts_shift, .ts_shift_num = ARRAY_SIZE(dma_ts_shift), .dmaor_init = DMAOR_DME, .chclr_present = 1, .chclr_bitwise = 1, .fourty_bits_addr = 1, }; static struct resource r8a7791_sys_dmac_resources[] = { /* Channel registers and DMAOR for low */ DEFINE_RES_MEM(0xe6700020, 0x8763 - 0x20), DEFINE_RES_IRQ(gic_spi(197)), DEFINE_RES_NAMED(gic_spi(200), 15, NULL, IORESOURCE_IRQ), /* Channel registers and DMAOR for high */ DEFINE_RES_MEM(0xe6720020, 0x8763 - 0x20), DEFINE_RES_IRQ(gic_spi(220)), DEFINE_RES_NAMED(gic_spi(216), 4, NULL, IORESOURCE_IRQ), DEFINE_RES_NAMED(gic_spi(308), 11, NULL, IORESOURCE_IRQ), }; #define r8a7791_register_sys_dmac(id) \ platform_device_register_resndata( \ &platform_bus, "sh-dma-engine", 2 + id, \ &r8a7791_sys_dmac_resources[id * 3], id * 1 + 3, \ &r8a7791_sys_dmac_platform_data, \ sizeof(r8a7791_sys_dmac_platform_data)) static void __init koelsch_add_dmac_prototype(void) { r8a7791_register_sys_dmac(0); r8a7791_register_sys_dmac(1); } static struct sh_mobile_sdhi_info sdhi0_info __initdata = { .dma_slave_tx = SYS_DMAC_SLAVE_SDHI0_TX, .dma_slave_rx = SYS_DMAC_SLAVE_SDHI0_RX, .dma_rx_offset = 0x2000, .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | MMC_CAP_POWER_OFF_CARD, .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT, }; static struct sh_mobile_sdhi_info sdhi1_info __initdata = { .dma_slave_tx = SYS_DMAC_SLAVE_SDHI1_TX, .dma_slave_rx = SYS_DMAC_SLAVE_SDHI1_RX, .tmio_caps = MMC_CAP_POWER_OFF_CARD, .dma_rx_offset = 0x2000, .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | MMC_CAP_POWER_OFF_CARD, .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT, }; static struct sh_mobile_sdhi_info sdhi2_info __initdata = { .dma_slave_tx = SYS_DMAC_SLAVE_SDHI2_TX, .dma_slave_rx = SYS_DMAC_SLAVE_SDHI2_RX, .dma_rx_offset = 0x2000, .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | MMC_CAP_POWER_OFF_CARD, .tmio_caps = MMC_CAP_POWER_OFF_CARD, .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_WRPROTECT_DISABLE, }; /* USBHS */ static const struct resource usbhs_resources[] __initconst = { DEFINE_RES_MEM(0xe6590000, 0x100), DEFINE_RES_IRQ(gic_spi(107)), }; struct usbhs_private { struct renesas_usbhs_platform_info info; struct usb_phy *phy; int id_gpio; }; #define usbhs_get_priv(pdev) \ container_of(renesas_usbhs_get_info(pdev), struct usbhs_private, info) static int usbhs_power_ctrl(struct platform_device *pdev, void __iomem *base, int enable) { struct usbhs_private *priv = usbhs_get_priv(pdev); if (!priv->phy) return -ENODEV; if (enable) { int retval = usb_phy_init(priv->phy); if (!retval) retval = usb_phy_set_suspend(priv->phy, 0); return retval; } usb_phy_set_suspend(priv->phy, 1); usb_phy_shutdown(priv->phy); return 0; } static int usbhs_hardware_init(struct platform_device *pdev) { struct usbhs_private *priv = usbhs_get_priv(pdev); struct usb_phy *phy; int ret; struct device_node *np; np = of_find_node_by_path("/gpio@e6055000"); if (np) { priv->id_gpio = of_get_gpio(np, 31); of_node_put(np); } else { pr_warn("Error: Unable to get MAX3355 ID input\n"); ret = -ENOTSUPP; goto error2; } /* Check MAX3355E ID pin */ gpio_request_one(priv->id_gpio, GPIOF_IN, NULL); if (!gpio_get_value(priv->id_gpio)) { pr_warn("Error: USB0 cable selects host mode\n"); ret = -ENOTSUPP; goto error; } phy = usb_get_phy_dev(&pdev->dev, 0); if (IS_ERR(phy)) return PTR_ERR(phy); priv->phy = phy; return 0; error: gpio_free(priv->id_gpio); error2: return ret; } static int usbhs_hardware_exit(struct platform_device *pdev) { struct usbhs_private *priv = usbhs_get_priv(pdev); if (!priv->phy) return 0; usb_put_phy(priv->phy); priv->phy = NULL; gpio_free(priv->id_gpio); return 0; } static int usbhs_get_id(struct platform_device *pdev) { return USBHS_GADGET; } static u32 koelsch_usbhs_pipe_type[] = { USB_ENDPOINT_XFER_CONTROL, USB_ENDPOINT_XFER_ISOC, USB_ENDPOINT_XFER_ISOC, USB_ENDPOINT_XFER_BULK, USB_ENDPOINT_XFER_BULK, USB_ENDPOINT_XFER_BULK, USB_ENDPOINT_XFER_INT, USB_ENDPOINT_XFER_INT, USB_ENDPOINT_XFER_INT, USB_ENDPOINT_XFER_BULK, USB_ENDPOINT_XFER_BULK, USB_ENDPOINT_XFER_BULK, USB_ENDPOINT_XFER_BULK, USB_ENDPOINT_XFER_BULK, USB_ENDPOINT_XFER_BULK, USB_ENDPOINT_XFER_BULK, }; static struct usbhs_private usbhs_priv __initdata = { .info = { .platform_callback = { .power_ctrl = usbhs_power_ctrl, .hardware_init = usbhs_hardware_init, .hardware_exit = usbhs_hardware_exit, .get_id = usbhs_get_id, }, .driver_param = { .buswait_bwait = 4, .pipe_type = koelsch_usbhs_pipe_type, .pipe_size = ARRAY_SIZE(koelsch_usbhs_pipe_type), }, } }; static void __init koelsch_add_usb0_gadget(void) { usb_bind_phy("renesas_usbhs", 0, "usb_phy_rcar_gen2"); platform_device_register_resndata(&platform_bus, "renesas_usbhs", -1, usbhs_resources, ARRAY_SIZE(usbhs_resources), &usbhs_priv.info, sizeof(usbhs_priv.info)); } /* Internal PCI1 */ static const struct resource pci1_resources[] __initconst = { DEFINE_RES_MEM(0xee0d0000, 0x10000), /* CFG */ DEFINE_RES_MEM(0xee0c0000, 0x10000), /* MEM */ DEFINE_RES_IRQ(gic_spi(113)), }; static void __init koelsch_add_usb1_host(void) { platform_device_register_simple("pci-rcar-gen2", 1, pci1_resources, ARRAY_SIZE(pci1_resources)); } /* USBHS PHY */ static const struct rcar_gen2_phy_platform_data usbhs_phy_pdata __initconst = { .chan0_pci = 0, /* Channel 0 is USBHS */ .chan2_pci = 1, /* Channel 2 is PCI USB host */ }; /* VIN */ static const struct resource vin_resources[] __initconst = { /* VIN0 */ DEFINE_RES_MEM(0xe6ef0000, 0x1000), DEFINE_RES_IRQ(gic_spi(188)), /* VIN1 */ DEFINE_RES_MEM(0xe6ef1000, 0x1000), DEFINE_RES_IRQ(gic_spi(189)), }; static void __init koelsch_add_vin_device(unsigned idx, struct rcar_vin_platform_data *pdata) { struct platform_device_info vin_info = { .parent = &platform_bus, .name = "r8a7791-vin", .id = idx, .res = &vin_resources[idx * 2], .num_res = 2, .dma_mask = DMA_BIT_MASK(32), .data = pdata, .size_data = sizeof(*pdata), }; BUG_ON(idx > 1); platform_device_register_full(&vin_info); } #define KOELSCH_CAMERA(idx, name, addr, pdata, flag) \ static struct i2c_board_info i2c_cam##idx##_device = { \ I2C_BOARD_INFO(name, addr), \ }; \ \ static struct rcar_vin_platform_data vin##idx##_pdata = { \ .flags = flag, \ }; \ \ static struct soc_camera_link cam##idx##_link = { \ .bus_id = idx, \ .board_info = &i2c_cam##idx##_device, \ .i2c_adapter_id = 2, \ .module_name = name, \ .priv = pdata, \ } KOELSCH_CAMERA(0, "adv7612", 0x4c, NULL, RCAR_VIN_BT709); KOELSCH_CAMERA(1, "adv7180", 0x20, NULL, RCAR_VIN_BT656); static void __init koelsch_add_camera0_device(void) { platform_device_register_data(&platform_bus, "soc-camera-pdrv", 0, &cam0_link, sizeof(cam0_link)); koelsch_add_vin_device(0, &vin0_pdata); } static void __init koelsch_add_camera1_device(void) { platform_device_register_data(&platform_bus, "soc-camera-pdrv", 1, &cam1_link, sizeof(cam1_link)); koelsch_add_vin_device(1, &vin1_pdata); } /* VSP1 */ #if defined(CONFIG_VIDEO_RENESAS_VSP1) static const struct vsp1_platform_data koelsch_vsps_pdata __initconst = { .features = 0, .rpf_count = 5, .uds_count = 3, .wpf_count = 4, }; static const struct vsp1_platform_data koelsch_vspd0_pdata __initconst = { .features = VSP1_HAS_LIF, .rpf_count = 4, .uds_count = 1, .wpf_count = 4, }; static const struct vsp1_platform_data koelsch_vspd1_pdata __initconst = { .features = VSP1_HAS_LIF, .rpf_count = 4, .uds_count = 1, .wpf_count = 4, }; static const struct vsp1_platform_data * const koelsch_vsp1_pdata[] __initconst = { &koelsch_vsps_pdata, &koelsch_vspd0_pdata, &koelsch_vspd1_pdata, }; static const struct resource vsp1_1_resources[] __initconst = { DEFINE_RES_MEM(0xfe928000, 0x8000), DEFINE_RES_IRQ(gic_spi(267)), }; static const struct resource vsp1_2_resources[] __initconst = { DEFINE_RES_MEM(0xfe930000, 0x8000), DEFINE_RES_IRQ(gic_spi(246)), }; static const struct resource vsp1_3_resources[] __initconst = { DEFINE_RES_MEM(0xfe938000, 0x8000), DEFINE_RES_IRQ(gic_spi(247)), }; static const struct resource * const vsp1_resources[] __initconst = { vsp1_1_resources, vsp1_2_resources, vsp1_3_resources, }; static void __init koelsch_add_vsp1_devices(void) { struct platform_device_info info = { .name = "vsp1", .size_data = sizeof(*koelsch_vsp1_pdata[0]), .num_res = 2, .dma_mask = DMA_BIT_MASK(32), }; unsigned int i; for (i = 1; i < ARRAY_SIZE(vsp1_resources); ++i) { info.id = i + 1; info.data = koelsch_vsp1_pdata[i]; info.res = vsp1_resources[i]; platform_device_register_full(&info); } } #endif static const struct resource usbhs_phy_resources[] __initconst = { DEFINE_RES_MEM(0xe6590100, 0x100), }; /* Add all available USB devices */ static void __init koelsch_add_usb_devices(void) { platform_device_register_resndata(&platform_bus, "usb_phy_rcar_gen2", -1, usbhs_phy_resources, ARRAY_SIZE(usbhs_phy_resources), &usbhs_phy_pdata, sizeof(usbhs_phy_pdata)); koelsch_add_usb0_gadget(); koelsch_add_usb1_host(); } /* MSIOF spidev */ static const struct spi_board_info spi_bus[] __initconst = { { .modalias = "spidev", .max_speed_hz = 6000000, .mode = SPI_MODE_3, .bus_num = 1, .chip_select = 0, }, { .modalias = "spidev", .max_speed_hz = 6000000, .mode = SPI_MODE_3, .bus_num = 2, .chip_select = 0, }, }; /* POWER IC */ static struct i2c_board_info poweric_i2c[] = { { I2C_BOARD_INFO("da9063", 0x58), }, }; static void koelsch_restart(char mode, const char *cmd) { struct i2c_adapter *adap; struct i2c_client *client; u8 val; int busnum = 6; adap = i2c_get_adapter(busnum); if (!adap) { pr_err("failed to get adapter i2c%d\n", busnum); return; } client = i2c_new_device(adap, &poweric_i2c[0]); if (!client) pr_err("failed to register %s to i2c%d\n", poweric_i2c[0].type, busnum); i2c_put_adapter(adap); val = i2c_smbus_read_byte_data(client, 0x13); if (val < 0) pr_err("couldn't access da9063\n"); val |= 0x02; i2c_smbus_write_byte_data(client, 0x13, val); } #define koelsch_add_msiof_device spi_register_board_info static struct of_dev_auxdata koelsch_auxdata_lookup[] __initdata = { OF_DEV_AUXDATA("renesas,sdhi-r8a7791", 0xee100000, "sdhi0", &sdhi0_info), OF_DEV_AUXDATA("renesas,sdhi-r8a7791", 0xee140000, "sdhi1", &sdhi1_info), OF_DEV_AUXDATA("renesas,sdhi-r8a7791", 0xee160000, "sdhi2", &sdhi2_info), {}, }; static void __init koelsch_add_standard_devices(void) { shmobile_clk_workaround(clk_names, ARRAY_SIZE(clk_names), false); shmobile_clk_workaround(clk_enables, ARRAY_SIZE(clk_enables), true); r8a7791_add_dt_devices(); koelsch_add_dmac_prototype(); of_platform_populate(NULL, of_default_bus_match_table, koelsch_auxdata_lookup, NULL); koelsch_add_du_device(); koelsch_add_usb_devices(); koelsch_add_rsnd_device(); koelsch_add_camera0_device(); koelsch_add_camera1_device(); #if defined(CONFIG_VIDEO_RENESAS_VSP1) koelsch_add_vsp1_devices(); #endif koelsch_add_msiof_device(spi_bus, ARRAY_SIZE(spi_bus)); } static const char * const koelsch_boards_compat_dt[] __initconst = { "renesas,koelsch", "renesas,koelsch-reference", NULL, }; DT_MACHINE_START(KOELSCH_DT, "koelsch") .smp = smp_ops(r8a7791_smp_ops), .init_early = shmobile_init_delay, .init_time = rcar_gen2_timer_init, .init_machine = koelsch_add_standard_devices, .init_late = shmobile_init_late, .reserve = rcar_gen2_reserve, .restart = koelsch_restart, .dt_compat = koelsch_boards_compat_dt, MACHINE_END