void prvSetupHardware( void )
{
/* Initialise the port used for the LED outputs. */
vParTestInitialise();
}
static void prvSetupHardware( void )
{
/* Initialise LED outputs. */
vParTestInitialise();
}
void prvSetupHardware( void )
{
/* Disable peripherals power. */
SC->PCONP = 0;
/* Enable GPIO power. */
SC->PCONP = PCONP_PCGPIO;
/* Disable TPIU. */
PINCON->PINSEL10 = 0;
if ( SC->PLL0STAT & ( 1 << 25 ) )
{
/* Enable PLL, disconnected. */
SC->PLL0CON = 1;
SC->PLL0FEED = PLLFEED_FEED1;
SC->PLL0FEED = PLLFEED_FEED2;
}
/* Disable PLL, disconnected. */
SC->PLL0CON = 0;
SC->PLL0FEED = PLLFEED_FEED1;
SC->PLL0FEED = PLLFEED_FEED2;
/* Enable main OSC. */
SC->SCS |= 0x20;
while( !( SC->SCS & 0x40 ) );
/* select main OSC, 12MHz, as the PLL clock source. */
SC->CLKSRCSEL = 0x1;
SC->PLL0CFG = 0x20031;
SC->PLL0FEED = PLLFEED_FEED1;
SC->PLL0FEED = PLLFEED_FEED2;
/* Enable PLL, disconnected. */
SC->PLL0CON = 1;
SC->PLL0FEED = PLLFEED_FEED1;
SC->PLL0FEED = PLLFEED_FEED2;
/* Set clock divider. */
SC->CCLKCFG = 0x03;
/* Configure flash accelerator. */
SC->FLASHCFG = 0x403a;
/* Check lock bit status. */
while( ( ( SC->PLL0STAT & ( 1 << 26 ) ) == 0 ) );
/* Enable and connect. */
SC->PLL0CON = 3;
SC->PLL0FEED = PLLFEED_FEED1;
SC->PLL0FEED = PLLFEED_FEED2;
while( ( ( SC->PLL0STAT & ( 1 << 25 ) ) == 0 ) );
/* Configure the clock for the USB. */
if( SC->PLL1STAT & ( 1 << 9 ) )
{
/* Enable PLL, disconnected. */
SC->PLL1CON = 1;
SC->PLL1FEED = PLLFEED_FEED1;
SC->PLL1FEED = PLLFEED_FEED2;
}
/* Disable PLL, disconnected. */
SC->PLL1CON = 0;
SC->PLL1FEED = PLLFEED_FEED1;
SC->PLL1FEED = PLLFEED_FEED2;
SC->PLL1CFG = 0x23;
SC->PLL1FEED = PLLFEED_FEED1;
SC->PLL1FEED = PLLFEED_FEED2;
/* Enable PLL, disconnected. */
SC->PLL1CON = 1;
SC->PLL1FEED = PLLFEED_FEED1;
SC->PLL1FEED = PLLFEED_FEED2;
while( ( ( SC->PLL1STAT & ( 1 << 10 ) ) == 0 ) );
/* Enable and connect. */
SC->PLL1CON = 3;
SC->PLL1FEED = PLLFEED_FEED1;
SC->PLL1FEED = PLLFEED_FEED2;
while( ( ( SC->PLL1STAT & ( 1 << 9 ) ) == 0 ) );
/* Setup the peripheral bus to be the same as the PLL output (64 MHz). */
SC->PCLKSEL0 = 0x05555555;
/* Configure the LEDs. */
vParTestInitialise();
}
static void prvSetupHardware( void )
{
vParTestInitialise();
}
static void prvSetupHardware( void )
{
SystemCoreClockUpdate();
vParTestInitialise();
}
static void prvSetupHardware( void )
{
long lCount;
#ifdef RUN_FROM_ROM
{
portFLOAT nsecsPerClockTick;
long lNumWaitStates;
unsigned long ulCSRWaitValue;
/* We are compiling to run from ROM (either on-chip or off-chip flash).
Leave the RAM/flash mapped the way they are on reset
(flash @ 0x00000000, RAM @ 0x00300000), and set up the
proper flash wait states (starts out at the maximum number
of wait states on reset, so we should be able to reduce it).
Most of this code will probably get removed by the compiler
if optimization is enabled, since these calculations are
based on constants. But the compiler should still produce
a correct wait state register value. */
nsecsPerClockTick = ( portFLOAT ) 1000000000 / configCPU_CLOCK_HZ;
lNumWaitStates = ( long )( ( configFLASH_SPEED_NSEC / nsecsPerClockTick ) + 0.5 ) - 1;
if( lNumWaitStates < 0 )
{
lNumWaitStates = 0;
}
if( lNumWaitStates > MAX_WAIT_STATES )
{
lNumWaitStates = MAX_WAIT_STATES;
}
ulCSRWaitValue = ululCSRWaitValues[ lNumWaitStates ];
ulCSRWaitValue = WaitState5;
AT91C_BASE_EBI->EBI_CSR[ 0 ] = ulCSRWaitValue | DataBus16 | WaitStateEnable
| PageSize1M | tDF_0cycle
| ByteWriteAccessType | CSEnable
| 0x00000000 /* Base Address */;
}
#else /* else we are compiling to run from on-chip RAM */
{
/* If compiling to run from RAM, we expect the on-chip RAM to already
be mapped at 0x00000000. This is typically done with an initialization
script for the JTAG emulator you are using to download and run the
demo application. So there is nothing to do here in this case. */
}
#endif
/* Disable all interrupts at the AIC level initially... */
AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF;
/* Set all SVR and SMR entries to default values (start with a clean slate)... */
for( lCount = 0; lCount < 32; lCount++ )
{
AT91C_BASE_AIC->AIC_SVR[ lCount ] = (unsigned long) 0;
AT91C_BASE_AIC->AIC_SMR[ lCount ] = AIC_SRCTYPE_INT_EDGE_TRIGGERED;
}
/* Disable clocks to all peripherals initially... */
AT91C_BASE_PS->PS_PCDR = 0xFFFFFFFF;
/* Clear all interrupts at the AIC level initially... */
AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF;
/* Perform 8 "End Of Interrupt" cmds to make sure AIC will not Lock out
nIRQ */
for( lCount = 0; lCount < 8; lCount++ )
{
AT91C_BASE_AIC->AIC_EOICR = 0;
}
/* Initialise LED outputs. */
vParTestInitialise();
}
static void prvSetupHardware( void )
{
/* Set up the ports used by the LED outputs (the name ParTest is now
obsolete - it originally came from "parallel port test"). */
vParTestInitialise();
}
int main( void )
{
#if UC3L
/*! \name Clock frequencies
*/
//! @{
#define EXAMPLE_TARGET_DFLL_FREQ_HZ 96000000 // DFLL target frequency, in Hz
#define EXAMPLE_TARGET_MCUCLK_FREQ_HZ 12000000 // MCU clock target frequency, in Hz
#define EXAMPLE_TARGET_PBACLK_FREQ_HZ 12000000 // PBA clock target frequency, in Hz
//! @}
/*! \name Parameters to pcl_configure_clocks().
*/
//! @{
static scif_gclk_opt_t gc_dfllif_ref_opt = { SCIF_GCCTRL_SLOWCLOCK, 0, false};
static pcl_freq_param_t pcl_dfll_freq_param = {
.main_clk_src = PCL_MC_DFLL0,
.cpu_f = EXAMPLE_TARGET_MCUCLK_FREQ_HZ,
.pba_f = EXAMPLE_TARGET_PBACLK_FREQ_HZ,
.pbb_f = EXAMPLE_TARGET_PBACLK_FREQ_HZ,
.dfll_f = EXAMPLE_TARGET_DFLL_FREQ_HZ,
.pextra_params = &gc_dfllif_ref_opt
};
//! @}
// Note: on the AT32UC3L-EK and UC3-L0-Xplained board, there are no crystal/external
// clock connected to the OSC0 pinout XIN0/XOUT0. We shall then program the DFLL and
// switch the main clock source to the DFLL.
pcl_configure_clocks(&pcl_dfll_freq_param);
// Note: since it is dynamically computing the appropriate field values of the
// configuration registers from the parameters structure, this function is not
// optimal in terms of code size. For a code size optimal solution, it is better
// to create a new function from pcl_configure_clocks_dfll0() and modify it
// to use preprocessor computation from pre-defined target frequencies.
#else
// Configure Osc0 in crystal mode (i.e. use of an external crystal source, with
// frequency FOSC0) with an appropriate startup time then switch the main clock
// source to Osc0.
pcl_switch_to_osc(PCL_OSC0, FOSC0, OSC0_STARTUP);
#endif
portDBG_TRACE("Starting the FreeRTOS AVR32 UC3 Demo...");
/* Setup the LED's for output. */
vParTestInitialise();
/* Start the standard demo tasks. See the WEB documentation for more
information.
Note that the UC3L and UC3B parts do not have enough internal RAM to launch all the tasks of this example.
That's why some of them are commented out using respectively #if (BOARD != UC3L_EK) or #if (BOARD != EVK1101)
compiler directives. */
vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );
vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
#if (BOARD != UC3L_EK)
vStartIntegerMathTasks( tskIDLE_PRIORITY );
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
vStartDynamicPriorityTasks();
#endif
#if (BOARD != EVK1101) && (BOARD != UC3L_EK)
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
vStartMathTasks( tskIDLE_PRIORITY );
#endif
/* Start the demo tasks defined within this file, specifically the check
task as described at the top of this file. */
xTaskCreate(
vErrorChecks
, (const signed portCHAR *)"ErrCheck"
, configMINIMAL_STACK_SIZE
, NULL
, mainCHECK_TASK_PRIORITY
, NULL );
/* Start the scheduler. */
vTaskStartScheduler();
/* Will only get here if there was insufficient memory to create the idle
task. */
return 0;
}
static void prvSetupHardware( void )
{
/* Start with the clocks in their expected state. */
RCC_DeInit();
/* Enable HSE (high speed external clock). */
RCC_HSEConfig( RCC_HSE_ON );
/* Wait till HSE is ready. */
while( RCC_GetFlagStatus( RCC_FLAG_HSERDY ) == RESET )
{
}
/* 2 wait states required on the flash. */
*( ( unsigned portLONG * ) 0x40022000 ) = 0x02;
/* HCLK = SYSCLK */
RCC_HCLKConfig( RCC_SYSCLK_Div1 );
/* PCLK2 = HCLK */
RCC_PCLK2Config( RCC_HCLK_Div1 );
/* PCLK1 = HCLK/2 */
RCC_PCLK1Config( RCC_HCLK_Div2 );
/* PLLCLK = 12MHz * 6 = 72 MHz. */
RCC_PLLConfig( RCC_PLLSource_HSE_Div1, RCC_PLLMul_6 );
/* Enable PLL. */
RCC_PLLCmd( ENABLE );
/* Wait till PLL is ready. */
while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
{
}
/* Select PLL as system clock source. */
RCC_SYSCLKConfig( RCC_SYSCLKSource_PLLCLK );
/* Wait till PLL is used as system clock source. */
while( RCC_GetSYSCLKSource() != 0x08 )
{
}
/* Enable GPIOA, GPIOB, GPIOC, GPIOD, GPIOE and AFIO clocks */
RCC_APB2PeriphClockCmd( RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |RCC_APB2Periph_GPIOC
| RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE | RCC_APB2Periph_AFIO, ENABLE );
/* SPI2 Periph clock enable */
RCC_APB1PeriphClockCmd( RCC_APB1Periph_SPI2, ENABLE );
/* Set the Vector Table base address at 0x08000000 */
NVIC_SetVectorTable( NVIC_VectTab_FLASH, 0x0 );
NVIC_PriorityGroupConfig( NVIC_PriorityGroup_4 );
/* Configure HCLK clock as SysTick clock source. */
SysTick_CLKSourceConfig( SysTick_CLKSource_HCLK );
/* Misc initialisation, including some of the CircleOS features. Note
that CircleOS itself is not used. */
vParTestInitialise();
MEMS_Init();
POINTER_Init();
POINTER_SetMode( POINTER_RESTORE_LESS );
}
static void prvSetupHardware( void )
{
/* Perform any configuration necessary to use the ParTest LED output
functions. */
vParTestInitialise();
}
void prvSetupHardware( void )
{
/*FSL: start LEDs*/
vParTestInitialise();
}
//!
//! \fn main
//! \brief start the software here
//! 1) Initialize the microcontroller and the shared hardware resources
//! of the board.
//! 2) Launch the IP modules.
//! 3) Start FreeRTOS.
//! \return 42, which should never occur.
//! \note
//!
int main( void )
{
volatile avr32_pm_t* pm = &AVR32_PM;
/* 1) Initialize the microcontroller and the shared hardware resources of the board. */
/* Switch to external oscillator 0 */
pm_switch_to_osc0( pm, FOSC0, OSC0_STARTUP );
/* Setup PLL0 on OSC0, mul+1=16 ,divisor by 1, lockcount=16, ie. 12Mhzx16/1 = 192MHz output.
Extra div by 2 => 96MHz */
pm_pll_setup(pm, /* volatile avr32_pm_t* pm */
0, /* unsigned int pll */
15, /* unsigned int mul */
1, /* unsigned int div, Sel Osc0/PLL0 or Osc1/Pll1 */
0, /* unsigned int osc */
16); /* unsigned int lockcount */
pm_pll_set_option( pm, 0, // pll0
0, // Choose the range 160-240MHz.
1, // div2
0 ); // wbwdisable
/* Enable PLL0 */
pm_pll_enable(pm,0);
/* Wait for PLL0 locked */
pm_wait_for_pll0_locked(pm) ;
/* Setup generic clock number 2 on PLL, with OSC0/PLL0, no divisor */
pm_gc_setup(pm,
0,
1, /* Use Osc (=0) or PLL (=1) */
0, /* Sel Osc0/PLL0 or Osc1/Pll1 */
0,
1);
/* Enable Generic clock 0*/
pm_gc_enable(pm, 0);
/* switch to clock */
pm_cksel( pm, 1, 1, 1, 0, 1, 0 );
flashc_set_wait_state( 1 );
pm_switch_to_clock( pm, AVR32_PM_MCCTRL_MCSEL_PLL0 );
/* Setup the LED's for output. */
vParTestInitialise();
/* Start the flash tasks just to provide visual feedback that the demo is
executing. */
vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
/* 2) Start ethernet task. */
vStartEthernetTask( mainETH_TASK_PRIORITY );
/* 3) Start FreeRTOS. */
vTaskStartScheduler();
/* Will only reach here if there was insufficient memory to create the idle task. */
return 0;
}
