static void xgene_sgmac_init(struct xgene_enet_pdata *p) { u32 data, loop = 10; xgene_sgmac_reset(p); /* Enable auto-negotiation */ xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_CONTROL_ADDR >> 2, 0x1000); xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_TBI_CONTROL_ADDR >> 2, 0); while (loop--) { data = xgene_mii_phy_read(p, INT_PHY_ADDR, SGMII_STATUS_ADDR >> 2); if ((data & AUTO_NEG_COMPLETE) && (data & LINK_STATUS)) break; usleep_range(10, 20); } if (!(data & AUTO_NEG_COMPLETE) || !(data & LINK_STATUS)) netdev_err(p->ndev, "Auto-negotiation failed\n"); data = xgene_enet_rd_mac(p, MAC_CONFIG_2_ADDR); ENET_INTERFACE_MODE2_SET(&data, 2); xgene_enet_wr_mac(p, MAC_CONFIG_2_ADDR, data | FULL_DUPLEX2); xgene_enet_wr_mac(p, INTERFACE_CONTROL_ADDR, ENET_GHD_MODE); data = xgene_enet_rd_csr(p, ENET_SPARE_CFG_REG_ADDR); data |= MPA_IDLE_WITH_QMI_EMPTY; xgene_enet_wr_csr(p, ENET_SPARE_CFG_REG_ADDR, data); xgene_sgmac_set_mac_addr(p); data = xgene_enet_rd_csr(p, DEBUG_REG_ADDR); data |= CFG_BYPASS_UNISEC_TX | CFG_BYPASS_UNISEC_RX; xgene_enet_wr_csr(p, DEBUG_REG_ADDR, data); /* Adjust MDC clock frequency */ data = xgene_enet_rd_mac(p, MII_MGMT_CONFIG_ADDR); MGMT_CLOCK_SEL_SET(&data, 7); xgene_enet_wr_mac(p, MII_MGMT_CONFIG_ADDR, data); /* Enable drop if bufpool not available */ data = xgene_enet_rd_csr(p, RSIF_CONFIG_REG_ADDR); data |= CFG_RSIF_FPBUFF_TIMEOUT_EN; xgene_enet_wr_csr(p, RSIF_CONFIG_REG_ADDR, data); /* Rtype should be copied from FP */ xgene_enet_wr_csr(p, RSIF_RAM_DBG_REG0_ADDR, 0); /* Bypass traffic gating */ xgene_enet_wr_csr(p, CFG_LINK_AGGR_RESUME_0_ADDR, TX_PORT0); xgene_enet_wr_csr(p, CFG_BYPASS_ADDR, RESUME_TX); xgene_enet_wr_csr(p, SG_RX_DV_GATE_REG_0_ADDR, RESUME_RX0); }
static void xgene_xgmac_tx_disable(struct xgene_enet_pdata *pdata) { u32 data; xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data); xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data & ~HSTTFEN); }
static void xgene_xgmac_rx_enable(struct xgene_enet_pdata *pdata) { u32 data; xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data); xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data | HSTRFEN); }
static void xgene_xgmac_init(struct xgene_enet_pdata *pdata) { u32 data; xgene_xgmac_reset(pdata); xgene_enet_rd_mac(pdata, AXGMAC_CONFIG_1, &data); data |= HSTPPEN; data &= ~HSTLENCHK; xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data); xgene_xgmac_set_mac_addr(pdata); xgene_xgmac_set_mss(pdata); xgene_enet_rd_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, &data); data |= CFG_RSIF_FPBUFF_TIMEOUT_EN; xgene_enet_wr_csr(pdata, XG_RSIF_CONFIG_REG_ADDR, data); xgene_enet_wr_csr(pdata, XG_CFG_BYPASS_ADDR, RESUME_TX); xgene_enet_wr_csr(pdata, XGENET_RX_DV_GATE_REG_0_ADDR, 0); xgene_enet_rd_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, &data); data |= BIT(12); xgene_enet_wr_csr(pdata, XG_ENET_SPARE_CFG_REG_ADDR, data); xgene_enet_wr_csr(pdata, XG_ENET_SPARE_CFG_REG_1_ADDR, 0x82); }
static void xgene_sgmac_rxtx(struct xgene_enet_pdata *p, u32 bits, bool set) { u32 data; data = xgene_enet_rd_mac(p, MAC_CONFIG_1_ADDR); if (set) data |= bits; else data &= ~bits; xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, data); }
static void xgene_sgmac_set_mac_addr(struct xgene_enet_pdata *p) { u32 addr0, addr1; u8 *dev_addr = p->ndev->dev_addr; addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) | (dev_addr[1] << 8) | dev_addr[0]; xgene_enet_wr_mac(p, STATION_ADDR0_ADDR, addr0); addr1 = xgene_enet_rd_mac(p, STATION_ADDR1_ADDR); addr1 |= (dev_addr[5] << 24) | (dev_addr[4] << 16); xgene_enet_wr_mac(p, STATION_ADDR1_ADDR, addr1); }
static u32 xgene_mii_phy_read(struct xgene_enet_pdata *p, u8 phy_id, u32 reg) { u32 addr, data, done; int i; addr = PHY_ADDR(phy_id) | REG_ADDR(reg); xgene_enet_wr_mac(p, MII_MGMT_ADDRESS_ADDR, addr); xgene_enet_wr_mac(p, MII_MGMT_COMMAND_ADDR, READ_CYCLE_MASK); for (i = 0; i < 10; i++) { done = xgene_enet_rd_mac(p, MII_MGMT_INDICATORS_ADDR); if (!(done & BUSY_MASK)) { data = xgene_enet_rd_mac(p, MII_MGMT_STATUS_ADDR); xgene_enet_wr_mac(p, MII_MGMT_COMMAND_ADDR, 0); return data; } usleep_range(10, 20); } netdev_err(p->ndev, "MII_MGMT read failed\n"); return 0; }
static void xgene_mii_phy_write(struct xgene_enet_pdata *p, u8 phy_id, u32 reg, u16 data) { u32 addr, wr_data, done; int i; addr = PHY_ADDR(phy_id) | REG_ADDR(reg); xgene_enet_wr_mac(p, MII_MGMT_ADDRESS_ADDR, addr); wr_data = PHY_CONTROL(data); xgene_enet_wr_mac(p, MII_MGMT_CONTROL_ADDR, wr_data); for (i = 0; i < 10; i++) { done = xgene_enet_rd_mac(p, MII_MGMT_INDICATORS_ADDR); if (!(done & BUSY_MASK)) return; usleep_range(10, 20); } netdev_err(p->ndev, "MII_MGMT write failed\n"); }
static void xgene_sgmac_init(struct xgene_enet_pdata *p) { u32 data, loop = 10; u32 offset = p->port_id * 4; u32 enet_spare_cfg_reg, rsif_config_reg; u32 cfg_bypass_reg, rx_dv_gate_reg; xgene_sgmac_reset(p); /* Enable auto-negotiation */ xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_CONTROL_ADDR >> 2, 0x1000); xgene_mii_phy_write(p, INT_PHY_ADDR, SGMII_TBI_CONTROL_ADDR >> 2, 0); while (loop--) { data = xgene_mii_phy_read(p, INT_PHY_ADDR, SGMII_STATUS_ADDR >> 2); if ((data & AUTO_NEG_COMPLETE) && (data & LINK_STATUS)) break; usleep_range(1000, 2000); } if (!(data & AUTO_NEG_COMPLETE) || !(data & LINK_STATUS)) netdev_err(p->ndev, "Auto-negotiation failed\n"); data = xgene_enet_rd_mac(p, MAC_CONFIG_2_ADDR); ENET_INTERFACE_MODE2_SET(&data, 2); xgene_enet_wr_mac(p, MAC_CONFIG_2_ADDR, data | FULL_DUPLEX2); xgene_enet_wr_mac(p, INTERFACE_CONTROL_ADDR, ENET_GHD_MODE); if (p->enet_id == XGENE_ENET1) { enet_spare_cfg_reg = ENET_SPARE_CFG_REG_ADDR; rsif_config_reg = RSIF_CONFIG_REG_ADDR; cfg_bypass_reg = CFG_BYPASS_ADDR; rx_dv_gate_reg = SG_RX_DV_GATE_REG_0_ADDR; } else { enet_spare_cfg_reg = XG_ENET_SPARE_CFG_REG_ADDR; rsif_config_reg = XG_RSIF_CONFIG_REG_ADDR; cfg_bypass_reg = XG_CFG_BYPASS_ADDR; rx_dv_gate_reg = XG_MCX_RX_DV_GATE_REG_0_ADDR; } data = xgene_enet_rd_csr(p, enet_spare_cfg_reg); data |= MPA_IDLE_WITH_QMI_EMPTY; xgene_enet_wr_csr(p, enet_spare_cfg_reg, data); xgene_sgmac_set_mac_addr(p); /* Adjust MDC clock frequency */ data = xgene_enet_rd_mac(p, MII_MGMT_CONFIG_ADDR); MGMT_CLOCK_SEL_SET(&data, 7); xgene_enet_wr_mac(p, MII_MGMT_CONFIG_ADDR, data); /* Enable drop if bufpool not available */ data = xgene_enet_rd_csr(p, rsif_config_reg); data |= CFG_RSIF_FPBUFF_TIMEOUT_EN; xgene_enet_wr_csr(p, rsif_config_reg, data); /* Bypass traffic gating */ xgene_enet_wr_csr(p, XG_ENET_SPARE_CFG_REG_1_ADDR, 0x84); xgene_enet_wr_csr(p, cfg_bypass_reg, RESUME_TX); xgene_enet_wr_mcx_csr(p, rx_dv_gate_reg + offset, RESUME_RX0); }