void AArch64AsmPrinter::EmitInstruction(const MachineInstr *MI) {
// Do any auto-generated pseudo lowerings.
if (emitPseudoExpansionLowering(*OutStreamer, MI))
return;
if (AArch64FI->getLOHRelated().count(MI)) {
// Generate a label for LOH related instruction
MCSymbol *LOHLabel = createTempSymbol("loh");
// Associate the instruction with the label
LOHInstToLabel[MI] = LOHLabel;
OutStreamer->EmitLabel(LOHLabel);
}
// Do any manual lowerings.
switch (MI->getOpcode()) {
default:
break;
case AArch64::DBG_VALUE: {
if (isVerbose() && OutStreamer->hasRawTextSupport()) {
SmallString<128> TmpStr;
raw_svector_ostream OS(TmpStr);
PrintDebugValueComment(MI, OS);
OutStreamer->EmitRawText(StringRef(OS.str()));
}
return;
}
// Tail calls use pseudo instructions so they have the proper code-gen
// attributes (isCall, isReturn, etc.). We lower them to the real
// instruction here.
case AArch64::TCRETURNri: {
MCInst TmpInst;
TmpInst.setOpcode(AArch64::BR);
TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
EmitToStreamer(*OutStreamer, TmpInst);
return;
}
case AArch64::TCRETURNdi: {
MCOperand Dest;
MCInstLowering.lowerOperand(MI->getOperand(0), Dest);
MCInst TmpInst;
TmpInst.setOpcode(AArch64::B);
TmpInst.addOperand(Dest);
EmitToStreamer(*OutStreamer, TmpInst);
return;
}
case AArch64::TLSDESC_CALLSEQ: {
/// lower this to:
/// adrp x0, :tlsdesc:var
/// ldr x1, [x0, #:tlsdesc_lo12:var]
/// add x0, x0, #:tlsdesc_lo12:var
/// .tlsdesccall var
/// blr x1
/// (TPIDR_EL0 offset now in x0)
const MachineOperand &MO_Sym = MI->getOperand(0);
MachineOperand MO_TLSDESC_LO12(MO_Sym), MO_TLSDESC(MO_Sym);
MCOperand Sym, SymTLSDescLo12, SymTLSDesc;
MO_TLSDESC_LO12.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGEOFF |
AArch64II::MO_NC);
MO_TLSDESC.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGE);
MCInstLowering.lowerOperand(MO_Sym, Sym);
MCInstLowering.lowerOperand(MO_TLSDESC_LO12, SymTLSDescLo12);
MCInstLowering.lowerOperand(MO_TLSDESC, SymTLSDesc);
MCInst Adrp;
Adrp.setOpcode(AArch64::ADRP);
Adrp.addOperand(MCOperand::createReg(AArch64::X0));
Adrp.addOperand(SymTLSDesc);
EmitToStreamer(*OutStreamer, Adrp);
MCInst Ldr;
Ldr.setOpcode(AArch64::LDRXui);
Ldr.addOperand(MCOperand::createReg(AArch64::X1));
Ldr.addOperand(MCOperand::createReg(AArch64::X0));
Ldr.addOperand(SymTLSDescLo12);
Ldr.addOperand(MCOperand::createImm(0));
EmitToStreamer(*OutStreamer, Ldr);
MCInst Add;
Add.setOpcode(AArch64::ADDXri);
Add.addOperand(MCOperand::createReg(AArch64::X0));
Add.addOperand(MCOperand::createReg(AArch64::X0));
Add.addOperand(SymTLSDescLo12);
Add.addOperand(MCOperand::createImm(AArch64_AM::getShiftValue(0)));
EmitToStreamer(*OutStreamer, Add);
// Emit a relocation-annotation. This expands to no code, but requests
// the following instruction gets an R_AARCH64_TLSDESC_CALL.
MCInst TLSDescCall;
TLSDescCall.setOpcode(AArch64::TLSDESCCALL);
TLSDescCall.addOperand(Sym);
EmitToStreamer(*OutStreamer, TLSDescCall);
MCInst Blr;
Blr.setOpcode(AArch64::BLR);
Blr.addOperand(MCOperand::createReg(AArch64::X1));
EmitToStreamer(*OutStreamer, Blr);
return;
}
case TargetOpcode::STACKMAP:
return LowerSTACKMAP(*OutStreamer, SM, *MI);
case TargetOpcode::PATCHPOINT:
return LowerPATCHPOINT(*OutStreamer, SM, *MI);
}
// Finally, do the automated lowerings for everything else.
MCInst TmpInst;
MCInstLowering.Lower(MI, TmpInst);
EmitToStreamer(*OutStreamer, TmpInst);
}
/// EmitInstruction -- Print out a single PowerPC MI in Darwin syntax to
/// the current output stream.
///
void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
MCInst TmpInst;
// Lower multi-instruction pseudo operations.
switch (MI->getOpcode()) {
default: break;
case TargetOpcode::DBG_VALUE:
llvm_unreachable("Should be handled target independently");
case PPC::MovePCtoLR:
case PPC::MovePCtoLR8: {
// Transform %LR = MovePCtoLR
// Into this, where the label is the PIC base:
// bl L1$pb
// L1$pb:
MCSymbol *PICBase = MF->getPICBaseSymbol();
// Emit the 'bl'.
OutStreamer.EmitInstruction(MCInstBuilder(PPC::BL)
// FIXME: We would like an efficient form for this, so we don't have to do
// a lot of extra uniquing.
.addExpr(MCSymbolRefExpr::Create(PICBase, OutContext)));
// Emit the label.
OutStreamer.EmitLabel(PICBase);
return;
}
case PPC::LDtocJTI:
case PPC::LDtocCPT:
case PPC::LDtoc: {
// Transform %X3 = LDtoc <ga:@min1>, %X2
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());
// Change the opcode to LD, and the global address operand to be a
// reference to the TOC entry we will synthesize later.
TmpInst.setOpcode(PPC::LD);
const MachineOperand &MO = MI->getOperand(1);
// Map symbol -> label of TOC entry
assert(MO.isGlobal() || MO.isCPI() || MO.isJTI());
MCSymbol *MOSymbol = 0;
if (MO.isGlobal())
MOSymbol = getSymbol(MO.getGlobal());
else if (MO.isCPI())
MOSymbol = GetCPISymbol(MO.getIndex());
else if (MO.isJTI())
MOSymbol = GetJTISymbol(MO.getIndex());
MCSymbol *TOCEntry = lookUpOrCreateTOCEntry(MOSymbol);
const MCExpr *Exp =
MCSymbolRefExpr::Create(TOCEntry, MCSymbolRefExpr::VK_PPC_TOC,
OutContext);
TmpInst.getOperand(1) = MCOperand::CreateExpr(Exp);
OutStreamer.EmitInstruction(TmpInst);
return;
}
case PPC::ADDIStocHA: {
// Transform %Xd = ADDIStocHA %X2, <ga:@sym>
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());
// Change the opcode to ADDIS8. If the global address is external,
// has common linkage, is a function address, or is a jump table
// address, then generate a TOC entry and reference that. Otherwise
// reference the symbol directly.
TmpInst.setOpcode(PPC::ADDIS8);
const MachineOperand &MO = MI->getOperand(2);
assert((MO.isGlobal() || MO.isCPI() || MO.isJTI()) &&
"Invalid operand for ADDIStocHA!");
MCSymbol *MOSymbol = 0;
bool IsExternal = false;
bool IsFunction = false;
bool IsCommon = false;
bool IsAvailExt = false;
if (MO.isGlobal()) {
const GlobalValue *GValue = MO.getGlobal();
const GlobalAlias *GAlias = dyn_cast<GlobalAlias>(GValue);
const GlobalValue *RealGValue = GAlias ?
GAlias->resolveAliasedGlobal(false) : GValue;
MOSymbol = getSymbol(RealGValue);
const GlobalVariable *GVar = dyn_cast<GlobalVariable>(RealGValue);
IsExternal = GVar && !GVar->hasInitializer();
IsCommon = GVar && RealGValue->hasCommonLinkage();
IsFunction = !GVar;
IsAvailExt = GVar && RealGValue->hasAvailableExternallyLinkage();
} else if (MO.isCPI())
MOSymbol = GetCPISymbol(MO.getIndex());
else if (MO.isJTI())
MOSymbol = GetJTISymbol(MO.getIndex());
if (IsExternal || IsFunction || IsCommon || IsAvailExt || MO.isJTI() ||
TM.getCodeModel() == CodeModel::Large)
MOSymbol = lookUpOrCreateTOCEntry(MOSymbol);
const MCExpr *Exp =
MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_TOC_HA,
OutContext);
TmpInst.getOperand(2) = MCOperand::CreateExpr(Exp);
OutStreamer.EmitInstruction(TmpInst);
return;
}
case PPC::LDtocL: {
// Transform %Xd = LDtocL <ga:@sym>, %Xs
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());
// Change the opcode to LD. If the global address is external, has
// common linkage, or is a jump table address, then reference the
// associated TOC entry. Otherwise reference the symbol directly.
TmpInst.setOpcode(PPC::LD);
const MachineOperand &MO = MI->getOperand(1);
assert((MO.isGlobal() || MO.isJTI() || MO.isCPI()) &&
"Invalid operand for LDtocL!");
MCSymbol *MOSymbol = 0;
if (MO.isJTI())
MOSymbol = lookUpOrCreateTOCEntry(GetJTISymbol(MO.getIndex()));
else if (MO.isCPI()) {
MOSymbol = GetCPISymbol(MO.getIndex());
if (TM.getCodeModel() == CodeModel::Large)
MOSymbol = lookUpOrCreateTOCEntry(MOSymbol);
}
else if (MO.isGlobal()) {
const GlobalValue *GValue = MO.getGlobal();
const GlobalAlias *GAlias = dyn_cast<GlobalAlias>(GValue);
const GlobalValue *RealGValue = GAlias ?
GAlias->resolveAliasedGlobal(false) : GValue;
MOSymbol = getSymbol(RealGValue);
const GlobalVariable *GVar = dyn_cast<GlobalVariable>(RealGValue);
if (!GVar || !GVar->hasInitializer() || RealGValue->hasCommonLinkage() ||
RealGValue->hasAvailableExternallyLinkage() ||
TM.getCodeModel() == CodeModel::Large)
MOSymbol = lookUpOrCreateTOCEntry(MOSymbol);
}
const MCExpr *Exp =
MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_TOC_LO,
OutContext);
TmpInst.getOperand(1) = MCOperand::CreateExpr(Exp);
OutStreamer.EmitInstruction(TmpInst);
return;
}
case PPC::ADDItocL: {
// Transform %Xd = ADDItocL %Xs, <ga:@sym>
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());
// Change the opcode to ADDI8. If the global address is external, then
// generate a TOC entry and reference that. Otherwise reference the
// symbol directly.
TmpInst.setOpcode(PPC::ADDI8);
const MachineOperand &MO = MI->getOperand(2);
assert((MO.isGlobal() || MO.isCPI()) && "Invalid operand for ADDItocL");
MCSymbol *MOSymbol = 0;
bool IsExternal = false;
bool IsFunction = false;
if (MO.isGlobal()) {
const GlobalValue *GValue = MO.getGlobal();
const GlobalAlias *GAlias = dyn_cast<GlobalAlias>(GValue);
const GlobalValue *RealGValue = GAlias ?
GAlias->resolveAliasedGlobal(false) : GValue;
MOSymbol = getSymbol(RealGValue);
const GlobalVariable *GVar = dyn_cast<GlobalVariable>(RealGValue);
IsExternal = GVar && !GVar->hasInitializer();
IsFunction = !GVar;
} else if (MO.isCPI())
MOSymbol = GetCPISymbol(MO.getIndex());
if (IsFunction || IsExternal || TM.getCodeModel() == CodeModel::Large)
MOSymbol = lookUpOrCreateTOCEntry(MOSymbol);
const MCExpr *Exp =
MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_TOC_LO,
OutContext);
TmpInst.getOperand(2) = MCOperand::CreateExpr(Exp);
OutStreamer.EmitInstruction(TmpInst);
return;
}
case PPC::ADDISgotTprelHA: {
// Transform: %Xd = ADDISgotTprelHA %X2, <ga:@sym>
// Into: %Xd = ADDIS8 %X2, sym@got@tlsgd@ha
assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
const MachineOperand &MO = MI->getOperand(2);
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = getSymbol(GValue);
const MCExpr *SymGotTprel =
MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TPREL_HA,
OutContext);
OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDIS8)
.addReg(MI->getOperand(0).getReg())
.addReg(PPC::X2)
.addExpr(SymGotTprel));
return;
}
case PPC::LDgotTprelL: {
// Transform %Xd = LDgotTprelL <ga:@sym>, %Xs
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());
// Change the opcode to LD.
TmpInst.setOpcode(PPC::LD);
const MachineOperand &MO = MI->getOperand(1);
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = getSymbol(GValue);
const MCExpr *Exp =
MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TPREL_LO,
OutContext);
TmpInst.getOperand(1) = MCOperand::CreateExpr(Exp);
OutStreamer.EmitInstruction(TmpInst);
return;
}
case PPC::ADDIStlsgdHA: {
// Transform: %Xd = ADDIStlsgdHA %X2, <ga:@sym>
// Into: %Xd = ADDIS8 %X2, sym@got@tlsgd@ha
assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
const MachineOperand &MO = MI->getOperand(2);
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = getSymbol(GValue);
const MCExpr *SymGotTlsGD =
MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TLSGD_HA,
OutContext);
OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDIS8)
.addReg(MI->getOperand(0).getReg())
.addReg(PPC::X2)
.addExpr(SymGotTlsGD));
return;
}
case PPC::ADDItlsgdL: {
// Transform: %Xd = ADDItlsgdL %Xs, <ga:@sym>
// Into: %Xd = ADDI8 %Xs, sym@got@tlsgd@l
assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
const MachineOperand &MO = MI->getOperand(2);
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = getSymbol(GValue);
const MCExpr *SymGotTlsGD =
MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TLSGD_LO,
OutContext);
OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDI8)
.addReg(MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg())
.addExpr(SymGotTlsGD));
return;
}
case PPC::GETtlsADDR: {
// Transform: %X3 = GETtlsADDR %X3, <ga:@sym>
// Into: BL8_NOP_TLS __tls_get_addr(sym@tlsgd)
assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
StringRef Name = "__tls_get_addr";
MCSymbol *TlsGetAddr = OutContext.GetOrCreateSymbol(Name);
const MCSymbolRefExpr *TlsRef =
MCSymbolRefExpr::Create(TlsGetAddr, MCSymbolRefExpr::VK_None, OutContext);
const MachineOperand &MO = MI->getOperand(2);
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = getSymbol(GValue);
const MCExpr *SymVar =
MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_TLSGD,
OutContext);
OutStreamer.EmitInstruction(MCInstBuilder(PPC::BL8_NOP_TLS)
.addExpr(TlsRef)
.addExpr(SymVar));
return;
}
case PPC::ADDIStlsldHA: {
// Transform: %Xd = ADDIStlsldHA %X2, <ga:@sym>
// Into: %Xd = ADDIS8 %X2, sym@got@tlsld@ha
assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
const MachineOperand &MO = MI->getOperand(2);
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = getSymbol(GValue);
const MCExpr *SymGotTlsLD =
MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TLSLD_HA,
OutContext);
OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDIS8)
.addReg(MI->getOperand(0).getReg())
.addReg(PPC::X2)
.addExpr(SymGotTlsLD));
return;
}
case PPC::ADDItlsldL: {
// Transform: %Xd = ADDItlsldL %Xs, <ga:@sym>
// Into: %Xd = ADDI8 %Xs, sym@got@tlsld@l
assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
const MachineOperand &MO = MI->getOperand(2);
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = getSymbol(GValue);
const MCExpr *SymGotTlsLD =
MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TLSLD_LO,
OutContext);
OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDI8)
.addReg(MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg())
.addExpr(SymGotTlsLD));
return;
}
case PPC::GETtlsldADDR: {
// Transform: %X3 = GETtlsldADDR %X3, <ga:@sym>
// Into: BL8_NOP_TLS __tls_get_addr(sym@tlsld)
assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
StringRef Name = "__tls_get_addr";
MCSymbol *TlsGetAddr = OutContext.GetOrCreateSymbol(Name);
const MCSymbolRefExpr *TlsRef =
MCSymbolRefExpr::Create(TlsGetAddr, MCSymbolRefExpr::VK_None, OutContext);
const MachineOperand &MO = MI->getOperand(2);
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = getSymbol(GValue);
const MCExpr *SymVar =
MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_TLSLD,
OutContext);
OutStreamer.EmitInstruction(MCInstBuilder(PPC::BL8_NOP_TLS)
.addExpr(TlsRef)
.addExpr(SymVar));
return;
}
case PPC::ADDISdtprelHA: {
// Transform: %Xd = ADDISdtprelHA %X3, <ga:@sym>
// Into: %Xd = ADDIS8 %X3, sym@dtprel@ha
assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
const MachineOperand &MO = MI->getOperand(2);
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = getSymbol(GValue);
const MCExpr *SymDtprel =
MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_DTPREL_HA,
OutContext);
OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDIS8)
.addReg(MI->getOperand(0).getReg())
.addReg(PPC::X3)
.addExpr(SymDtprel));
return;
}
case PPC::ADDIdtprelL: {
// Transform: %Xd = ADDIdtprelL %Xs, <ga:@sym>
// Into: %Xd = ADDI8 %Xs, sym@dtprel@l
assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
const MachineOperand &MO = MI->getOperand(2);
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = getSymbol(GValue);
const MCExpr *SymDtprel =
MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_DTPREL_LO,
OutContext);
OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDI8)
.addReg(MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg())
.addExpr(SymDtprel));
return;
}
case PPC::MFOCRF:
case PPC::MFOCRF8:
if (!Subtarget.hasMFOCRF()) {
// Transform: %R3 = MFOCRF %CR7
// Into: %R3 = MFCR ;; cr7
unsigned NewOpcode =
MI->getOpcode() == PPC::MFOCRF ? PPC::MFCR : PPC::MFCR8;
OutStreamer.AddComment(PPCInstPrinter::
getRegisterName(MI->getOperand(1).getReg()));
OutStreamer.EmitInstruction(MCInstBuilder(NewOpcode)
.addReg(MI->getOperand(0).getReg()));
return;
}
break;
case PPC::MTOCRF:
case PPC::MTOCRF8:
if (!Subtarget.hasMFOCRF()) {
// Transform: %CR7 = MTOCRF %R3
// Into: MTCRF mask, %R3 ;; cr7
unsigned NewOpcode =
MI->getOpcode() == PPC::MTOCRF ? PPC::MTCRF : PPC::MTCRF8;
unsigned Mask = 0x80 >> OutContext.getRegisterInfo()
->getEncodingValue(MI->getOperand(0).getReg());
OutStreamer.AddComment(PPCInstPrinter::
getRegisterName(MI->getOperand(0).getReg()));
OutStreamer.EmitInstruction(MCInstBuilder(NewOpcode)
.addImm(Mask)
.addReg(MI->getOperand(1).getReg()));
return;
}
break;
case PPC::SYNC:
// In Book E sync is called msync, handle this special case here...
if (Subtarget.isBookE()) {
OutStreamer.EmitRawText(StringRef("\tmsync"));
return;
}
break;
case PPC::LD:
case PPC::STD:
case PPC::LWA_32:
case PPC::LWA: {
// Verify alignment is legal, so we don't create relocations
// that can't be supported.
// FIXME: This test is currently disabled for Darwin. The test
// suite shows a handful of test cases that fail this check for
// Darwin. Those need to be investigated before this sanity test
// can be enabled for those subtargets.
if (!Subtarget.isDarwin()) {
unsigned OpNum = (MI->getOpcode() == PPC::STD) ? 2 : 1;
const MachineOperand &MO = MI->getOperand(OpNum);
if (MO.isGlobal() && MO.getGlobal()->getAlignment() < 4)
llvm_unreachable("Global must be word-aligned for LD, STD, LWA!");
}
// Now process the instruction normally.
break;
}
}
MCInst HexagonMCInstrInfo::createBundle() {
MCInst Result;
Result.setOpcode(Hexagon::BUNDLE);
Result.addOperand(MCOperand::createImm(0));
return Result;
}
void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
StringRef Annot) {
unsigned Opcode = MI->getOpcode();
// Check for HINT instructions w/ canonical names.
if (Opcode == ARM::HINT || Opcode == ARM::t2HINT) {
switch (MI->getOperand(0).getImm()) {
case 0: O << "\tnop"; break;
case 1: O << "\tyield"; break;
case 2: O << "\twfe"; break;
case 3: O << "\twfi"; break;
case 4: O << "\tsev"; break;
default:
// Anything else should just print normally.
printInstruction(MI, O);
printAnnotation(O, Annot);
return;
}
printPredicateOperand(MI, 1, O);
if (Opcode == ARM::t2HINT)
O << ".w";
printAnnotation(O, Annot);
return;
}
// Check for MOVs and print canonical forms, instead.
if (Opcode == ARM::MOVsr) {
// FIXME: Thumb variants?
const MCOperand &Dst = MI->getOperand(0);
const MCOperand &MO1 = MI->getOperand(1);
const MCOperand &MO2 = MI->getOperand(2);
const MCOperand &MO3 = MI->getOperand(3);
O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
printSBitModifierOperand(MI, 6, O);
printPredicateOperand(MI, 4, O);
O << '\t';
printRegName(O, Dst.getReg());
O << ", ";
printRegName(O, MO1.getReg());
O << ", ";
printRegName(O, MO2.getReg());
assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
printAnnotation(O, Annot);
return;
}
if (Opcode == ARM::MOVsi) {
// FIXME: Thumb variants?
const MCOperand &Dst = MI->getOperand(0);
const MCOperand &MO1 = MI->getOperand(1);
const MCOperand &MO2 = MI->getOperand(2);
O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
printSBitModifierOperand(MI, 5, O);
printPredicateOperand(MI, 3, O);
O << '\t';
printRegName(O, Dst.getReg());
O << ", ";
printRegName(O, MO1.getReg());
if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
printAnnotation(O, Annot);
return;
}
O << ", "
<< markup("<imm:")
<< "#" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()))
<< markup(">");
printAnnotation(O, Annot);
return;
}
// A8.6.123 PUSH
if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
MI->getOperand(0).getReg() == ARM::SP &&
MI->getNumOperands() > 5) {
// Should only print PUSH if there are at least two registers in the list.
O << '\t' << "push";
printPredicateOperand(MI, 2, O);
if (Opcode == ARM::t2STMDB_UPD)
O << ".w";
O << '\t';
printRegisterList(MI, 4, O);
printAnnotation(O, Annot);
return;
}
if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
MI->getOperand(3).getImm() == -4) {
O << '\t' << "push";
printPredicateOperand(MI, 4, O);
O << "\t{";
printRegName(O, MI->getOperand(1).getReg());
O << "}";
printAnnotation(O, Annot);
return;
}
// A8.6.122 POP
if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
MI->getOperand(0).getReg() == ARM::SP &&
MI->getNumOperands() > 5) {
// Should only print POP if there are at least two registers in the list.
O << '\t' << "pop";
printPredicateOperand(MI, 2, O);
if (Opcode == ARM::t2LDMIA_UPD)
O << ".w";
O << '\t';
printRegisterList(MI, 4, O);
printAnnotation(O, Annot);
return;
}
if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
MI->getOperand(4).getImm() == 4) {
O << '\t' << "pop";
printPredicateOperand(MI, 5, O);
O << "\t{";
printRegName(O, MI->getOperand(0).getReg());
O << "}";
printAnnotation(O, Annot);
return;
}
// A8.6.355 VPUSH
if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) &&
MI->getOperand(0).getReg() == ARM::SP) {
O << '\t' << "vpush";
printPredicateOperand(MI, 2, O);
O << '\t';
printRegisterList(MI, 4, O);
printAnnotation(O, Annot);
return;
}
// A8.6.354 VPOP
if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) &&
MI->getOperand(0).getReg() == ARM::SP) {
O << '\t' << "vpop";
printPredicateOperand(MI, 2, O);
O << '\t';
printRegisterList(MI, 4, O);
printAnnotation(O, Annot);
return;
}
if (Opcode == ARM::tLDMIA) {
bool Writeback = true;
unsigned BaseReg = MI->getOperand(0).getReg();
for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
if (MI->getOperand(i).getReg() == BaseReg)
Writeback = false;
}
O << "\tldm";
printPredicateOperand(MI, 1, O);
O << '\t';
printRegName(O, BaseReg);
if (Writeback) O << "!";
O << ", ";
printRegisterList(MI, 3, O);
printAnnotation(O, Annot);
return;
}
// Thumb1 NOP
if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 &&
MI->getOperand(1).getReg() == ARM::R8) {
O << "\tnop";
printPredicateOperand(MI, 2, O);
printAnnotation(O, Annot);
return;
}
// Combine 2 GPRs from disassember into a GPRPair to match with instr def.
// ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
// a single GPRPair reg operand is used in the .td file to replace the two
// GPRs. However, when decoding them, the two GRPs cannot be automatically
// expressed as a GPRPair, so we have to manually merge them.
// FIXME: We would really like to be able to tablegen'erate this.
if (Opcode == ARM::LDREXD || Opcode == ARM::STREXD) {
const MCRegisterClass& MRC = MRI.getRegClass(ARM::GPRRegClassID);
bool isStore = Opcode == ARM::STREXD;
unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
if (MRC.contains(Reg)) {
MCInst NewMI;
MCOperand NewReg;
NewMI.setOpcode(Opcode);
if (isStore)
NewMI.addOperand(MI->getOperand(0));
NewReg = MCOperand::CreateReg(MRI.getMatchingSuperReg(Reg, ARM::gsub_0,
&MRI.getRegClass(ARM::GPRPairRegClassID)));
NewMI.addOperand(NewReg);
// Copy the rest operands into NewMI.
for(unsigned i= isStore ? 3 : 2; i < MI->getNumOperands(); ++i)
NewMI.addOperand(MI->getOperand(i));
printInstruction(&NewMI, O);
return;
}
}
printInstruction(MI, O);
printAnnotation(O, Annot);
}
void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
OutMI.setOpcode(MI->getOpcode());
for (const MachineOperand &MO : MI->operands())
if (auto MaybeMCOp = LowerMachineOperand(MI, MO))
OutMI.addOperand(MaybeMCOp.getValue());
// Handle a few special cases to eliminate operand modifiers.
ReSimplify:
switch (OutMI.getOpcode()) {
case X86::LEA64_32r:
case X86::LEA64r:
case X86::LEA16r:
case X86::LEA32r:
// LEA should have a segment register, but it must be empty.
assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
"Unexpected # of LEA operands");
assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
"LEA has segment specified!");
break;
case X86::MOV32ri64:
OutMI.setOpcode(X86::MOV32ri);
break;
// Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
// if one of the registers is extended, but other isn't.
case X86::VMOVAPDrr:
case X86::VMOVAPDYrr:
case X86::VMOVAPSrr:
case X86::VMOVAPSYrr:
case X86::VMOVDQArr:
case X86::VMOVDQAYrr:
case X86::VMOVDQUrr:
case X86::VMOVDQUYrr:
case X86::VMOVUPDrr:
case X86::VMOVUPDYrr:
case X86::VMOVUPSrr:
case X86::VMOVUPSYrr: {
if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) {
unsigned NewOpc;
switch (OutMI.getOpcode()) {
default: llvm_unreachable("Invalid opcode");
case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
}
OutMI.setOpcode(NewOpc);
}
break;
}
case X86::VMOVSDrr:
case X86::VMOVSSrr: {
if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) {
unsigned NewOpc;
switch (OutMI.getOpcode()) {
default: llvm_unreachable("Invalid opcode");
case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
}
OutMI.setOpcode(NewOpc);
}
break;
}
// TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
// inputs modeled as normal uses instead of implicit uses. As such, truncate
// off all but the first operand (the callee). FIXME: Change isel.
case X86::TAILJMPr64:
case X86::TAILJMPr64_REX:
case X86::CALL64r:
case X86::CALL64pcrel32: {
unsigned Opcode = OutMI.getOpcode();
MCOperand Saved = OutMI.getOperand(0);
OutMI = MCInst();
OutMI.setOpcode(Opcode);
OutMI.addOperand(Saved);
break;
}
case X86::EH_RETURN:
case X86::EH_RETURN64: {
OutMI = MCInst();
OutMI.setOpcode(getRetOpcode(AsmPrinter.getSubtarget()));
break;
}
// TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
case X86::TAILJMPr:
case X86::TAILJMPd:
case X86::TAILJMPd64: {
unsigned Opcode;
switch (OutMI.getOpcode()) {
default: llvm_unreachable("Invalid opcode");
case X86::TAILJMPr: Opcode = X86::JMP32r; break;
case X86::TAILJMPd:
case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
}
MCOperand Saved = OutMI.getOperand(0);
OutMI = MCInst();
OutMI.setOpcode(Opcode);
OutMI.addOperand(Saved);
break;
}
case X86::DEC16r:
case X86::DEC32r:
case X86::INC16r:
case X86::INC32r:
// If we aren't in 64-bit mode we can use the 1-byte inc/dec instructions.
if (!AsmPrinter.getSubtarget().is64Bit()) {
unsigned Opcode;
switch (OutMI.getOpcode()) {
default: llvm_unreachable("Invalid opcode");
case X86::DEC16r: Opcode = X86::DEC16r_alt; break;
case X86::DEC32r: Opcode = X86::DEC32r_alt; break;
case X86::INC16r: Opcode = X86::INC16r_alt; break;
case X86::INC32r: Opcode = X86::INC32r_alt; break;
}
OutMI.setOpcode(Opcode);
}
break;
// These are pseudo-ops for OR to help with the OR->ADD transformation. We do
// this with an ugly goto in case the resultant OR uses EAX and needs the
// short form.
case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
// Atomic load and store require a separate pseudo-inst because Acquire
// implies mayStore and Release implies mayLoad; fix these to regular MOV
// instructions here
case X86::ACQUIRE_MOV8rm: OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
case X86::RELEASE_MOV8mr: OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
case X86::RELEASE_MOV8mi: OutMI.setOpcode(X86::MOV8mi); goto ReSimplify;
case X86::RELEASE_MOV16mi: OutMI.setOpcode(X86::MOV16mi); goto ReSimplify;
case X86::RELEASE_MOV32mi: OutMI.setOpcode(X86::MOV32mi); goto ReSimplify;
case X86::RELEASE_MOV64mi32: OutMI.setOpcode(X86::MOV64mi32); goto ReSimplify;
case X86::RELEASE_ADD8mi: OutMI.setOpcode(X86::ADD8mi); goto ReSimplify;
case X86::RELEASE_ADD32mi: OutMI.setOpcode(X86::ADD32mi); goto ReSimplify;
case X86::RELEASE_ADD64mi32: OutMI.setOpcode(X86::ADD64mi32); goto ReSimplify;
case X86::RELEASE_AND8mi: OutMI.setOpcode(X86::AND8mi); goto ReSimplify;
case X86::RELEASE_AND32mi: OutMI.setOpcode(X86::AND32mi); goto ReSimplify;
case X86::RELEASE_AND64mi32: OutMI.setOpcode(X86::AND64mi32); goto ReSimplify;
case X86::RELEASE_OR8mi: OutMI.setOpcode(X86::OR8mi); goto ReSimplify;
case X86::RELEASE_OR32mi: OutMI.setOpcode(X86::OR32mi); goto ReSimplify;
case X86::RELEASE_OR64mi32: OutMI.setOpcode(X86::OR64mi32); goto ReSimplify;
case X86::RELEASE_XOR8mi: OutMI.setOpcode(X86::XOR8mi); goto ReSimplify;
case X86::RELEASE_XOR32mi: OutMI.setOpcode(X86::XOR32mi); goto ReSimplify;
case X86::RELEASE_XOR64mi32: OutMI.setOpcode(X86::XOR64mi32); goto ReSimplify;
case X86::RELEASE_INC8m: OutMI.setOpcode(X86::INC8m); goto ReSimplify;
case X86::RELEASE_INC16m: OutMI.setOpcode(X86::INC16m); goto ReSimplify;
case X86::RELEASE_INC32m: OutMI.setOpcode(X86::INC32m); goto ReSimplify;
case X86::RELEASE_INC64m: OutMI.setOpcode(X86::INC64m); goto ReSimplify;
case X86::RELEASE_DEC8m: OutMI.setOpcode(X86::DEC8m); goto ReSimplify;
case X86::RELEASE_DEC16m: OutMI.setOpcode(X86::DEC16m); goto ReSimplify;
case X86::RELEASE_DEC32m: OutMI.setOpcode(X86::DEC32m); goto ReSimplify;
case X86::RELEASE_DEC64m: OutMI.setOpcode(X86::DEC64m); goto ReSimplify;
// We don't currently select the correct instruction form for instructions
// which have a short %eax, etc. form. Handle this by custom lowering, for
// now.
//
// Note, we are currently not handling the following instructions:
// MOV64ao8, MOV64o8a
// XCHG16ar, XCHG32ar, XCHG64ar
case X86::MOV8mr_NOREX:
case X86::MOV8mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o32a); break;
case X86::MOV8rm_NOREX:
case X86::MOV8rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao32); break;
case X86::MOV16mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o32a); break;
case X86::MOV16rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao32); break;
case X86::MOV32mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
case X86::MOV32rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
case X86::ADC8ri: SimplifyShortImmForm(OutMI, X86::ADC8i8); break;
case X86::ADC16ri: SimplifyShortImmForm(OutMI, X86::ADC16i16); break;
case X86::ADC32ri: SimplifyShortImmForm(OutMI, X86::ADC32i32); break;
case X86::ADC64ri32: SimplifyShortImmForm(OutMI, X86::ADC64i32); break;
case X86::ADD8ri: SimplifyShortImmForm(OutMI, X86::ADD8i8); break;
case X86::ADD16ri: SimplifyShortImmForm(OutMI, X86::ADD16i16); break;
case X86::ADD32ri: SimplifyShortImmForm(OutMI, X86::ADD32i32); break;
case X86::ADD64ri32: SimplifyShortImmForm(OutMI, X86::ADD64i32); break;
case X86::AND8ri: SimplifyShortImmForm(OutMI, X86::AND8i8); break;
case X86::AND16ri: SimplifyShortImmForm(OutMI, X86::AND16i16); break;
case X86::AND32ri: SimplifyShortImmForm(OutMI, X86::AND32i32); break;
case X86::AND64ri32: SimplifyShortImmForm(OutMI, X86::AND64i32); break;
case X86::CMP8ri: SimplifyShortImmForm(OutMI, X86::CMP8i8); break;
case X86::CMP16ri: SimplifyShortImmForm(OutMI, X86::CMP16i16); break;
case X86::CMP32ri: SimplifyShortImmForm(OutMI, X86::CMP32i32); break;
case X86::CMP64ri32: SimplifyShortImmForm(OutMI, X86::CMP64i32); break;
case X86::OR8ri: SimplifyShortImmForm(OutMI, X86::OR8i8); break;
case X86::OR16ri: SimplifyShortImmForm(OutMI, X86::OR16i16); break;
case X86::OR32ri: SimplifyShortImmForm(OutMI, X86::OR32i32); break;
case X86::OR64ri32: SimplifyShortImmForm(OutMI, X86::OR64i32); break;
case X86::SBB8ri: SimplifyShortImmForm(OutMI, X86::SBB8i8); break;
case X86::SBB16ri: SimplifyShortImmForm(OutMI, X86::SBB16i16); break;
case X86::SBB32ri: SimplifyShortImmForm(OutMI, X86::SBB32i32); break;
case X86::SBB64ri32: SimplifyShortImmForm(OutMI, X86::SBB64i32); break;
case X86::SUB8ri: SimplifyShortImmForm(OutMI, X86::SUB8i8); break;
case X86::SUB16ri: SimplifyShortImmForm(OutMI, X86::SUB16i16); break;
case X86::SUB32ri: SimplifyShortImmForm(OutMI, X86::SUB32i32); break;
case X86::SUB64ri32: SimplifyShortImmForm(OutMI, X86::SUB64i32); break;
case X86::TEST8ri: SimplifyShortImmForm(OutMI, X86::TEST8i8); break;
case X86::TEST16ri: SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
case X86::TEST32ri: SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
case X86::XOR8ri: SimplifyShortImmForm(OutMI, X86::XOR8i8); break;
case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break;
case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break;
case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break;
// Try to shrink some forms of movsx.
case X86::MOVSX16rr8:
case X86::MOVSX32rr16:
case X86::MOVSX64rr32:
SimplifyMOVSX(OutMI);
break;
}
}
/// EmitInstruction -- Print out a single PowerPC MI in Darwin syntax to
/// the current output stream.
///
void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
MCInst TmpInst;
// Lower multi-instruction pseudo operations.
switch (MI->getOpcode()) {
default: break;
case TargetOpcode::DBG_VALUE: {
if (!isVerbose() || !OutStreamer.hasRawTextSupport()) return;
SmallString<32> Str;
raw_svector_ostream O(Str);
unsigned NOps = MI->getNumOperands();
assert(NOps==4);
O << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
// cast away const; DIetc do not take const operands for some reason.
DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
O << V.getName();
O << " <- ";
// Frame address. Currently handles register +- offset only.
assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
O << '['; printOperand(MI, 0, O); O << '+'; printOperand(MI, 1, O);
O << ']';
O << "+";
printOperand(MI, NOps-2, O);
OutStreamer.EmitRawText(O.str());
return;
}
case PPC::MovePCtoLR:
case PPC::MovePCtoLR8: {
// Transform %LR = MovePCtoLR
// Into this, where the label is the PIC base:
// bl L1$pb
// L1$pb:
MCSymbol *PICBase = MF->getPICBaseSymbol();
// Emit the 'bl'.
OutStreamer.EmitInstruction(MCInstBuilder(PPC::BL_Darwin) // Darwin vs SVR4 doesn't matter here.
// FIXME: We would like an efficient form for this, so we don't have to do
// a lot of extra uniquing.
.addExpr(MCSymbolRefExpr::Create(PICBase, OutContext)));
// Emit the label.
OutStreamer.EmitLabel(PICBase);
return;
}
case PPC::LDtocJTI:
case PPC::LDtocCPT:
case PPC::LDtoc: {
// Transform %X3 = LDtoc <ga:@min1>, %X2
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());
// Change the opcode to LD, and the global address operand to be a
// reference to the TOC entry we will synthesize later.
TmpInst.setOpcode(PPC::LD);
const MachineOperand &MO = MI->getOperand(1);
// Map symbol -> label of TOC entry
assert(MO.isGlobal() || MO.isCPI() || MO.isJTI());
MCSymbol *MOSymbol = 0;
if (MO.isGlobal())
MOSymbol = Mang->getSymbol(MO.getGlobal());
else if (MO.isCPI())
MOSymbol = GetCPISymbol(MO.getIndex());
else if (MO.isJTI())
MOSymbol = GetJTISymbol(MO.getIndex());
MCSymbol *TOCEntry = lookUpOrCreateTOCEntry(MOSymbol);
const MCExpr *Exp =
MCSymbolRefExpr::Create(TOCEntry, MCSymbolRefExpr::VK_PPC_TOC_ENTRY,
OutContext);
TmpInst.getOperand(1) = MCOperand::CreateExpr(Exp);
OutStreamer.EmitInstruction(TmpInst);
return;
}
case PPC::ADDIStocHA: {
// Transform %Xd = ADDIStocHA %X2, <ga:@sym>
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());
// Change the opcode to ADDIS8. If the global address is external,
// has common linkage, is a function address, or is a jump table
// address, then generate a TOC entry and reference that. Otherwise
// reference the symbol directly.
TmpInst.setOpcode(PPC::ADDIS8);
const MachineOperand &MO = MI->getOperand(2);
assert((MO.isGlobal() || MO.isCPI() || MO.isJTI()) &&
"Invalid operand for ADDIStocHA!");
MCSymbol *MOSymbol = 0;
bool IsExternal = false;
bool IsFunction = false;
bool IsCommon = false;
if (MO.isGlobal()) {
const GlobalValue *GValue = MO.getGlobal();
MOSymbol = Mang->getSymbol(GValue);
const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GValue);
IsExternal = GVar && !GVar->hasInitializer();
IsCommon = GVar && GValue->hasCommonLinkage();
IsFunction = !GVar;
} else if (MO.isCPI())
MOSymbol = GetCPISymbol(MO.getIndex());
else if (MO.isJTI())
MOSymbol = GetJTISymbol(MO.getIndex());
if (IsExternal || IsFunction || IsCommon || MO.isJTI())
MOSymbol = lookUpOrCreateTOCEntry(MOSymbol);
const MCExpr *Exp =
MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_TOC16_HA,
OutContext);
TmpInst.getOperand(2) = MCOperand::CreateExpr(Exp);
OutStreamer.EmitInstruction(TmpInst);
return;
}
case PPC::LDtocL: {
// Transform %Xd = LDtocL <ga:@sym>, %Xs
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());
// Change the opcode to LDrs, which is a form of LD with the offset
// specified by a SymbolLo. If the global address is external, has
// common linkage, or is a jump table address, then reference the
// associated TOC entry. Otherwise reference the symbol directly.
TmpInst.setOpcode(PPC::LDrs);
const MachineOperand &MO = MI->getOperand(1);
assert((MO.isGlobal() || MO.isJTI()) && "Invalid operand for LDtocL!");
MCSymbol *MOSymbol = 0;
if (MO.isJTI())
MOSymbol = lookUpOrCreateTOCEntry(GetJTISymbol(MO.getIndex()));
else {
const GlobalValue *GValue = MO.getGlobal();
MOSymbol = Mang->getSymbol(GValue);
const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GValue);
if (!GVar || !GVar->hasInitializer() || GValue->hasCommonLinkage())
MOSymbol = lookUpOrCreateTOCEntry(MOSymbol);
}
const MCExpr *Exp =
MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_TOC16_LO,
OutContext);
TmpInst.getOperand(1) = MCOperand::CreateExpr(Exp);
OutStreamer.EmitInstruction(TmpInst);
return;
}
case PPC::ADDItocL: {
// Transform %Xd = ADDItocL %Xs, <ga:@sym>
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());
// Change the opcode to ADDI8L. If the global address is external, then
// generate a TOC entry and reference that. Otherwise reference the
// symbol directly.
TmpInst.setOpcode(PPC::ADDI8L);
const MachineOperand &MO = MI->getOperand(2);
assert((MO.isGlobal() || MO.isCPI()) && "Invalid operand for ADDItocL");
MCSymbol *MOSymbol = 0;
bool IsExternal = false;
bool IsFunction = false;
if (MO.isGlobal()) {
const GlobalValue *GValue = MO.getGlobal();
MOSymbol = Mang->getSymbol(GValue);
const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GValue);
IsExternal = GVar && !GVar->hasInitializer();
IsFunction = !GVar;
} else if (MO.isCPI())
MOSymbol = GetCPISymbol(MO.getIndex());
if (IsFunction || IsExternal)
MOSymbol = lookUpOrCreateTOCEntry(MOSymbol);
const MCExpr *Exp =
MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_TOC16_LO,
OutContext);
TmpInst.getOperand(2) = MCOperand::CreateExpr(Exp);
OutStreamer.EmitInstruction(TmpInst);
return;
}
case PPC::ADDISgotTprelHA: {
// Transform: %Xd = ADDISgotTprelHA %X2, <ga:@sym>
// Into: %Xd = ADDIS8 %X2, sym@got@tlsgd@ha
assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
const MachineOperand &MO = MI->getOperand(2);
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = Mang->getSymbol(GValue);
const MCExpr *SymGotTprel =
MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TPREL16_HA,
OutContext);
OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDIS8)
.addReg(MI->getOperand(0).getReg())
.addReg(PPC::X2)
.addExpr(SymGotTprel));
return;
}
case PPC::LDgotTprelL: {
// Transform %Xd = LDgotTprelL <ga:@sym>, %Xs
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());
// Change the opcode to LDrs, which is a form of LD with the offset
// specified by a SymbolLo.
TmpInst.setOpcode(PPC::LDrs);
const MachineOperand &MO = MI->getOperand(1);
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = Mang->getSymbol(GValue);
const MCExpr *Exp =
MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TPREL16_LO,
OutContext);
TmpInst.getOperand(1) = MCOperand::CreateExpr(Exp);
OutStreamer.EmitInstruction(TmpInst);
return;
}
case PPC::ADDIStlsgdHA: {
// Transform: %Xd = ADDIStlsgdHA %X2, <ga:@sym>
// Into: %Xd = ADDIS8 %X2, sym@got@tlsgd@ha
assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
const MachineOperand &MO = MI->getOperand(2);
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = Mang->getSymbol(GValue);
const MCExpr *SymGotTlsGD =
MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TLSGD16_HA,
OutContext);
OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDIS8)
.addReg(MI->getOperand(0).getReg())
.addReg(PPC::X2)
.addExpr(SymGotTlsGD));
return;
}
case PPC::ADDItlsgdL: {
// Transform: %Xd = ADDItlsgdL %Xs, <ga:@sym>
// Into: %Xd = ADDI8L %Xs, sym@got@tlsgd@l
assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
const MachineOperand &MO = MI->getOperand(2);
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = Mang->getSymbol(GValue);
const MCExpr *SymGotTlsGD =
MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TLSGD16_LO,
OutContext);
OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDI8L)
.addReg(MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg())
.addExpr(SymGotTlsGD));
return;
}
case PPC::GETtlsADDR: {
// Transform: %X3 = GETtlsADDR %X3, <ga:@sym>
// Into: BL8_NOP_ELF_TLSGD __tls_get_addr(sym@tlsgd)
assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
StringRef Name = "__tls_get_addr";
MCSymbol *TlsGetAddr = OutContext.GetOrCreateSymbol(Name);
const MCSymbolRefExpr *TlsRef =
MCSymbolRefExpr::Create(TlsGetAddr, MCSymbolRefExpr::VK_None, OutContext);
const MachineOperand &MO = MI->getOperand(2);
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = Mang->getSymbol(GValue);
const MCExpr *SymVar =
MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_TLSGD,
OutContext);
OutStreamer.EmitInstruction(MCInstBuilder(PPC::BL8_NOP_ELF_TLSGD)
.addExpr(TlsRef)
.addExpr(SymVar));
return;
}
case PPC::ADDIStlsldHA: {
// Transform: %Xd = ADDIStlsldHA %X2, <ga:@sym>
// Into: %Xd = ADDIS8 %X2, sym@got@tlsld@ha
assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
const MachineOperand &MO = MI->getOperand(2);
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = Mang->getSymbol(GValue);
const MCExpr *SymGotTlsLD =
MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TLSLD16_HA,
OutContext);
OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDIS8)
.addReg(MI->getOperand(0).getReg())
.addReg(PPC::X2)
.addExpr(SymGotTlsLD));
return;
}
case PPC::ADDItlsldL: {
// Transform: %Xd = ADDItlsldL %Xs, <ga:@sym>
// Into: %Xd = ADDI8L %Xs, sym@got@tlsld@l
assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
const MachineOperand &MO = MI->getOperand(2);
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = Mang->getSymbol(GValue);
const MCExpr *SymGotTlsLD =
MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_GOT_TLSLD16_LO,
OutContext);
OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDI8L)
.addReg(MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg())
.addExpr(SymGotTlsLD));
return;
}
case PPC::GETtlsldADDR: {
// Transform: %X3 = GETtlsldADDR %X3, <ga:@sym>
// Into: BL8_NOP_ELF_TLSLD __tls_get_addr(sym@tlsld)
assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
StringRef Name = "__tls_get_addr";
MCSymbol *TlsGetAddr = OutContext.GetOrCreateSymbol(Name);
const MCSymbolRefExpr *TlsRef =
MCSymbolRefExpr::Create(TlsGetAddr, MCSymbolRefExpr::VK_None, OutContext);
const MachineOperand &MO = MI->getOperand(2);
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = Mang->getSymbol(GValue);
const MCExpr *SymVar =
MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_TLSLD,
OutContext);
OutStreamer.EmitInstruction(MCInstBuilder(PPC::BL8_NOP_ELF_TLSLD)
.addExpr(TlsRef)
.addExpr(SymVar));
return;
}
case PPC::ADDISdtprelHA: {
// Transform: %Xd = ADDISdtprelHA %X3, <ga:@sym>
// Into: %Xd = ADDIS8 %X3, sym@dtprel@ha
assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
const MachineOperand &MO = MI->getOperand(2);
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = Mang->getSymbol(GValue);
const MCExpr *SymDtprel =
MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_DTPREL16_HA,
OutContext);
OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDIS8)
.addReg(MI->getOperand(0).getReg())
.addReg(PPC::X3)
.addExpr(SymDtprel));
return;
}
case PPC::ADDIdtprelL: {
// Transform: %Xd = ADDIdtprelL %Xs, <ga:@sym>
// Into: %Xd = ADDI8L %Xs, sym@dtprel@l
assert(Subtarget.isPPC64() && "Not supported for 32-bit PowerPC");
const MachineOperand &MO = MI->getOperand(2);
const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = Mang->getSymbol(GValue);
const MCExpr *SymDtprel =
MCSymbolRefExpr::Create(MOSymbol, MCSymbolRefExpr::VK_PPC_DTPREL16_LO,
OutContext);
OutStreamer.EmitInstruction(MCInstBuilder(PPC::ADDI8L)
.addReg(MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg())
.addExpr(SymDtprel));
return;
}
case PPC::MFCRpseud:
case PPC::MFCR8pseud:
// Transform: %R3 = MFCRpseud %CR7
// Into: %R3 = MFCR ;; cr7
OutStreamer.AddComment(PPCInstPrinter::
getRegisterName(MI->getOperand(1).getReg()));
OutStreamer.EmitInstruction(MCInstBuilder(Subtarget.isPPC64() ? PPC::MFCR8 : PPC::MFCR)
.addReg(MI->getOperand(0).getReg()));
return;
case PPC::SYNC:
// In Book E sync is called msync, handle this special case here...
if (Subtarget.isBookE()) {
OutStreamer.EmitRawText(StringRef("\tmsync"));
return;
}
}
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());
OutStreamer.EmitInstruction(TmpInst);
}
static DecodeStatus
DecodeL2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
// Try and decode as a L3R / L2RUS instruction.
unsigned Opcode = fieldFromInstruction(Insn, 16, 4) |
fieldFromInstruction(Insn, 27, 5) << 4;
switch (Opcode) {
case 0x0c:
Inst.setOpcode(XCore::STW_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x1c:
Inst.setOpcode(XCore::XOR_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x2c:
Inst.setOpcode(XCore::ASHR_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x3c:
Inst.setOpcode(XCore::LDAWF_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x4c:
Inst.setOpcode(XCore::LDAWB_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x5c:
Inst.setOpcode(XCore::LDA16F_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x6c:
Inst.setOpcode(XCore::LDA16B_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x7c:
Inst.setOpcode(XCore::MUL_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x8c:
Inst.setOpcode(XCore::DIVS_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x9c:
Inst.setOpcode(XCore::DIVU_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x10c:
Inst.setOpcode(XCore::ST16_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x11c:
Inst.setOpcode(XCore::ST8_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x12c:
Inst.setOpcode(XCore::ASHR_l2rus);
return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
case 0x12d:
Inst.setOpcode(XCore::OUTPW_l2rus);
return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
case 0x12e:
Inst.setOpcode(XCore::INPW_l2rus);
return DecodeL2RUSBitpInstruction(Inst, Insn, Address, Decoder);
case 0x13c:
Inst.setOpcode(XCore::LDAWF_l2rus);
return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
case 0x14c:
Inst.setOpcode(XCore::LDAWB_l2rus);
return DecodeL2RUSInstruction(Inst, Insn, Address, Decoder);
case 0x15c:
Inst.setOpcode(XCore::CRC_l3r);
return DecodeL3RSrcDstInstruction(Inst, Insn, Address, Decoder);
case 0x18c:
Inst.setOpcode(XCore::REMS_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
case 0x19c:
Inst.setOpcode(XCore::REMU_l3r);
return DecodeL3RInstruction(Inst, Insn, Address, Decoder);
}
return MCDisassembler::Fail;
}
bool MBlazeDisassembler::getInstruction(MCInst &instr,
uint64_t &size,
const MemoryObject ®ion,
uint64_t address,
raw_ostream &vStream) const {
// The machine instruction.
uint32_t insn;
uint8_t bytes[4];
// We always consume 4 bytes of data
size = 4;
// We want to read exactly 4 bytes of data.
if (region.readBytes(address, 4, (uint8_t*)bytes, NULL) == -1)
return false;
// Encoded as a big-endian 32-bit word in the stream.
insn = (bytes[0]<<24) | (bytes[1]<<16) | (bytes[2]<< 8) | (bytes[3]<<0);
// Get the MCInst opcode from the binary instruction and make sure
// that it is a valid instruction.
unsigned opcode = getOPCODE(insn);
if (opcode == UNSUPPORTED)
return false;
instr.setOpcode(opcode);
uint64_t tsFlags = MBlazeInsts[opcode].TSFlags;
switch ((tsFlags & MBlazeII::FormMask)) {
default:
llvm_unreachable("unknown instruction encoding");
case MBlazeII::FRRRR:
instr.addOperand(MCOperand::CreateReg(getRD(insn)));
instr.addOperand(MCOperand::CreateReg(getRB(insn)));
instr.addOperand(MCOperand::CreateReg(getRA(insn)));
break;
case MBlazeII::FRRR:
instr.addOperand(MCOperand::CreateReg(getRD(insn)));
instr.addOperand(MCOperand::CreateReg(getRA(insn)));
instr.addOperand(MCOperand::CreateReg(getRB(insn)));
break;
case MBlazeII::FRI:
switch (opcode) {
default:
llvm_unreachable("unknown instruction encoding");
case MBlaze::MFS:
instr.addOperand(MCOperand::CreateReg(getRD(insn)));
instr.addOperand(MCOperand::CreateImm(insn&0x3FFF));
break;
case MBlaze::MTS:
instr.addOperand(MCOperand::CreateImm(insn&0x3FFF));
instr.addOperand(MCOperand::CreateReg(getRA(insn)));
break;
case MBlaze::MSRSET:
case MBlaze::MSRCLR:
instr.addOperand(MCOperand::CreateReg(getRD(insn)));
instr.addOperand(MCOperand::CreateImm(insn&0x7FFF));
break;
}
break;
case MBlazeII::FRRI:
instr.addOperand(MCOperand::CreateReg(getRD(insn)));
instr.addOperand(MCOperand::CreateReg(getRA(insn)));
switch (opcode) {
default:
instr.addOperand(MCOperand::CreateImm(getIMM(insn)));
break;
case MBlaze::BSRLI:
case MBlaze::BSRAI:
case MBlaze::BSLLI:
instr.addOperand(MCOperand::CreateImm(insn&0x1F));
break;
}
break;
case MBlazeII::FCRR:
instr.addOperand(MCOperand::CreateReg(getRA(insn)));
instr.addOperand(MCOperand::CreateReg(getRB(insn)));
break;
case MBlazeII::FCRI:
instr.addOperand(MCOperand::CreateReg(getRA(insn)));
instr.addOperand(MCOperand::CreateImm(getIMM(insn)));
break;
case MBlazeII::FRCR:
instr.addOperand(MCOperand::CreateReg(getRD(insn)));
instr.addOperand(MCOperand::CreateReg(getRB(insn)));
break;
case MBlazeII::FRCI:
instr.addOperand(MCOperand::CreateReg(getRD(insn)));
instr.addOperand(MCOperand::CreateImm(getIMM(insn)));
break;
case MBlazeII::FCCR:
instr.addOperand(MCOperand::CreateReg(getRB(insn)));
break;
case MBlazeII::FCCI:
instr.addOperand(MCOperand::CreateImm(getIMM(insn)));
break;
case MBlazeII::FRRCI:
instr.addOperand(MCOperand::CreateReg(getRD(insn)));
instr.addOperand(MCOperand::CreateReg(getRA(insn)));
instr.addOperand(MCOperand::CreateImm(getSHT(insn)));
break;
case MBlazeII::FRRC:
instr.addOperand(MCOperand::CreateReg(getRD(insn)));
instr.addOperand(MCOperand::CreateReg(getRA(insn)));
break;
case MBlazeII::FRCX:
instr.addOperand(MCOperand::CreateReg(getRD(insn)));
instr.addOperand(MCOperand::CreateImm(getFSL(insn)));
break;
case MBlazeII::FRCS:
instr.addOperand(MCOperand::CreateReg(getRD(insn)));
instr.addOperand(MCOperand::CreateImm(getRS(insn)));
break;
case MBlazeII::FCRCS:
instr.addOperand(MCOperand::CreateReg(getRA(insn)));
instr.addOperand(MCOperand::CreateImm(getRS(insn)));
break;
case MBlazeII::FCRCX:
instr.addOperand(MCOperand::CreateReg(getRA(insn)));
instr.addOperand(MCOperand::CreateImm(getFSL(insn)));
break;
case MBlazeII::FCX:
instr.addOperand(MCOperand::CreateImm(getFSL(insn)));
break;
case MBlazeII::FCR:
instr.addOperand(MCOperand::CreateReg(getRB(insn)));
break;
case MBlazeII::FRIR:
instr.addOperand(MCOperand::CreateReg(getRD(insn)));
instr.addOperand(MCOperand::CreateImm(getIMM(insn)));
instr.addOperand(MCOperand::CreateReg(getRA(insn)));
break;
}
return true;
}
void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
const MachineInstr &MI) {
MCInst &MappedInst = static_cast <MCInst &>(Inst);
const MCRegisterInfo *RI = OutStreamer->getContext().getRegisterInfo();
switch (Inst.getOpcode()) {
default: return;
case Hexagon::A2_iconst: {
Inst.setOpcode(Hexagon::A2_addi);
MCOperand Reg = Inst.getOperand(0);
MCOperand S16 = Inst.getOperand(1);
HexagonMCInstrInfo::setMustNotExtend(*S16.getExpr());
HexagonMCInstrInfo::setS23_2_reloc(*S16.getExpr());
Inst.clear();
Inst.addOperand(Reg);
Inst.addOperand(MCOperand::createReg(Hexagon::R0));
Inst.addOperand(S16);
break;
}
// "$dst = CONST64(#$src1)",
case Hexagon::CONST64:
if (!OutStreamer->hasRawTextSupport()) {
const MCOperand &Imm = MappedInst.getOperand(1);
MCSectionSubPair Current = OutStreamer->getCurrentSection();
MCSymbol *Sym = smallData(*this, MI, *OutStreamer, Imm, 8);
OutStreamer->SwitchSection(Current.first, Current.second);
MCInst TmpInst;
MCOperand &Reg = MappedInst.getOperand(0);
TmpInst.setOpcode(Hexagon::L2_loadrdgp);
TmpInst.addOperand(Reg);
TmpInst.addOperand(MCOperand::createExpr(
MCSymbolRefExpr::create(Sym, OutContext)));
MappedInst = TmpInst;
}
break;
case Hexagon::CONST32:
if (!OutStreamer->hasRawTextSupport()) {
MCOperand &Imm = MappedInst.getOperand(1);
MCSectionSubPair Current = OutStreamer->getCurrentSection();
MCSymbol *Sym = smallData(*this, MI, *OutStreamer, Imm, 4);
OutStreamer->SwitchSection(Current.first, Current.second);
MCInst TmpInst;
MCOperand &Reg = MappedInst.getOperand(0);
TmpInst.setOpcode(Hexagon::L2_loadrigp);
TmpInst.addOperand(Reg);
TmpInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create(
MCSymbolRefExpr::create(Sym, OutContext), OutContext)));
MappedInst = TmpInst;
}
break;
// C2_pxfer_map maps to C2_or instruction. Though, it's possible to use
// C2_or during instruction selection itself but it results
// into suboptimal code.
case Hexagon::C2_pxfer_map: {
MCOperand &Ps = Inst.getOperand(1);
MappedInst.setOpcode(Hexagon::C2_or);
MappedInst.addOperand(Ps);
return;
}
// Vector reduce complex multiply by scalar, Rt & 1 map to :hi else :lo
// The insn is mapped from the 4 operand to the 3 operand raw form taking
// 3 register pairs.
case Hexagon::M2_vrcmpys_acc_s1: {
MCOperand &Rt = Inst.getOperand(3);
assert (Rt.isReg() && "Expected register and none was found");
unsigned Reg = RI->getEncodingValue(Rt.getReg());
if (Reg & 1)
MappedInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_h);
else
MappedInst.setOpcode(Hexagon::M2_vrcmpys_acc_s1_l);
Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));
return;
}
case Hexagon::M2_vrcmpys_s1: {
MCOperand &Rt = Inst.getOperand(2);
assert (Rt.isReg() && "Expected register and none was found");
unsigned Reg = RI->getEncodingValue(Rt.getReg());
if (Reg & 1)
MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1_h);
else
MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1_l);
Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));
return;
}
case Hexagon::M2_vrcmpys_s1rp: {
MCOperand &Rt = Inst.getOperand(2);
assert (Rt.isReg() && "Expected register and none was found");
unsigned Reg = RI->getEncodingValue(Rt.getReg());
if (Reg & 1)
MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1rp_h);
else
MappedInst.setOpcode(Hexagon::M2_vrcmpys_s1rp_l);
Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));
return;
}
case Hexagon::A4_boundscheck: {
MCOperand &Rs = Inst.getOperand(1);
assert (Rs.isReg() && "Expected register and none was found");
unsigned Reg = RI->getEncodingValue(Rs.getReg());
if (Reg & 1) // Odd mapped to raw:hi, regpair is rodd:odd-1, like r3:2
MappedInst.setOpcode(Hexagon::A4_boundscheck_hi);
else // raw:lo
MappedInst.setOpcode(Hexagon::A4_boundscheck_lo);
Rs.setReg(getHexagonRegisterPair(Rs.getReg(), RI));
return;
}
case Hexagon::S5_asrhub_rnd_sat_goodsyntax: {
MCOperand &MO = MappedInst.getOperand(2);
int64_t Imm;
MCExpr const *Expr = MO.getExpr();
bool Success = Expr->evaluateAsAbsolute(Imm);
assert (Success && "Expected immediate and none was found");
(void)Success;
MCInst TmpInst;
if (Imm == 0) {
TmpInst.setOpcode(Hexagon::S2_vsathub);
TmpInst.addOperand(MappedInst.getOperand(0));
TmpInst.addOperand(MappedInst.getOperand(1));
MappedInst = TmpInst;
return;
}
TmpInst.setOpcode(Hexagon::S5_asrhub_rnd_sat);
TmpInst.addOperand(MappedInst.getOperand(0));
TmpInst.addOperand(MappedInst.getOperand(1));
const MCExpr *One = MCConstantExpr::create(1, OutContext);
const MCExpr *Sub = MCBinaryExpr::createSub(Expr, One, OutContext);
TmpInst.addOperand(
MCOperand::createExpr(HexagonMCExpr::create(Sub, OutContext)));
MappedInst = TmpInst;
return;
}
case Hexagon::S5_vasrhrnd_goodsyntax:
case Hexagon::S2_asr_i_p_rnd_goodsyntax: {
MCOperand &MO2 = MappedInst.getOperand(2);
MCExpr const *Expr = MO2.getExpr();
int64_t Imm;
bool Success = Expr->evaluateAsAbsolute(Imm);
assert (Success && "Expected immediate and none was found");
(void)Success;
MCInst TmpInst;
if (Imm == 0) {
TmpInst.setOpcode(Hexagon::A2_combinew);
TmpInst.addOperand(MappedInst.getOperand(0));
MCOperand &MO1 = MappedInst.getOperand(1);
unsigned High = RI->getSubReg(MO1.getReg(), Hexagon::subreg_hireg);
unsigned Low = RI->getSubReg(MO1.getReg(), Hexagon::subreg_loreg);
// Add a new operand for the second register in the pair.
TmpInst.addOperand(MCOperand::createReg(High));
TmpInst.addOperand(MCOperand::createReg(Low));
MappedInst = TmpInst;
return;
}
if (Inst.getOpcode() == Hexagon::S2_asr_i_p_rnd_goodsyntax)
TmpInst.setOpcode(Hexagon::S2_asr_i_p_rnd);
else
TmpInst.setOpcode(Hexagon::S5_vasrhrnd);
TmpInst.addOperand(MappedInst.getOperand(0));
TmpInst.addOperand(MappedInst.getOperand(1));
const MCExpr *One = MCConstantExpr::create(1, OutContext);
const MCExpr *Sub = MCBinaryExpr::createSub(Expr, One, OutContext);
TmpInst.addOperand(
MCOperand::createExpr(HexagonMCExpr::create(Sub, OutContext)));
MappedInst = TmpInst;
return;
}
// if ("#u5==0") Assembler mapped to: "Rd=Rs"; else Rd=asr(Rs,#u5-1):rnd
case Hexagon::S2_asr_i_r_rnd_goodsyntax: {
MCOperand &MO = Inst.getOperand(2);
MCExpr const *Expr = MO.getExpr();
int64_t Imm;
bool Success = Expr->evaluateAsAbsolute(Imm);
assert (Success && "Expected immediate and none was found");
(void)Success;
MCInst TmpInst;
if (Imm == 0) {
TmpInst.setOpcode(Hexagon::A2_tfr);
TmpInst.addOperand(MappedInst.getOperand(0));
TmpInst.addOperand(MappedInst.getOperand(1));
MappedInst = TmpInst;
return;
}
TmpInst.setOpcode(Hexagon::S2_asr_i_r_rnd);
TmpInst.addOperand(MappedInst.getOperand(0));
TmpInst.addOperand(MappedInst.getOperand(1));
const MCExpr *One = MCConstantExpr::create(1, OutContext);
const MCExpr *Sub = MCBinaryExpr::createSub(Expr, One, OutContext);
TmpInst.addOperand(
MCOperand::createExpr(HexagonMCExpr::create(Sub, OutContext)));
MappedInst = TmpInst;
return;
}
// Translate a "$Rdd = #imm" to "$Rdd = combine(#[-1,0], #imm)"
case Hexagon::A2_tfrpi: {
MCInst TmpInst;
MCOperand &Rdd = MappedInst.getOperand(0);
MCOperand &MO = MappedInst.getOperand(1);
TmpInst.setOpcode(Hexagon::A2_combineii);
TmpInst.addOperand(Rdd);
int64_t Imm;
bool Success = MO.getExpr()->evaluateAsAbsolute(Imm);
if (Success && Imm < 0) {
const MCExpr *MOne = MCConstantExpr::create(-1, OutContext);
TmpInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create(MOne, OutContext)));
} else {
const MCExpr *Zero = MCConstantExpr::create(0, OutContext);
TmpInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create(Zero, OutContext)));
}
TmpInst.addOperand(MO);
MappedInst = TmpInst;
return;
}
// Translate a "$Rdd = $Rss" to "$Rdd = combine($Rs, $Rt)"
case Hexagon::A2_tfrp: {
MCOperand &MO = MappedInst.getOperand(1);
unsigned High = RI->getSubReg(MO.getReg(), Hexagon::subreg_hireg);
unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::subreg_loreg);
MO.setReg(High);
// Add a new operand for the second register in the pair.
MappedInst.addOperand(MCOperand::createReg(Low));
MappedInst.setOpcode(Hexagon::A2_combinew);
return;
}
case Hexagon::A2_tfrpt:
case Hexagon::A2_tfrpf: {
MCOperand &MO = MappedInst.getOperand(2);
unsigned High = RI->getSubReg(MO.getReg(), Hexagon::subreg_hireg);
unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::subreg_loreg);
MO.setReg(High);
// Add a new operand for the second register in the pair.
MappedInst.addOperand(MCOperand::createReg(Low));
MappedInst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt)
? Hexagon::C2_ccombinewt
: Hexagon::C2_ccombinewf);
return;
}
case Hexagon::A2_tfrptnew:
case Hexagon::A2_tfrpfnew: {
MCOperand &MO = MappedInst.getOperand(2);
unsigned High = RI->getSubReg(MO.getReg(), Hexagon::subreg_hireg);
unsigned Low = RI->getSubReg(MO.getReg(), Hexagon::subreg_loreg);
MO.setReg(High);
// Add a new operand for the second register in the pair.
MappedInst.addOperand(MCOperand::createReg(Low));
MappedInst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrptnew)
? Hexagon::C2_ccombinewnewt
: Hexagon::C2_ccombinewnewf);
return;
}
case Hexagon::M2_mpysmi: {
MCOperand &Imm = MappedInst.getOperand(2);
MCExpr const *Expr = Imm.getExpr();
int64_t Value;
bool Success = Expr->evaluateAsAbsolute(Value);
assert(Success);
(void)Success;
if (Value < 0 && Value > -256) {
MappedInst.setOpcode(Hexagon::M2_mpysin);
Imm.setExpr(HexagonMCExpr::create(
MCUnaryExpr::createMinus(Expr, OutContext), OutContext));
} else
MappedInst.setOpcode(Hexagon::M2_mpysip);
return;
}
case Hexagon::A2_addsp: {
MCOperand &Rt = Inst.getOperand(1);
assert (Rt.isReg() && "Expected register and none was found");
unsigned Reg = RI->getEncodingValue(Rt.getReg());
if (Reg & 1)
MappedInst.setOpcode(Hexagon::A2_addsph);
else
MappedInst.setOpcode(Hexagon::A2_addspl);
Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));
return;
}
case Hexagon::V6_vd0:
case Hexagon::V6_vd0_128B: {
MCInst TmpInst;
assert (Inst.getOperand(0).isReg() &&
"Expected register and none was found");
TmpInst.setOpcode(Hexagon::V6_vxor);
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(0));
TmpInst.addOperand(Inst.getOperand(0));
MappedInst = TmpInst;
return;
}
}
}
void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
OutMI.setOpcode(MI->getOpcode());
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
MCOperand MCOp;
switch (MO.getType()) {
default:
MI->dump();
llvm_unreachable("unknown operand type");
case MachineOperand::MO_Register:
// Ignore all implicit register operands.
if (MO.isImplicit()) continue;
MCOp = MCOperand::CreateReg(MO.getReg());
break;
case MachineOperand::MO_Immediate:
MCOp = MCOperand::CreateImm(MO.getImm());
break;
case MachineOperand::MO_MachineBasicBlock:
case MachineOperand::MO_GlobalAddress:
case MachineOperand::MO_ExternalSymbol:
MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
break;
case MachineOperand::MO_JumpTableIndex:
MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
break;
case MachineOperand::MO_ConstantPoolIndex:
MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
break;
case MachineOperand::MO_BlockAddress:
MCOp = LowerSymbolOperand(MO,
AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
break;
case MachineOperand::MO_RegisterMask:
// Ignore call clobbers.
continue;
}
OutMI.addOperand(MCOp);
}
// Handle a few special cases to eliminate operand modifiers.
ReSimplify:
switch (OutMI.getOpcode()) {
case X86::LEA64_32r:
case X86::LEA64r:
case X86::LEA16r:
case X86::LEA32r:
// LEA should have a segment register, but it must be empty.
assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
"Unexpected # of LEA operands");
assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
"LEA has segment specified!");
break;
case X86::MOV32r0: LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); break;
case X86::MOV32ri64:
OutMI.setOpcode(X86::MOV32ri);
break;
// Commute operands to get a smaller encoding by using VEX.R instead of VEX.B
// if one of the registers is extended, but other isn't.
case X86::VMOVAPDrr:
case X86::VMOVAPDYrr:
case X86::VMOVAPSrr:
case X86::VMOVAPSYrr:
case X86::VMOVDQArr:
case X86::VMOVDQAYrr:
case X86::VMOVDQUrr:
case X86::VMOVDQUYrr:
case X86::VMOVUPDrr:
case X86::VMOVUPDYrr:
case X86::VMOVUPSrr:
case X86::VMOVUPSYrr: {
if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
X86II::isX86_64ExtendedReg(OutMI.getOperand(1).getReg())) {
unsigned NewOpc;
switch (OutMI.getOpcode()) {
default: llvm_unreachable("Invalid opcode");
case X86::VMOVAPDrr: NewOpc = X86::VMOVAPDrr_REV; break;
case X86::VMOVAPDYrr: NewOpc = X86::VMOVAPDYrr_REV; break;
case X86::VMOVAPSrr: NewOpc = X86::VMOVAPSrr_REV; break;
case X86::VMOVAPSYrr: NewOpc = X86::VMOVAPSYrr_REV; break;
case X86::VMOVDQArr: NewOpc = X86::VMOVDQArr_REV; break;
case X86::VMOVDQAYrr: NewOpc = X86::VMOVDQAYrr_REV; break;
case X86::VMOVDQUrr: NewOpc = X86::VMOVDQUrr_REV; break;
case X86::VMOVDQUYrr: NewOpc = X86::VMOVDQUYrr_REV; break;
case X86::VMOVUPDrr: NewOpc = X86::VMOVUPDrr_REV; break;
case X86::VMOVUPDYrr: NewOpc = X86::VMOVUPDYrr_REV; break;
case X86::VMOVUPSrr: NewOpc = X86::VMOVUPSrr_REV; break;
case X86::VMOVUPSYrr: NewOpc = X86::VMOVUPSYrr_REV; break;
}
OutMI.setOpcode(NewOpc);
}
break;
}
case X86::VMOVSDrr:
case X86::VMOVSSrr: {
if (!X86II::isX86_64ExtendedReg(OutMI.getOperand(0).getReg()) &&
X86II::isX86_64ExtendedReg(OutMI.getOperand(2).getReg())) {
unsigned NewOpc;
switch (OutMI.getOpcode()) {
default: llvm_unreachable("Invalid opcode");
case X86::VMOVSDrr: NewOpc = X86::VMOVSDrr_REV; break;
case X86::VMOVSSrr: NewOpc = X86::VMOVSSrr_REV; break;
}
OutMI.setOpcode(NewOpc);
}
break;
}
// TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have register
// inputs modeled as normal uses instead of implicit uses. As such, truncate
// off all but the first operand (the callee). FIXME: Change isel.
case X86::TAILJMPr64:
case X86::CALL64r:
case X86::CALL64pcrel32: {
unsigned Opcode = OutMI.getOpcode();
MCOperand Saved = OutMI.getOperand(0);
OutMI = MCInst();
OutMI.setOpcode(Opcode);
OutMI.addOperand(Saved);
break;
}
case X86::EH_RETURN:
case X86::EH_RETURN64: {
OutMI = MCInst();
OutMI.setOpcode(X86::RET);
break;
}
// TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
case X86::TAILJMPr:
case X86::TAILJMPd:
case X86::TAILJMPd64: {
unsigned Opcode;
switch (OutMI.getOpcode()) {
default: llvm_unreachable("Invalid opcode");
case X86::TAILJMPr: Opcode = X86::JMP32r; break;
case X86::TAILJMPd:
case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
}
MCOperand Saved = OutMI.getOperand(0);
OutMI = MCInst();
OutMI.setOpcode(Opcode);
OutMI.addOperand(Saved);
break;
}
// These are pseudo-ops for OR to help with the OR->ADD transformation. We do
// this with an ugly goto in case the resultant OR uses EAX and needs the
// short form.
case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
// The assembler backend wants to see branches in their small form and relax
// them to their large form. The JIT can only handle the large form because
// it does not do relaxation. For now, translate the large form to the
// small one here.
case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break;
case X86::JO_4: OutMI.setOpcode(X86::JO_1); break;
case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break;
case X86::JB_4: OutMI.setOpcode(X86::JB_1); break;
case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break;
case X86::JE_4: OutMI.setOpcode(X86::JE_1); break;
case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break;
case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break;
case X86::JA_4: OutMI.setOpcode(X86::JA_1); break;
case X86::JS_4: OutMI.setOpcode(X86::JS_1); break;
case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break;
case X86::JP_4: OutMI.setOpcode(X86::JP_1); break;
case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break;
case X86::JL_4: OutMI.setOpcode(X86::JL_1); break;
case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break;
case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break;
case X86::JG_4: OutMI.setOpcode(X86::JG_1); break;
// Atomic load and store require a separate pseudo-inst because Acquire
// implies mayStore and Release implies mayLoad; fix these to regular MOV
// instructions here
case X86::ACQUIRE_MOV8rm: OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
case X86::RELEASE_MOV8mr: OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
// We don't currently select the correct instruction form for instructions
// which have a short %eax, etc. form. Handle this by custom lowering, for
// now.
//
// Note, we are currently not handling the following instructions:
// MOV64ao8, MOV64o8a
// XCHG16ar, XCHG32ar, XCHG64ar
case X86::MOV8mr_NOREX:
case X86::MOV8mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao8); break;
case X86::MOV8rm_NOREX:
case X86::MOV8rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o8a); break;
case X86::MOV16mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao16); break;
case X86::MOV16rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o16a); break;
case X86::MOV32mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
case X86::MOV32rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
case X86::ADC8ri: SimplifyShortImmForm(OutMI, X86::ADC8i8); break;
case X86::ADC16ri: SimplifyShortImmForm(OutMI, X86::ADC16i16); break;
case X86::ADC32ri: SimplifyShortImmForm(OutMI, X86::ADC32i32); break;
case X86::ADC64ri32: SimplifyShortImmForm(OutMI, X86::ADC64i32); break;
case X86::ADD8ri: SimplifyShortImmForm(OutMI, X86::ADD8i8); break;
case X86::ADD16ri: SimplifyShortImmForm(OutMI, X86::ADD16i16); break;
case X86::ADD32ri: SimplifyShortImmForm(OutMI, X86::ADD32i32); break;
case X86::ADD64ri32: SimplifyShortImmForm(OutMI, X86::ADD64i32); break;
case X86::AND8ri: SimplifyShortImmForm(OutMI, X86::AND8i8); break;
case X86::AND16ri: SimplifyShortImmForm(OutMI, X86::AND16i16); break;
case X86::AND32ri: SimplifyShortImmForm(OutMI, X86::AND32i32); break;
case X86::AND64ri32: SimplifyShortImmForm(OutMI, X86::AND64i32); break;
case X86::CMP8ri: SimplifyShortImmForm(OutMI, X86::CMP8i8); break;
case X86::CMP16ri: SimplifyShortImmForm(OutMI, X86::CMP16i16); break;
case X86::CMP32ri: SimplifyShortImmForm(OutMI, X86::CMP32i32); break;
case X86::CMP64ri32: SimplifyShortImmForm(OutMI, X86::CMP64i32); break;
case X86::OR8ri: SimplifyShortImmForm(OutMI, X86::OR8i8); break;
case X86::OR16ri: SimplifyShortImmForm(OutMI, X86::OR16i16); break;
case X86::OR32ri: SimplifyShortImmForm(OutMI, X86::OR32i32); break;
case X86::OR64ri32: SimplifyShortImmForm(OutMI, X86::OR64i32); break;
case X86::SBB8ri: SimplifyShortImmForm(OutMI, X86::SBB8i8); break;
case X86::SBB16ri: SimplifyShortImmForm(OutMI, X86::SBB16i16); break;
case X86::SBB32ri: SimplifyShortImmForm(OutMI, X86::SBB32i32); break;
case X86::SBB64ri32: SimplifyShortImmForm(OutMI, X86::SBB64i32); break;
case X86::SUB8ri: SimplifyShortImmForm(OutMI, X86::SUB8i8); break;
case X86::SUB16ri: SimplifyShortImmForm(OutMI, X86::SUB16i16); break;
case X86::SUB32ri: SimplifyShortImmForm(OutMI, X86::SUB32i32); break;
case X86::SUB64ri32: SimplifyShortImmForm(OutMI, X86::SUB64i32); break;
case X86::TEST8ri: SimplifyShortImmForm(OutMI, X86::TEST8i8); break;
case X86::TEST16ri: SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
case X86::TEST32ri: SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
case X86::XOR8ri: SimplifyShortImmForm(OutMI, X86::XOR8i8); break;
case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break;
case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break;
case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break;
case X86::MORESTACK_RET:
OutMI.setOpcode(X86::RET);
break;
case X86::MORESTACK_RET_RESTORE_R10:
OutMI.setOpcode(X86::MOV64rr);
OutMI.addOperand(MCOperand::CreateReg(X86::R10));
OutMI.addOperand(MCOperand::CreateReg(X86::RAX));
AsmPrinter.OutStreamer.EmitInstruction(MCInstBuilder(X86::RET));
break;
}
}
void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
OutMI.setOpcode(MI->getOpcode());
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
MCOperand MCOp;
switch (MO.getType()) {
default:
MI->dump();
llvm_unreachable("unknown operand type");
case MachineOperand::MO_Register:
// Ignore all implicit register operands.
if (MO.isImplicit()) continue;
MCOp = MCOperand::CreateReg(MO.getReg());
break;
case MachineOperand::MO_Immediate:
MCOp = MCOperand::CreateImm(MO.getImm());
break;
case MachineOperand::MO_MachineBasicBlock:
MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
MO.getMBB()->getSymbol(), Ctx));
break;
case MachineOperand::MO_GlobalAddress:
case MachineOperand::MO_ExternalSymbol:
MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
break;
case MachineOperand::MO_JumpTableIndex:
MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
break;
case MachineOperand::MO_ConstantPoolIndex:
MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
break;
case MachineOperand::MO_BlockAddress:
MCOp = LowerSymbolOperand(MO,
AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
break;
}
OutMI.addOperand(MCOp);
}
// Handle a few special cases to eliminate operand modifiers.
ReSimplify:
switch (OutMI.getOpcode()) {
case X86::LEA64_32r: // Handle 'subreg rewriting' for the lea64_32mem operand.
lower_lea64_32mem(&OutMI, 1);
// FALL THROUGH.
case X86::LEA64r:
case X86::LEA16r:
case X86::LEA32r:
// LEA should have a segment register, but it must be empty.
assert(OutMI.getNumOperands() == 1+X86::AddrNumOperands &&
"Unexpected # of LEA operands");
assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 &&
"LEA has segment specified!");
break;
case X86::MOVZX64rr32: LowerSubReg32_Op0(OutMI, X86::MOV32rr); break;
case X86::MOVZX64rm32: LowerSubReg32_Op0(OutMI, X86::MOV32rm); break;
case X86::MOV64ri64i32: LowerSubReg32_Op0(OutMI, X86::MOV32ri); break;
case X86::MOVZX64rr8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr8); break;
case X86::MOVZX64rm8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break;
case X86::MOVZX64rr16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr16); break;
case X86::MOVZX64rm16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm16); break;
case X86::SETB_C8r: LowerUnaryToTwoAddr(OutMI, X86::SBB8rr); break;
case X86::SETB_C16r: LowerUnaryToTwoAddr(OutMI, X86::SBB16rr); break;
case X86::SETB_C32r: LowerUnaryToTwoAddr(OutMI, X86::SBB32rr); break;
case X86::SETB_C64r: LowerUnaryToTwoAddr(OutMI, X86::SBB64rr); break;
case X86::MOV8r0: LowerUnaryToTwoAddr(OutMI, X86::XOR8rr); break;
case X86::MOV32r0: LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); break;
case X86::FsFLD0SS: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
case X86::FsFLD0SD: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
case X86::VFsFLD0SS: LowerUnaryToTwoAddr(OutMI, X86::VPXORrr); break;
case X86::VFsFLD0SD: LowerUnaryToTwoAddr(OutMI, X86::VPXORrr); break;
case X86::V_SET0PS: LowerUnaryToTwoAddr(OutMI, X86::XORPSrr); break;
case X86::V_SET0PD: LowerUnaryToTwoAddr(OutMI, X86::XORPDrr); break;
case X86::V_SET0PI: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
case X86::V_SETALLONES: LowerUnaryToTwoAddr(OutMI, X86::PCMPEQDrr); break;
case X86::AVX_SET0PS: LowerUnaryToTwoAddr(OutMI, X86::VXORPSrr); break;
case X86::AVX_SET0PSY: LowerUnaryToTwoAddr(OutMI, X86::VXORPSYrr); break;
case X86::AVX_SET0PD: LowerUnaryToTwoAddr(OutMI, X86::VXORPDrr); break;
case X86::AVX_SET0PDY: LowerUnaryToTwoAddr(OutMI, X86::VXORPDYrr); break;
case X86::AVX_SET0PI: LowerUnaryToTwoAddr(OutMI, X86::VPXORrr); break;
case X86::AVX_SETALLONES: LowerUnaryToTwoAddr(OutMI, X86::VPCMPEQDrr); break;
case X86::MOV16r0:
LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV16r0 -> MOV32r0
LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
break;
case X86::MOV64r0:
LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV64r0 -> MOV32r0
LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
break;
// TAILJMPr64, [WIN]CALL64r, [WIN]CALL64pcrel32 - These instructions have
// register inputs modeled as normal uses instead of implicit uses. As such,
// truncate off all but the first operand (the callee). FIXME: Change isel.
case X86::TAILJMPr64:
case X86::CALL64r:
case X86::CALL64pcrel32:
case X86::WINCALL64r:
case X86::WINCALL64pcrel32: {
unsigned Opcode = OutMI.getOpcode();
MCOperand Saved = OutMI.getOperand(0);
OutMI = MCInst();
OutMI.setOpcode(Opcode);
OutMI.addOperand(Saved);
break;
}
case X86::EH_RETURN:
case X86::EH_RETURN64: {
OutMI = MCInst();
OutMI.setOpcode(X86::RET);
break;
}
// TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
case X86::TAILJMPr:
case X86::TAILJMPd:
case X86::TAILJMPd64: {
unsigned Opcode;
switch (OutMI.getOpcode()) {
default: assert(0 && "Invalid opcode");
case X86::TAILJMPr: Opcode = X86::JMP32r; break;
case X86::TAILJMPd:
case X86::TAILJMPd64: Opcode = X86::JMP_1; break;
}
MCOperand Saved = OutMI.getOperand(0);
OutMI = MCInst();
OutMI.setOpcode(Opcode);
OutMI.addOperand(Saved);
break;
}
// These are pseudo-ops for OR to help with the OR->ADD transformation. We do
// this with an ugly goto in case the resultant OR uses EAX and needs the
// short form.
case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify;
case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify;
case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify;
case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify;
case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify;
case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify;
case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify;
case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify;
case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify;
// The assembler backend wants to see branches in their small form and relax
// them to their large form. The JIT can only handle the large form because
// it does not do relaxation. For now, translate the large form to the
// small one here.
case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break;
case X86::JO_4: OutMI.setOpcode(X86::JO_1); break;
case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break;
case X86::JB_4: OutMI.setOpcode(X86::JB_1); break;
case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break;
case X86::JE_4: OutMI.setOpcode(X86::JE_1); break;
case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break;
case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break;
case X86::JA_4: OutMI.setOpcode(X86::JA_1); break;
case X86::JS_4: OutMI.setOpcode(X86::JS_1); break;
case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break;
case X86::JP_4: OutMI.setOpcode(X86::JP_1); break;
case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break;
case X86::JL_4: OutMI.setOpcode(X86::JL_1); break;
case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break;
case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break;
case X86::JG_4: OutMI.setOpcode(X86::JG_1); break;
// Atomic load and store require a separate pseudo-inst because Acquire
// implies mayStore and Release implies mayLoad; fix these to regular MOV
// instructions here
case X86::ACQUIRE_MOV8rm: OutMI.setOpcode(X86::MOV8rm); goto ReSimplify;
case X86::ACQUIRE_MOV16rm: OutMI.setOpcode(X86::MOV16rm); goto ReSimplify;
case X86::ACQUIRE_MOV32rm: OutMI.setOpcode(X86::MOV32rm); goto ReSimplify;
case X86::ACQUIRE_MOV64rm: OutMI.setOpcode(X86::MOV64rm); goto ReSimplify;
case X86::RELEASE_MOV8mr: OutMI.setOpcode(X86::MOV8mr); goto ReSimplify;
case X86::RELEASE_MOV16mr: OutMI.setOpcode(X86::MOV16mr); goto ReSimplify;
case X86::RELEASE_MOV32mr: OutMI.setOpcode(X86::MOV32mr); goto ReSimplify;
case X86::RELEASE_MOV64mr: OutMI.setOpcode(X86::MOV64mr); goto ReSimplify;
// We don't currently select the correct instruction form for instructions
// which have a short %eax, etc. form. Handle this by custom lowering, for
// now.
//
// Note, we are currently not handling the following instructions:
// MOV64ao8, MOV64o8a
// XCHG16ar, XCHG32ar, XCHG64ar
case X86::MOV8mr_NOREX:
case X86::MOV8mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8ao8); break;
case X86::MOV8rm_NOREX:
case X86::MOV8rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV8o8a); break;
case X86::MOV16mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16ao16); break;
case X86::MOV16rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV16o16a); break;
case X86::MOV32mr: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32ao32); break;
case X86::MOV32rm: SimplifyShortMoveForm(AsmPrinter, OutMI, X86::MOV32o32a); break;
case X86::ADC8ri: SimplifyShortImmForm(OutMI, X86::ADC8i8); break;
case X86::ADC16ri: SimplifyShortImmForm(OutMI, X86::ADC16i16); break;
case X86::ADC32ri: SimplifyShortImmForm(OutMI, X86::ADC32i32); break;
case X86::ADC64ri32: SimplifyShortImmForm(OutMI, X86::ADC64i32); break;
case X86::ADD8ri: SimplifyShortImmForm(OutMI, X86::ADD8i8); break;
case X86::ADD16ri: SimplifyShortImmForm(OutMI, X86::ADD16i16); break;
case X86::ADD32ri: SimplifyShortImmForm(OutMI, X86::ADD32i32); break;
case X86::ADD64ri32: SimplifyShortImmForm(OutMI, X86::ADD64i32); break;
case X86::AND8ri: SimplifyShortImmForm(OutMI, X86::AND8i8); break;
case X86::AND16ri: SimplifyShortImmForm(OutMI, X86::AND16i16); break;
case X86::AND32ri: SimplifyShortImmForm(OutMI, X86::AND32i32); break;
case X86::AND64ri32: SimplifyShortImmForm(OutMI, X86::AND64i32); break;
case X86::CMP8ri: SimplifyShortImmForm(OutMI, X86::CMP8i8); break;
case X86::CMP16ri: SimplifyShortImmForm(OutMI, X86::CMP16i16); break;
case X86::CMP32ri: SimplifyShortImmForm(OutMI, X86::CMP32i32); break;
case X86::CMP64ri32: SimplifyShortImmForm(OutMI, X86::CMP64i32); break;
case X86::OR8ri: SimplifyShortImmForm(OutMI, X86::OR8i8); break;
case X86::OR16ri: SimplifyShortImmForm(OutMI, X86::OR16i16); break;
case X86::OR32ri: SimplifyShortImmForm(OutMI, X86::OR32i32); break;
case X86::OR64ri32: SimplifyShortImmForm(OutMI, X86::OR64i32); break;
case X86::SBB8ri: SimplifyShortImmForm(OutMI, X86::SBB8i8); break;
case X86::SBB16ri: SimplifyShortImmForm(OutMI, X86::SBB16i16); break;
case X86::SBB32ri: SimplifyShortImmForm(OutMI, X86::SBB32i32); break;
case X86::SBB64ri32: SimplifyShortImmForm(OutMI, X86::SBB64i32); break;
case X86::SUB8ri: SimplifyShortImmForm(OutMI, X86::SUB8i8); break;
case X86::SUB16ri: SimplifyShortImmForm(OutMI, X86::SUB16i16); break;
case X86::SUB32ri: SimplifyShortImmForm(OutMI, X86::SUB32i32); break;
case X86::SUB64ri32: SimplifyShortImmForm(OutMI, X86::SUB64i32); break;
case X86::TEST8ri: SimplifyShortImmForm(OutMI, X86::TEST8i8); break;
case X86::TEST16ri: SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
case X86::TEST32ri: SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
case X86::XOR8ri: SimplifyShortImmForm(OutMI, X86::XOR8i8); break;
case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break;
case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break;
case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break;
}
}
// Create an MCInst from a MachineInstr
void llvm::HexagonLowerToMC(MachineInstr const* MI, MCInst& MCB,
HexagonAsmPrinter& AP) {
if(MI->getOpcode() == Hexagon::ENDLOOP0){
HexagonMCInstrInfo::setInnerLoop(MCB);
return;
}
if(MI->getOpcode() == Hexagon::ENDLOOP1){
HexagonMCInstrInfo::setOuterLoop(MCB);
return;
}
MCInst* MCI = new (AP.OutContext) MCInst;
MCI->setOpcode(MI->getOpcode());
assert(MCI->getOpcode() == static_cast<unsigned>(MI->getOpcode()) &&
"MCI opcode should have been set on construction");
for (unsigned i = 0, e = MI->getNumOperands(); i < e; i++) {
const MachineOperand &MO = MI->getOperand(i);
MCOperand MCO;
switch (MO.getType()) {
default:
MI->dump();
llvm_unreachable("unknown operand type");
case MachineOperand::MO_Register:
// Ignore all implicit register operands.
if (MO.isImplicit()) continue;
MCO = MCOperand::createReg(MO.getReg());
break;
case MachineOperand::MO_FPImmediate: {
APFloat Val = MO.getFPImm()->getValueAPF();
// FP immediates are used only when setting GPRs, so they may be dealt
// with like regular immediates from this point on.
MCO = MCOperand::createImm(*Val.bitcastToAPInt().getRawData());
break;
}
case MachineOperand::MO_Immediate:
MCO = MCOperand::createImm(MO.getImm());
break;
case MachineOperand::MO_MachineBasicBlock:
MCO = MCOperand::createExpr
(MCSymbolRefExpr::create(MO.getMBB()->getSymbol(),
AP.OutContext));
break;
case MachineOperand::MO_GlobalAddress:
MCO = GetSymbolRef(MO, AP.getSymbol(MO.getGlobal()), AP);
break;
case MachineOperand::MO_ExternalSymbol:
MCO = GetSymbolRef(MO, AP.GetExternalSymbolSymbol(MO.getSymbolName()),
AP);
break;
case MachineOperand::MO_JumpTableIndex:
MCO = GetSymbolRef(MO, AP.GetJTISymbol(MO.getIndex()), AP);
break;
case MachineOperand::MO_ConstantPoolIndex:
MCO = GetSymbolRef(MO, AP.GetCPISymbol(MO.getIndex()), AP);
break;
case MachineOperand::MO_BlockAddress:
MCO = GetSymbolRef(MO, AP.GetBlockAddressSymbol(MO.getBlockAddress()),AP);
break;
}
MCI->addOperand(MCO);
}
MCB.addOperand(MCOperand::createInst(MCI));
}
void WebAssemblyMCInstLower::Lower(const MachineInstr *MI,
MCInst &OutMI) const {
OutMI.setOpcode(MI->getOpcode());
const MCInstrDesc &Desc = MI->getDesc();
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
MCOperand MCOp;
switch (MO.getType()) {
default:
MI->print(errs());
llvm_unreachable("unknown operand type");
case MachineOperand::MO_MachineBasicBlock:
MI->print(errs());
llvm_unreachable("MachineBasicBlock operand should have been rewritten");
case MachineOperand::MO_Register: {
// Ignore all implicit register operands.
if (MO.isImplicit())
continue;
const WebAssemblyFunctionInfo &MFI =
*MI->getParent()->getParent()->getInfo<WebAssemblyFunctionInfo>();
unsigned WAReg = MFI.getWAReg(MO.getReg());
MCOp = MCOperand::createReg(WAReg);
break;
}
case MachineOperand::MO_Immediate:
if (i < Desc.NumOperands) {
const MCOperandInfo &Info = Desc.OpInfo[i];
if (Info.OperandType == WebAssembly::OPERAND_TYPEINDEX) {
MCSymbol *Sym = Printer.createTempSymbol("typeindex");
SmallVector<wasm::ValType, 4> Returns;
SmallVector<wasm::ValType, 4> Params;
const MachineRegisterInfo &MRI =
MI->getParent()->getParent()->getRegInfo();
for (const MachineOperand &MO : MI->defs())
Returns.push_back(getType(MRI.getRegClass(MO.getReg())));
for (const MachineOperand &MO : MI->explicit_uses())
if (MO.isReg())
Params.push_back(getType(MRI.getRegClass(MO.getReg())));
// call_indirect instructions have a callee operand at the end which
// doesn't count as a param.
if (WebAssembly::isCallIndirect(*MI))
Params.pop_back();
MCSymbolWasm *WasmSym = cast<MCSymbolWasm>(Sym);
auto Signature = make_unique<wasm::WasmSignature>(std::move(Returns),
std::move(Params));
WasmSym->setSignature(Signature.get());
Printer.addSignature(std::move(Signature));
WasmSym->setType(wasm::WASM_SYMBOL_TYPE_FUNCTION);
const MCExpr *Expr = MCSymbolRefExpr::create(
WasmSym, MCSymbolRefExpr::VK_WebAssembly_TYPEINDEX, Ctx);
MCOp = MCOperand::createExpr(Expr);
break;
}
}
MCOp = MCOperand::createImm(MO.getImm());
break;
case MachineOperand::MO_FPImmediate: {
// TODO: MC converts all floating point immediate operands to double.
// This is fine for numeric values, but may cause NaNs to change bits.
const ConstantFP *Imm = MO.getFPImm();
if (Imm->getType()->isFloatTy())
MCOp = MCOperand::createFPImm(Imm->getValueAPF().convertToFloat());
else if (Imm->getType()->isDoubleTy())
MCOp = MCOperand::createFPImm(Imm->getValueAPF().convertToDouble());
else
llvm_unreachable("unknown floating point immediate type");
break;
}
case MachineOperand::MO_GlobalAddress:
assert(MO.getTargetFlags() == WebAssemblyII::MO_NO_FLAG &&
"WebAssembly does not use target flags on GlobalAddresses");
MCOp = LowerSymbolOperand(GetGlobalAddressSymbol(MO), MO.getOffset(),
MO.getGlobal()->getValueType()->isFunctionTy(),
false, false);
break;
case MachineOperand::MO_ExternalSymbol:
// The target flag indicates whether this is a symbol for a
// variable or a function.
assert((MO.getTargetFlags() & ~WebAssemblyII::MO_SYMBOL_MASK) == 0 &&
"WebAssembly uses only symbol flags on ExternalSymbols");
MCOp = LowerSymbolOperand(
GetExternalSymbolSymbol(MO), /*Offset=*/0,
(MO.getTargetFlags() & WebAssemblyII::MO_SYMBOL_FUNCTION) != 0,
(MO.getTargetFlags() & WebAssemblyII::MO_SYMBOL_GLOBAL) != 0,
(MO.getTargetFlags() & WebAssemblyII::MO_SYMBOL_EVENT) != 0);
break;
case MachineOperand::MO_MCSymbol:
// This is currently used only for LSDA symbols (GCC_except_table),
// because global addresses or other external symbols are handled above.
assert(MO.getTargetFlags() == 0 &&
"WebAssembly does not use target flags on MCSymbol");
MCOp = LowerSymbolOperand(MO.getMCSymbol(), /*Offset=*/0, false, false,
false);
break;
}
OutMI.addOperand(MCOp);
}
if (!WasmKeepRegisters)
removeRegisterOperands(MI, OutMI);
}
void WebAssemblyMCInstLower::Lower(const MachineInstr *MI,
MCInst &OutMI) const {
OutMI.setOpcode(MI->getOpcode());
const MCInstrDesc &Desc = MI->getDesc();
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
MCOperand MCOp;
switch (MO.getType()) {
default:
MI->print(errs());
llvm_unreachable("unknown operand type");
case MachineOperand::MO_MachineBasicBlock:
MI->print(errs());
llvm_unreachable("MachineBasicBlock operand should have been rewritten");
case MachineOperand::MO_Register: {
// Ignore all implicit register operands.
if (MO.isImplicit())
continue;
const WebAssemblyFunctionInfo &MFI =
*MI->getParent()->getParent()->getInfo<WebAssemblyFunctionInfo>();
unsigned WAReg = MFI.getWAReg(MO.getReg());
MCOp = MCOperand::createReg(WAReg);
break;
}
case MachineOperand::MO_Immediate:
if (i < Desc.NumOperands) {
const MCOperandInfo &Info = Desc.OpInfo[i];
if (Info.OperandType == WebAssembly::OPERAND_TYPEINDEX) {
MCSymbol *Sym = Printer.createTempSymbol("typeindex");
if (!isa<MCSymbolELF>(Sym)) {
SmallVector<unsigned, 4> Returns;
SmallVector<unsigned, 4> Params;
const MachineRegisterInfo &MRI =
MI->getParent()->getParent()->getRegInfo();
for (const MachineOperand &MO : MI->defs())
Returns.push_back(getType(MRI.getRegClass(MO.getReg())));
for (const MachineOperand &MO : MI->explicit_uses())
if (MO.isReg())
Params.push_back(getType(MRI.getRegClass(MO.getReg())));
// call_indirect instructions have a callee operand at the end which
// doesn't count as a param.
if (WebAssembly::isCallIndirect(*MI))
Params.pop_back();
MCSymbolWasm *WasmSym = cast<MCSymbolWasm>(Sym);
WasmSym->setReturns(std::move(Returns));
WasmSym->setParams(std::move(Params));
WasmSym->setIsFunction(true);
const MCExpr *Expr =
MCSymbolRefExpr::create(WasmSym,
MCSymbolRefExpr::VK_WebAssembly_TYPEINDEX,
Ctx);
MCOp = MCOperand::createExpr(Expr);
break;
}
}
}
MCOp = MCOperand::createImm(MO.getImm());
break;
case MachineOperand::MO_FPImmediate: {
// TODO: MC converts all floating point immediate operands to double.
// This is fine for numeric values, but may cause NaNs to change bits.
const ConstantFP *Imm = MO.getFPImm();
if (Imm->getType()->isFloatTy())
MCOp = MCOperand::createFPImm(Imm->getValueAPF().convertToFloat());
else if (Imm->getType()->isDoubleTy())
MCOp = MCOperand::createFPImm(Imm->getValueAPF().convertToDouble());
else
llvm_unreachable("unknown floating point immediate type");
break;
}
case MachineOperand::MO_GlobalAddress:
assert(MO.getTargetFlags() == 0 &&
"WebAssembly does not use target flags on GlobalAddresses");
MCOp = LowerSymbolOperand(GetGlobalAddressSymbol(MO), MO.getOffset(),
MO.getGlobal()->getValueType()->isFunctionTy());
break;
case MachineOperand::MO_ExternalSymbol:
// The target flag indicates whether this is a symbol for a
// variable or a function.
assert((MO.getTargetFlags() & -2) == 0 &&
"WebAssembly uses only one target flag bit on ExternalSymbols");
MCOp = LowerSymbolOperand(GetExternalSymbolSymbol(MO), /*Offset=*/0,
MO.getTargetFlags() & 1);
break;
}
OutMI.addOperand(MCOp);
}
}
bool SparcAsmParser::expandSET(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions) {
MCOperand MCRegOp = Inst.getOperand(0);
MCOperand MCValOp = Inst.getOperand(1);
assert(MCRegOp.isReg());
assert(MCValOp.isImm() || MCValOp.isExpr());
// the imm operand can be either an expression or an immediate.
bool IsImm = Inst.getOperand(1).isImm();
int64_t RawImmValue = IsImm ? MCValOp.getImm() : 0;
// Allow either a signed or unsigned 32-bit immediate.
if (RawImmValue < -2147483648LL || RawImmValue > 4294967295LL) {
return Error(IDLoc,
"set: argument must be between -2147483648 and 4294967295");
}
// If the value was expressed as a large unsigned number, that's ok.
// We want to see if it "looks like" a small signed number.
int32_t ImmValue = RawImmValue;
// For 'set' you can't use 'or' with a negative operand on V9 because
// that would splat the sign bit across the upper half of the destination
// register, whereas 'set' is defined to zero the high 32 bits.
bool IsEffectivelyImm13 =
IsImm && ((is64Bit() ? 0 : -4096) <= ImmValue && ImmValue < 4096);
const MCExpr *ValExpr;
if (IsImm)
ValExpr = MCConstantExpr::create(ImmValue, getContext());
else
ValExpr = MCValOp.getExpr();
MCOperand PrevReg = MCOperand::createReg(Sparc::G0);
// If not just a signed imm13 value, then either we use a 'sethi' with a
// following 'or', or a 'sethi' by itself if there are no more 1 bits.
// In either case, start with the 'sethi'.
if (!IsEffectivelyImm13) {
MCInst TmpInst;
const MCExpr *Expr = adjustPICRelocation(SparcMCExpr::VK_Sparc_HI, ValExpr);
TmpInst.setLoc(IDLoc);
TmpInst.setOpcode(SP::SETHIi);
TmpInst.addOperand(MCRegOp);
TmpInst.addOperand(MCOperand::createExpr(Expr));
Instructions.push_back(TmpInst);
PrevReg = MCRegOp;
}
// The low bits require touching in 3 cases:
// * A non-immediate value will always require both instructions.
// * An effectively imm13 value needs only an 'or' instruction.
// * Otherwise, an immediate that is not effectively imm13 requires the
// 'or' only if bits remain after clearing the 22 bits that 'sethi' set.
// If the low bits are known zeros, there's nothing to do.
// In the second case, and only in that case, must we NOT clear
// bits of the immediate value via the %lo() assembler function.
// Note also, the 'or' instruction doesn't mind a large value in the case
// where the operand to 'set' was 0xFFFFFzzz - it does exactly what you mean.
if (!IsImm || IsEffectivelyImm13 || (ImmValue & 0x3ff)) {
MCInst TmpInst;
const MCExpr *Expr;
if (IsEffectivelyImm13)
Expr = ValExpr;
else
Expr = adjustPICRelocation(SparcMCExpr::VK_Sparc_LO, ValExpr);
TmpInst.setLoc(IDLoc);
TmpInst.setOpcode(SP::ORri);
TmpInst.addOperand(MCRegOp);
TmpInst.addOperand(PrevReg);
TmpInst.addOperand(MCOperand::createExpr(Expr));
Instructions.push_back(TmpInst);
}
return false;
}
/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
void Thumb2InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
NopInst.setOpcode(ARM::tHINT);
NopInst.addOperand(MCOperand::createImm(0));
NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
NopInst.addOperand(MCOperand::createReg(0));
}
bool X86ATTAsmParser::
MatchAndEmitInstruction(SMLoc IDLoc,
SmallVectorImpl<MCParsedAsmOperand*> &Operands,
MCStreamer &Out) {
assert(!Operands.empty() && "Unexpect empty operand list!");
X86Operand *Op = static_cast<X86Operand*>(Operands[0]);
assert(Op->isToken() && "Leading operand should always be a mnemonic!");
// First, handle aliases that expand to multiple instructions.
// FIXME: This should be replaced with a real .td file alias mechanism.
// Also, MatchInstructionImpl should do actually *do* the EmitInstruction
// call.
if (Op->getToken() == "fstsw" || Op->getToken() == "fstcw" ||
Op->getToken() == "fstsww" || Op->getToken() == "fstcww" ||
Op->getToken() == "finit" || Op->getToken() == "fsave" ||
Op->getToken() == "fstenv" || Op->getToken() == "fclex") {
MCInst Inst;
Inst.setOpcode(X86::WAIT);
Out.EmitInstruction(Inst);
const char *Repl =
StringSwitch<const char*>(Op->getToken())
.Case("finit", "fninit")
.Case("fsave", "fnsave")
.Case("fstcw", "fnstcw")
.Case("fstcww", "fnstcw")
.Case("fstenv", "fnstenv")
.Case("fstsw", "fnstsw")
.Case("fstsww", "fnstsw")
.Case("fclex", "fnclex")
.Default(0);
assert(Repl && "Unknown wait-prefixed instruction");
delete Operands[0];
Operands[0] = X86Operand::CreateToken(Repl, IDLoc);
}
bool WasOriginallyInvalidOperand = false;
unsigned OrigErrorInfo;
MCInst Inst;
// First, try a direct match.
switch (MatchInstructionImpl(Operands, Inst, OrigErrorInfo)) {
case Match_Success:
Out.EmitInstruction(Inst);
return false;
case Match_MissingFeature:
Error(IDLoc, "instruction requires a CPU feature not currently enabled");
return true;
case Match_ConversionFail:
return Error(IDLoc, "unable to convert operands to instruction");
case Match_InvalidOperand:
WasOriginallyInvalidOperand = true;
break;
case Match_MnemonicFail:
break;
}
// FIXME: Ideally, we would only attempt suffix matches for things which are
// valid prefixes, and we could just infer the right unambiguous
// type. However, that requires substantially more matcher support than the
// following hack.
// Change the operand to point to a temporary token.
StringRef Base = Op->getToken();
SmallString<16> Tmp;
Tmp += Base;
Tmp += ' ';
Op->setTokenValue(Tmp.str());
// If this instruction starts with an 'f', then it is a floating point stack
// instruction. These come in up to three forms for 32-bit, 64-bit, and
// 80-bit floating point, which use the suffixes s,l,t respectively.
//
// Otherwise, we assume that this may be an integer instruction, which comes
// in 8/16/32/64-bit forms using the b,w,l,q suffixes respectively.
const char *Suffixes = Base[0] != 'f' ? "bwlq" : "slt\0";
// Check for the various suffix matches.
Tmp[Base.size()] = Suffixes[0];
unsigned ErrorInfoIgnore;
MatchResultTy Match1, Match2, Match3, Match4;
Match1 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
Tmp[Base.size()] = Suffixes[1];
Match2 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
Tmp[Base.size()] = Suffixes[2];
Match3 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
Tmp[Base.size()] = Suffixes[3];
Match4 = MatchInstructionImpl(Operands, Inst, ErrorInfoIgnore);
// Restore the old token.
Op->setTokenValue(Base);
// If exactly one matched, then we treat that as a successful match (and the
// instruction will already have been filled in correctly, since the failing
// matches won't have modified it).
unsigned NumSuccessfulMatches =
(Match1 == Match_Success) + (Match2 == Match_Success) +
(Match3 == Match_Success) + (Match4 == Match_Success);
if (NumSuccessfulMatches == 1) {
Out.EmitInstruction(Inst);
return false;
}
// Otherwise, the match failed, try to produce a decent error message.
// If we had multiple suffix matches, then identify this as an ambiguous
// match.
if (NumSuccessfulMatches > 1) {
char MatchChars[4];
unsigned NumMatches = 0;
if (Match1 == Match_Success) MatchChars[NumMatches++] = Suffixes[0];
if (Match2 == Match_Success) MatchChars[NumMatches++] = Suffixes[1];
if (Match3 == Match_Success) MatchChars[NumMatches++] = Suffixes[2];
if (Match4 == Match_Success) MatchChars[NumMatches++] = Suffixes[3];
SmallString<126> Msg;
raw_svector_ostream OS(Msg);
OS << "ambiguous instructions require an explicit suffix (could be ";
for (unsigned i = 0; i != NumMatches; ++i) {
if (i != 0)
OS << ", ";
if (i + 1 == NumMatches)
OS << "or ";
OS << "'" << Base << MatchChars[i] << "'";
}
OS << ")";
Error(IDLoc, OS.str());
return true;
}
// Okay, we know that none of the variants matched successfully.
// If all of the instructions reported an invalid mnemonic, then the original
// mnemonic was invalid.
if ((Match1 == Match_MnemonicFail) && (Match2 == Match_MnemonicFail) &&
(Match3 == Match_MnemonicFail) && (Match4 == Match_MnemonicFail)) {
if (!WasOriginallyInvalidOperand) {
Error(IDLoc, "invalid instruction mnemonic '" + Base + "'");
return true;
}
// Recover location info for the operand if we know which was the problem.
SMLoc ErrorLoc = IDLoc;
if (OrigErrorInfo != ~0U) {
if (OrigErrorInfo >= Operands.size())
return Error(IDLoc, "too few operands for instruction");
ErrorLoc = ((X86Operand*)Operands[OrigErrorInfo])->getStartLoc();
if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
}
return Error(ErrorLoc, "invalid operand for instruction");
}
// If one instruction matched with a missing feature, report this as a
// missing feature.
if ((Match1 == Match_MissingFeature) + (Match2 == Match_MissingFeature) +
(Match3 == Match_MissingFeature) + (Match4 == Match_MissingFeature) == 1){
Error(IDLoc, "instruction requires a CPU feature not currently enabled");
return true;
}
// If one instruction matched with an invalid operand, report this as an
// operand failure.
if ((Match1 == Match_InvalidOperand) + (Match2 == Match_InvalidOperand) +
(Match3 == Match_InvalidOperand) + (Match4 == Match_InvalidOperand) == 1){
Error(IDLoc, "invalid operand for instruction");
return true;
}
// If all of these were an outright failure, report it in a useless way.
// FIXME: We should give nicer diagnostics about the exact failure.
Error(IDLoc, "unknown use of instruction mnemonic without a size suffix");
return true;
}
/// EmitInstruction -- Print out a single PowerPC MI in Darwin syntax to
/// the current output stream.
///
void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
MCInst TmpInst;
// Lower multi-instruction pseudo operations.
switch (MI->getOpcode()) {
default: break;
case TargetOpcode::DBG_VALUE: {
if (!isVerbose() || !OutStreamer.hasRawTextSupport()) return;
SmallString<32> Str;
raw_svector_ostream O(Str);
unsigned NOps = MI->getNumOperands();
assert(NOps==4);
O << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
// cast away const; DIetc do not take const operands for some reason.
DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps-1).getMetadata()));
O << V.getName();
O << " <- ";
// Frame address. Currently handles register +- offset only.
assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
O << '['; printOperand(MI, 0, O); O << '+'; printOperand(MI, 1, O);
O << ']';
O << "+";
printOperand(MI, NOps-2, O);
OutStreamer.EmitRawText(O.str());
return;
}
case PPC::MovePCtoLR:
case PPC::MovePCtoLR8: {
// Transform %LR = MovePCtoLR
// Into this, where the label is the PIC base:
// bl L1$pb
// L1$pb:
MCSymbol *PICBase = MF->getPICBaseSymbol();
// Emit the 'bl'.
TmpInst.setOpcode(PPC::BL_Darwin); // Darwin vs SVR4 doesn't matter here.
// FIXME: We would like an efficient form for this, so we don't have to do
// a lot of extra uniquing.
TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::
Create(PICBase, OutContext)));
OutStreamer.EmitInstruction(TmpInst);
// Emit the label.
OutStreamer.EmitLabel(PICBase);
return;
}
case PPC::LDtoc: {
// Transform %X3 = LDtoc <ga:@min1>, %X2
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());
// Change the opcode to LD, and the global address operand to be a
// reference to the TOC entry we will synthesize later.
TmpInst.setOpcode(PPC::LD);
const MachineOperand &MO = MI->getOperand(1);
assert(MO.isGlobal());
// Map symbol -> label of TOC entry.
MCSymbol *&TOCEntry = TOC[Mang->getSymbol(MO.getGlobal())];
if (TOCEntry == 0)
TOCEntry = GetTempSymbol("C", TOCLabelID++);
const MCExpr *Exp =
MCSymbolRefExpr::Create(TOCEntry, MCSymbolRefExpr::VK_PPC_TOC,
OutContext);
TmpInst.getOperand(1) = MCOperand::CreateExpr(Exp);
OutStreamer.EmitInstruction(TmpInst);
return;
}
case PPC::MFCRpseud:
// Transform: %R3 = MFCRpseud %CR7
// Into: %R3 = MFCR ;; cr7
OutStreamer.AddComment(PPCInstPrinter::
getRegisterName(MI->getOperand(1).getReg()));
TmpInst.setOpcode(PPC::MFCR);
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
OutStreamer.EmitInstruction(TmpInst);
return;
}
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());
OutStreamer.EmitInstruction(TmpInst);
}
MCInst HexagonMCInstrInfo::deriveSubInst(MCInst const &Inst) {
MCInst Result;
bool Absolute;
int64_t Value;
switch (Inst.getOpcode()) {
default:
// dbgs() << "opcode: "<< Inst->getOpcode() << "\n";
llvm_unreachable("Unimplemented subinstruction \n");
break;
case Hexagon::A2_addi:
Absolute = Inst.getOperand(2).getExpr()->evaluateAsAbsolute(Value);
if (Absolute) {
if (Value == 1) {
Result.setOpcode(Hexagon::SA1_inc);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break;
} // 1,2 SUBInst $Rd = add($Rs, #1)
if (Value == -1) {
Result.setOpcode(Hexagon::SA1_dec);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break;
} // 1,2 SUBInst $Rd = add($Rs,#-1)
if (Inst.getOperand(1).getReg() == Hexagon::R29) {
Result.setOpcode(Hexagon::SA1_addsp);
addOps(Result, Inst, 0);
addOps(Result, Inst, 2);
break;
} // 1,3 SUBInst $Rd = add(r29, #$u6_2)
}
Result.setOpcode(Hexagon::SA1_addi);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 1,2,3 SUBInst $Rx = add($Rx, #$s7)
case Hexagon::A2_add:
Result.setOpcode(Hexagon::SA1_addrx);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 1,2,3 SUBInst $Rx = add($_src_, $Rs)
case Hexagon::S2_allocframe:
Result.setOpcode(Hexagon::SS2_allocframe);
addOps(Result, Inst, 0);
break; // 1 SUBInst allocframe(#$u5_3)
case Hexagon::A2_andir:
if (minConstant(Inst, 2) == 255) {
Result.setOpcode(Hexagon::SA1_zxtb);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 1,2 $Rd = and($Rs, #255)
} else {
Result.setOpcode(Hexagon::SA1_and1);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 1,2 SUBInst $Rd = and($Rs, #1)
}
case Hexagon::C2_cmpeqi:
Result.setOpcode(Hexagon::SA1_cmpeqi);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 2,3 SUBInst p0 = cmp.eq($Rs, #$u2)
case Hexagon::A4_combineii:
case Hexagon::A2_combineii:
Absolute = Inst.getOperand(1).getExpr()->evaluateAsAbsolute(Value);
assert(Absolute);(void)Absolute;
if (Value == 1) {
Result.setOpcode(Hexagon::SA1_combine1i);
addOps(Result, Inst, 0);
addOps(Result, Inst, 2);
break; // 1,3 SUBInst $Rdd = combine(#1, #$u2)
}
if (Value == 3) {
Result.setOpcode(Hexagon::SA1_combine3i);
addOps(Result, Inst, 0);
addOps(Result, Inst, 2);
break; // 1,3 SUBInst $Rdd = combine(#3, #$u2)
}
if (Value == 0) {
Result.setOpcode(Hexagon::SA1_combine0i);
addOps(Result, Inst, 0);
addOps(Result, Inst, 2);
break; // 1,3 SUBInst $Rdd = combine(#0, #$u2)
}
if (Value == 2) {
Result.setOpcode(Hexagon::SA1_combine2i);
addOps(Result, Inst, 0);
addOps(Result, Inst, 2);
break; // 1,3 SUBInst $Rdd = combine(#2, #$u2)
}
case Hexagon::A4_combineir:
Result.setOpcode(Hexagon::SA1_combinezr);
addOps(Result, Inst, 0);
addOps(Result, Inst, 2);
break; // 1,3 SUBInst $Rdd = combine(#0, $Rs)
case Hexagon::A4_combineri:
Result.setOpcode(Hexagon::SA1_combinerz);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 1,2 SUBInst $Rdd = combine($Rs, #0)
case Hexagon::L4_return_tnew_pnt:
case Hexagon::L4_return_tnew_pt:
Result.setOpcode(Hexagon::SL2_return_tnew);
break; // none SUBInst if (p0.new) dealloc_return:nt
case Hexagon::L4_return_fnew_pnt:
case Hexagon::L4_return_fnew_pt:
Result.setOpcode(Hexagon::SL2_return_fnew);
break; // none SUBInst if (!p0.new) dealloc_return:nt
case Hexagon::L4_return_f:
Result.setOpcode(Hexagon::SL2_return_f);
break; // none SUBInst if (!p0) dealloc_return
case Hexagon::L4_return_t:
Result.setOpcode(Hexagon::SL2_return_t);
break; // none SUBInst if (p0) dealloc_return
case Hexagon::L4_return:
Result.setOpcode(Hexagon::SL2_return);
break; // none SUBInst dealloc_return
case Hexagon::L2_deallocframe:
Result.setOpcode(Hexagon::SL2_deallocframe);
break; // none SUBInst deallocframe
case Hexagon::EH_RETURN_JMPR:
case Hexagon::J2_jumpr:
case Hexagon::PS_jmpret:
Result.setOpcode(Hexagon::SL2_jumpr31);
break; // none SUBInst jumpr r31
case Hexagon::J2_jumprf:
case Hexagon::PS_jmpretf:
Result.setOpcode(Hexagon::SL2_jumpr31_f);
break; // none SUBInst if (!p0) jumpr r31
case Hexagon::J2_jumprfnew:
case Hexagon::J2_jumprfnewpt:
case Hexagon::PS_jmpretfnewpt:
case Hexagon::PS_jmpretfnew:
Result.setOpcode(Hexagon::SL2_jumpr31_fnew);
break; // none SUBInst if (!p0.new) jumpr:nt r31
case Hexagon::J2_jumprt:
case Hexagon::PS_jmprett:
Result.setOpcode(Hexagon::SL2_jumpr31_t);
break; // none SUBInst if (p0) jumpr r31
case Hexagon::J2_jumprtnew:
case Hexagon::J2_jumprtnewpt:
case Hexagon::PS_jmprettnewpt:
case Hexagon::PS_jmprettnew:
Result.setOpcode(Hexagon::SL2_jumpr31_tnew);
break; // none SUBInst if (p0.new) jumpr:nt r31
case Hexagon::L2_loadrb_io:
Result.setOpcode(Hexagon::SL2_loadrb_io);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 1,2,3 SUBInst $Rd = memb($Rs + #$u3_0)
case Hexagon::L2_loadrd_io:
Result.setOpcode(Hexagon::SL2_loadrd_sp);
addOps(Result, Inst, 0);
addOps(Result, Inst, 2);
break; // 1,3 SUBInst $Rdd = memd(r29 + #$u5_3)
case Hexagon::L2_loadrh_io:
Result.setOpcode(Hexagon::SL2_loadrh_io);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 1,2,3 SUBInst $Rd = memh($Rs + #$u3_1)
case Hexagon::L2_loadrub_io:
Result.setOpcode(Hexagon::SL1_loadrub_io);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 1,2,3 SUBInst $Rd = memub($Rs + #$u4_0)
case Hexagon::L2_loadruh_io:
Result.setOpcode(Hexagon::SL2_loadruh_io);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 1,2,3 SUBInst $Rd = memuh($Rs + #$u3_1)
case Hexagon::L2_loadri_io:
if (Inst.getOperand(1).getReg() == Hexagon::R29) {
Result.setOpcode(Hexagon::SL2_loadri_sp);
addOps(Result, Inst, 0);
addOps(Result, Inst, 2);
break; // 2 1,3 SUBInst $Rd = memw(r29 + #$u5_2)
} else {
Result.setOpcode(Hexagon::SL1_loadri_io);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 1,2,3 SUBInst $Rd = memw($Rs + #$u4_2)
}
case Hexagon::S4_storeirb_io:
Absolute = Inst.getOperand(2).getExpr()->evaluateAsAbsolute(Value);
assert(Absolute);(void)Absolute;
if (Value == 0) {
Result.setOpcode(Hexagon::SS2_storebi0);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 1,2 SUBInst memb($Rs + #$u4_0)=#0
} else if (Value == 1) {
Result.setOpcode(Hexagon::SS2_storebi1);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 2 1,2 SUBInst memb($Rs + #$u4_0)=#1
}
case Hexagon::S2_storerb_io:
Result.setOpcode(Hexagon::SS1_storeb_io);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 1,2,3 SUBInst memb($Rs + #$u4_0) = $Rt
case Hexagon::S2_storerd_io:
Result.setOpcode(Hexagon::SS2_stored_sp);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 2,3 SUBInst memd(r29 + #$s6_3) = $Rtt
case Hexagon::S2_storerh_io:
Result.setOpcode(Hexagon::SS2_storeh_io);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 1,2,3 SUBInst memb($Rs + #$u4_0) = $Rt
case Hexagon::S4_storeiri_io:
Absolute = Inst.getOperand(2).getExpr()->evaluateAsAbsolute(Value);
assert(Absolute);(void)Absolute;
if (Value == 0) {
Result.setOpcode(Hexagon::SS2_storewi0);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 3 1,2 SUBInst memw($Rs + #$u4_2)=#0
} else if (Value == 1) {
Result.setOpcode(Hexagon::SS2_storewi1);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 3 1,2 SUBInst memw($Rs + #$u4_2)=#1
} else if (Inst.getOperand(0).getReg() == Hexagon::R29) {
Result.setOpcode(Hexagon::SS2_storew_sp);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2);
break; // 1 2,3 SUBInst memw(r29 + #$u5_2) = $Rt
}
case Hexagon::S2_storeri_io:
if (Inst.getOperand(0).getReg() == Hexagon::R29) {
Result.setOpcode(Hexagon::SS2_storew_sp);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2); // 1,2,3 SUBInst memw(sp + #$u5_2) = $Rt
} else {
Result.setOpcode(Hexagon::SS1_storew_io);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
addOps(Result, Inst, 2); // 1,2,3 SUBInst memw($Rs + #$u4_2) = $Rt
}
break;
case Hexagon::A2_sxtb:
Result.setOpcode(Hexagon::SA1_sxtb);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 1,2 SUBInst $Rd = sxtb($Rs)
case Hexagon::A2_sxth:
Result.setOpcode(Hexagon::SA1_sxth);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 1,2 SUBInst $Rd = sxth($Rs)
case Hexagon::A2_tfr:
Result.setOpcode(Hexagon::SA1_tfr);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 1,2 SUBInst $Rd = $Rs
case Hexagon::C2_cmovenewif:
Result.setOpcode(Hexagon::SA1_clrfnew);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 2 SUBInst if (!p0.new) $Rd = #0
case Hexagon::C2_cmovenewit:
Result.setOpcode(Hexagon::SA1_clrtnew);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 2 SUBInst if (p0.new) $Rd = #0
case Hexagon::C2_cmoveif:
Result.setOpcode(Hexagon::SA1_clrf);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 2 SUBInst if (!p0) $Rd = #0
case Hexagon::C2_cmoveit:
Result.setOpcode(Hexagon::SA1_clrt);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 2 SUBInst if (p0) $Rd = #0
case Hexagon::A2_tfrsi:
Absolute = Inst.getOperand(1).getExpr()->evaluateAsAbsolute(Value);
if (Absolute && Value == -1) {
Result.setOpcode(Hexagon::SA1_setin1);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 2 1 SUBInst $Rd = #-1
} else {
Result.setOpcode(Hexagon::SA1_seti);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 1,2 SUBInst $Rd = #$u6
}
case Hexagon::A2_zxtb:
Result.setOpcode(Hexagon::SA1_zxtb);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 1,2 $Rd = and($Rs, #255)
case Hexagon::A2_zxth:
Result.setOpcode(Hexagon::SA1_zxth);
addOps(Result, Inst, 0);
addOps(Result, Inst, 1);
break; // 1,2 SUBInst $Rd = zxth($Rs)
}
return Result;
}
/// LowerSubReg32_Op0 - Things like MOVZX16rr8 -> MOVZX32rr8.
static void LowerSubReg32_Op0(MCInst &OutMI, unsigned NewOpc) {
OutMI.setOpcode(NewOpc);
lower_subreg32(&OutMI, 0);
}
void MipsAsmPrinter::EmitInstrReg(unsigned Opcode, unsigned Reg) {
MCInst I;
I.setOpcode(Opcode);
I.addOperand(MCOperand::CreateReg(Reg));
OutStreamer.EmitInstruction(I, getSubtargetInfo());
}
/// LowerUnaryToTwoAddr - R = setb -> R = sbb R, R
static void LowerUnaryToTwoAddr(MCInst &OutMI, unsigned NewOpc) {
OutMI.setOpcode(NewOpc);
OutMI.addOperand(OutMI.getOperand(0));
OutMI.addOperand(OutMI.getOperand(0));
}
void AArch64AsmPrinter::EmitInstruction(const MachineInstr *MI) {
// Do any auto-generated pseudo lowerings.
if (emitPseudoExpansionLowering(OutStreamer, MI))
return;
if (AArch64FI->getLOHRelated().count(MI)) {
// Generate a label for LOH related instruction
MCSymbol *LOHLabel = GetTempSymbol("loh", LOHLabelCounter++);
// Associate the instruction with the label
LOHInstToLabel[MI] = LOHLabel;
OutStreamer.EmitLabel(LOHLabel);
}
// Do any manual lowerings.
switch (MI->getOpcode()) {
default:
break;
case AArch64::DBG_VALUE: {
if (isVerbose() && OutStreamer.hasRawTextSupport()) {
SmallString<128> TmpStr;
raw_svector_ostream OS(TmpStr);
PrintDebugValueComment(MI, OS);
OutStreamer.EmitRawText(StringRef(OS.str()));
}
return;
}
// Tail calls use pseudo instructions so they have the proper code-gen
// attributes (isCall, isReturn, etc.). We lower them to the real
// instruction here.
case AArch64::TCRETURNri: {
MCInst TmpInst;
TmpInst.setOpcode(AArch64::BR);
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
EmitToStreamer(OutStreamer, TmpInst);
return;
}
case AArch64::TCRETURNdi: {
MCOperand Dest;
MCInstLowering.lowerOperand(MI->getOperand(0), Dest);
MCInst TmpInst;
TmpInst.setOpcode(AArch64::B);
TmpInst.addOperand(Dest);
EmitToStreamer(OutStreamer, TmpInst);
return;
}
case AArch64::TLSDESC_BLR: {
MCOperand Callee, Sym;
MCInstLowering.lowerOperand(MI->getOperand(0), Callee);
MCInstLowering.lowerOperand(MI->getOperand(1), Sym);
// First emit a relocation-annotation. This expands to no code, but requests
// the following instruction gets an R_AARCH64_TLSDESC_CALL.
MCInst TLSDescCall;
TLSDescCall.setOpcode(AArch64::TLSDESCCALL);
TLSDescCall.addOperand(Sym);
EmitToStreamer(OutStreamer, TLSDescCall);
// Other than that it's just a normal indirect call to the function loaded
// from the descriptor.
MCInst BLR;
BLR.setOpcode(AArch64::BLR);
BLR.addOperand(Callee);
EmitToStreamer(OutStreamer, BLR);
return;
}
case TargetOpcode::STACKMAP:
return LowerSTACKMAP(OutStreamer, SM, *MI);
case TargetOpcode::PATCHPOINT:
return LowerPATCHPOINT(OutStreamer, SM, *MI);
}
// Finally, do the automated lowerings for everything else.
MCInst TmpInst;
MCInstLowering.Lower(MI, TmpInst);
EmitToStreamer(OutStreamer, TmpInst);
}
void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const {
OutMI.setOpcode(MI->getOpcode());
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
MCOperand MCOp;
switch (MO.getType()) {
default:
MI->dump();
llvm_unreachable("unknown operand type");
case MachineOperand::MO_Register:
// Ignore all implicit register operands.
if (MO.isImplicit()) continue;
MCOp = MCOperand::CreateReg(MO.getReg());
break;
case MachineOperand::MO_Immediate:
MCOp = MCOperand::CreateImm(MO.getImm());
break;
case MachineOperand::MO_MachineBasicBlock:
MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
MO.getMBB()->getSymbol(), Ctx));
break;
case MachineOperand::MO_GlobalAddress:
MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
break;
case MachineOperand::MO_ExternalSymbol:
MCOp = LowerSymbolOperand(MO, GetSymbolFromOperand(MO));
break;
case MachineOperand::MO_JumpTableIndex:
MCOp = LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
break;
case MachineOperand::MO_ConstantPoolIndex:
MCOp = LowerSymbolOperand(MO, AsmPrinter.GetCPISymbol(MO.getIndex()));
break;
case MachineOperand::MO_BlockAddress:
MCOp = LowerSymbolOperand(MO,
AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress()));
break;
}
OutMI.addOperand(MCOp);
}
// Handle a few special cases to eliminate operand modifiers.
switch (OutMI.getOpcode()) {
case X86::LEA64_32r: // Handle 'subreg rewriting' for the lea64_32mem operand.
lower_lea64_32mem(&OutMI, 1);
break;
case X86::MOVZX16rr8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr8); break;
case X86::MOVZX16rm8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break;
case X86::MOVSX16rr8: LowerSubReg32_Op0(OutMI, X86::MOVSX32rr8); break;
case X86::MOVSX16rm8: LowerSubReg32_Op0(OutMI, X86::MOVSX32rm8); break;
case X86::MOVZX64rr32: LowerSubReg32_Op0(OutMI, X86::MOV32rr); break;
case X86::MOVZX64rm32: LowerSubReg32_Op0(OutMI, X86::MOV32rm); break;
case X86::MOV64ri64i32: LowerSubReg32_Op0(OutMI, X86::MOV32ri); break;
case X86::MOVZX64rr8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr8); break;
case X86::MOVZX64rm8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break;
case X86::MOVZX64rr16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr16); break;
case X86::MOVZX64rm16: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm16); break;
case X86::SETB_C8r: LowerUnaryToTwoAddr(OutMI, X86::SBB8rr); break;
case X86::SETB_C16r: LowerUnaryToTwoAddr(OutMI, X86::SBB16rr); break;
case X86::SETB_C32r: LowerUnaryToTwoAddr(OutMI, X86::SBB32rr); break;
case X86::SETB_C64r: LowerUnaryToTwoAddr(OutMI, X86::SBB64rr); break;
case X86::MOV8r0: LowerUnaryToTwoAddr(OutMI, X86::XOR8rr); break;
case X86::MOV32r0: LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); break;
case X86::MMX_V_SET0: LowerUnaryToTwoAddr(OutMI, X86::MMX_PXORrr); break;
case X86::MMX_V_SETALLONES:
LowerUnaryToTwoAddr(OutMI, X86::MMX_PCMPEQDrr); break;
case X86::FsFLD0SS: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
case X86::FsFLD0SD: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
case X86::V_SET0PS: LowerUnaryToTwoAddr(OutMI, X86::XORPSrr); break;
case X86::V_SET0PD: LowerUnaryToTwoAddr(OutMI, X86::XORPDrr); break;
case X86::V_SET0PI: LowerUnaryToTwoAddr(OutMI, X86::PXORrr); break;
case X86::V_SETALLONES: LowerUnaryToTwoAddr(OutMI, X86::PCMPEQDrr); break;
case X86::MOV16r0:
LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV16r0 -> MOV32r0
LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
break;
case X86::MOV64r0:
LowerSubReg32_Op0(OutMI, X86::MOV32r0); // MOV64r0 -> MOV32r0
LowerUnaryToTwoAddr(OutMI, X86::XOR32rr); // MOV32r0 -> XOR32rr
break;
// TAILJMPr, TAILJMPr64, CALL64r, CALL64pcrel32 - These instructions have
// register inputs modeled as normal uses instead of implicit uses. As such,
// truncate off all but the first operand (the callee). FIXME: Change isel.
case X86::TAILJMPr:
case X86::TAILJMPr64:
case X86::CALL64r:
case X86::CALL64pcrel32: {
unsigned Opcode = OutMI.getOpcode();
MCOperand Saved = OutMI.getOperand(0);
OutMI = MCInst();
OutMI.setOpcode(Opcode);
OutMI.addOperand(Saved);
break;
}
// TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions.
case X86::TAILJMPd:
case X86::TAILJMPd64: {
MCOperand Saved = OutMI.getOperand(0);
OutMI = MCInst();
OutMI.setOpcode(X86::TAILJMP_1);
OutMI.addOperand(Saved);
break;
}
// The assembler backend wants to see branches in their small form and relax
// them to their large form. The JIT can only handle the large form because
// it does not do relaxation. For now, translate the large form to the
// small one here.
case X86::JMP_4: OutMI.setOpcode(X86::JMP_1); break;
case X86::JO_4: OutMI.setOpcode(X86::JO_1); break;
case X86::JNO_4: OutMI.setOpcode(X86::JNO_1); break;
case X86::JB_4: OutMI.setOpcode(X86::JB_1); break;
case X86::JAE_4: OutMI.setOpcode(X86::JAE_1); break;
case X86::JE_4: OutMI.setOpcode(X86::JE_1); break;
case X86::JNE_4: OutMI.setOpcode(X86::JNE_1); break;
case X86::JBE_4: OutMI.setOpcode(X86::JBE_1); break;
case X86::JA_4: OutMI.setOpcode(X86::JA_1); break;
case X86::JS_4: OutMI.setOpcode(X86::JS_1); break;
case X86::JNS_4: OutMI.setOpcode(X86::JNS_1); break;
case X86::JP_4: OutMI.setOpcode(X86::JP_1); break;
case X86::JNP_4: OutMI.setOpcode(X86::JNP_1); break;
case X86::JL_4: OutMI.setOpcode(X86::JL_1); break;
case X86::JGE_4: OutMI.setOpcode(X86::JGE_1); break;
case X86::JLE_4: OutMI.setOpcode(X86::JLE_1); break;
case X86::JG_4: OutMI.setOpcode(X86::JG_1); break;
// We don't currently select the correct instruction form for instructions
// which have a short %eax, etc. form. Handle this by custom lowering, for
// now.
//
// Note, we are currently not handling the following instructions:
// MOV64ao8, MOV64o8a
// XCHG16ar, XCHG32ar, XCHG64ar
case X86::MOV8mr_NOREX:
case X86::MOV8mr: SimplifyShortMoveForm(OutMI, X86::MOV8ao8); break;
case X86::MOV8rm_NOREX:
case X86::MOV8rm: SimplifyShortMoveForm(OutMI, X86::MOV8o8a); break;
case X86::MOV16mr: SimplifyShortMoveForm(OutMI, X86::MOV16ao16); break;
case X86::MOV16rm: SimplifyShortMoveForm(OutMI, X86::MOV16o16a); break;
case X86::MOV32mr: SimplifyShortMoveForm(OutMI, X86::MOV32ao32); break;
case X86::MOV32rm: SimplifyShortMoveForm(OutMI, X86::MOV32o32a); break;
case X86::MOV64mr: SimplifyShortMoveForm(OutMI, X86::MOV64ao64); break;
case X86::MOV64rm: SimplifyShortMoveForm(OutMI, X86::MOV64o64a); break;
case X86::ADC8ri: SimplifyShortImmForm(OutMI, X86::ADC8i8); break;
case X86::ADC16ri: SimplifyShortImmForm(OutMI, X86::ADC16i16); break;
case X86::ADC32ri: SimplifyShortImmForm(OutMI, X86::ADC32i32); break;
case X86::ADC64ri32: SimplifyShortImmForm(OutMI, X86::ADC64i32); break;
case X86::ADD8ri: SimplifyShortImmForm(OutMI, X86::ADD8i8); break;
case X86::ADD16ri: SimplifyShortImmForm(OutMI, X86::ADD16i16); break;
case X86::ADD32ri: SimplifyShortImmForm(OutMI, X86::ADD32i32); break;
case X86::ADD64ri32: SimplifyShortImmForm(OutMI, X86::ADD64i32); break;
case X86::AND8ri: SimplifyShortImmForm(OutMI, X86::AND8i8); break;
case X86::AND16ri: SimplifyShortImmForm(OutMI, X86::AND16i16); break;
case X86::AND32ri: SimplifyShortImmForm(OutMI, X86::AND32i32); break;
case X86::AND64ri32: SimplifyShortImmForm(OutMI, X86::AND64i32); break;
case X86::CMP8ri: SimplifyShortImmForm(OutMI, X86::CMP8i8); break;
case X86::CMP16ri: SimplifyShortImmForm(OutMI, X86::CMP16i16); break;
case X86::CMP32ri: SimplifyShortImmForm(OutMI, X86::CMP32i32); break;
case X86::CMP64ri32: SimplifyShortImmForm(OutMI, X86::CMP64i32); break;
case X86::OR8ri: SimplifyShortImmForm(OutMI, X86::OR8i8); break;
case X86::OR16ri: SimplifyShortImmForm(OutMI, X86::OR16i16); break;
case X86::OR32ri: SimplifyShortImmForm(OutMI, X86::OR32i32); break;
case X86::OR64ri32: SimplifyShortImmForm(OutMI, X86::OR64i32); break;
case X86::SBB8ri: SimplifyShortImmForm(OutMI, X86::SBB8i8); break;
case X86::SBB16ri: SimplifyShortImmForm(OutMI, X86::SBB16i16); break;
case X86::SBB32ri: SimplifyShortImmForm(OutMI, X86::SBB32i32); break;
case X86::SBB64ri32: SimplifyShortImmForm(OutMI, X86::SBB64i32); break;
case X86::SUB8ri: SimplifyShortImmForm(OutMI, X86::SUB8i8); break;
case X86::SUB16ri: SimplifyShortImmForm(OutMI, X86::SUB16i16); break;
case X86::SUB32ri: SimplifyShortImmForm(OutMI, X86::SUB32i32); break;
case X86::SUB64ri32: SimplifyShortImmForm(OutMI, X86::SUB64i32); break;
case X86::TEST8ri: SimplifyShortImmForm(OutMI, X86::TEST8i8); break;
case X86::TEST16ri: SimplifyShortImmForm(OutMI, X86::TEST16i16); break;
case X86::TEST32ri: SimplifyShortImmForm(OutMI, X86::TEST32i32); break;
case X86::TEST64ri32: SimplifyShortImmForm(OutMI, X86::TEST64i32); break;
case X86::XOR8ri: SimplifyShortImmForm(OutMI, X86::XOR8i8); break;
case X86::XOR16ri: SimplifyShortImmForm(OutMI, X86::XOR16i16); break;
case X86::XOR32ri: SimplifyShortImmForm(OutMI, X86::XOR32i32); break;
case X86::XOR64ri32: SimplifyShortImmForm(OutMI, X86::XOR64i32); break;
}
}
void X86AsmPrinter::LowerTlsAddr(X86MCInstLower &MCInstLowering,
const MachineInstr &MI) {
bool is64Bits = MI.getOpcode() == X86::TLS_addr64 ||
MI.getOpcode() == X86::TLS_base_addr64;
bool needsPadding = MI.getOpcode() == X86::TLS_addr64;
MCContext &context = OutStreamer->getContext();
if (needsPadding)
EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
MCSymbolRefExpr::VariantKind SRVK;
switch (MI.getOpcode()) {
case X86::TLS_addr32:
case X86::TLS_addr64:
SRVK = MCSymbolRefExpr::VK_TLSGD;
break;
case X86::TLS_base_addr32:
SRVK = MCSymbolRefExpr::VK_TLSLDM;
break;
case X86::TLS_base_addr64:
SRVK = MCSymbolRefExpr::VK_TLSLD;
break;
default:
llvm_unreachable("unexpected opcode");
}
MCSymbol *sym = MCInstLowering.GetSymbolFromOperand(MI.getOperand(3));
const MCSymbolRefExpr *symRef = MCSymbolRefExpr::create(sym, SRVK, context);
MCInst LEA;
if (is64Bits) {
LEA.setOpcode(X86::LEA64r);
LEA.addOperand(MCOperand::createReg(X86::RDI)); // dest
LEA.addOperand(MCOperand::createReg(X86::RIP)); // base
LEA.addOperand(MCOperand::createImm(1)); // scale
LEA.addOperand(MCOperand::createReg(0)); // index
LEA.addOperand(MCOperand::createExpr(symRef)); // disp
LEA.addOperand(MCOperand::createReg(0)); // seg
} else if (SRVK == MCSymbolRefExpr::VK_TLSLDM) {
LEA.setOpcode(X86::LEA32r);
LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
LEA.addOperand(MCOperand::createReg(X86::EBX)); // base
LEA.addOperand(MCOperand::createImm(1)); // scale
LEA.addOperand(MCOperand::createReg(0)); // index
LEA.addOperand(MCOperand::createExpr(symRef)); // disp
LEA.addOperand(MCOperand::createReg(0)); // seg
} else {
LEA.setOpcode(X86::LEA32r);
LEA.addOperand(MCOperand::createReg(X86::EAX)); // dest
LEA.addOperand(MCOperand::createReg(0)); // base
LEA.addOperand(MCOperand::createImm(1)); // scale
LEA.addOperand(MCOperand::createReg(X86::EBX)); // index
LEA.addOperand(MCOperand::createExpr(symRef)); // disp
LEA.addOperand(MCOperand::createReg(0)); // seg
}
EmitAndCountInstruction(LEA);
if (needsPadding) {
EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
EmitAndCountInstruction(MCInstBuilder(X86::DATA16_PREFIX));
EmitAndCountInstruction(MCInstBuilder(X86::REX64_PREFIX));
}
StringRef name = is64Bits ? "__tls_get_addr" : "___tls_get_addr";
MCSymbol *tlsGetAddr = context.getOrCreateSymbol(name);
const MCSymbolRefExpr *tlsRef =
MCSymbolRefExpr::create(tlsGetAddr,
MCSymbolRefExpr::VK_PLT,
context);
EmitAndCountInstruction(MCInstBuilder(is64Bits ? X86::CALL64pcrel32
: X86::CALLpcrel32)
.addExpr(tlsRef));
}
void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
X86MCInstLower MCInstLowering(OutContext, Mang, *this);
switch (MI->getOpcode()) {
case TargetOpcode::DBG_VALUE:
if (isVerbose() && OutStreamer.hasRawTextSupport()) {
std::string TmpStr;
raw_string_ostream OS(TmpStr);
PrintDebugValueComment(MI, OS);
OutStreamer.EmitRawText(StringRef(OS.str()));
}
return;
case X86::MOVPC32r: {
MCInst TmpInst;
// This is a pseudo op for a two instruction sequence with a label, which
// looks like:
// call "L1$pb"
// "L1$pb":
// popl %esi
// Emit the call.
MCSymbol *PICBase = MCInstLowering.GetPICBaseSymbol();
TmpInst.setOpcode(X86::CALLpcrel32);
// FIXME: We would like an efficient form for this, so we don't have to do a
// lot of extra uniquing.
TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(PICBase,
OutContext)));
OutStreamer.EmitInstruction(TmpInst);
// Emit the label.
OutStreamer.EmitLabel(PICBase);
// popl $reg
TmpInst.setOpcode(X86::POP32r);
TmpInst.getOperand(0) = MCOperand::CreateReg(MI->getOperand(0).getReg());
OutStreamer.EmitInstruction(TmpInst);
return;
}
case X86::ADD32ri: {
// Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri.
if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS)
break;
// Okay, we have something like:
// EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL)
// For this, we want to print something like:
// MYGLOBAL + (. - PICBASE)
// However, we can't generate a ".", so just emit a new label here and refer
// to it.
MCSymbol *DotSym = OutContext.CreateTempSymbol();
OutStreamer.EmitLabel(DotSym);
// Now that we have emitted the label, lower the complex operand expression.
MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2));
const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
const MCExpr *PICBase =
MCSymbolRefExpr::Create(MCInstLowering.GetPICBaseSymbol(), OutContext);
DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext);
DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext),
DotExpr, OutContext);
MCInst TmpInst;
TmpInst.setOpcode(X86::ADD32ri);
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
TmpInst.addOperand(MCOperand::CreateExpr(DotExpr));
OutStreamer.EmitInstruction(TmpInst);
return;
}
}
MCInst TmpInst;
MCInstLowering.Lower(MI, TmpInst);
OutStreamer.EmitInstruction(TmpInst);
}
static DecodeStatus
Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
// Try and decode as a 3R instruction.
unsigned Opcode = fieldFromInstruction(Insn, 11, 5);
switch (Opcode) {
case 0x0:
Inst.setOpcode(XCore::STW_2rus);
return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
case 0x1:
Inst.setOpcode(XCore::LDW_2rus);
return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
case 0x2:
Inst.setOpcode(XCore::ADD_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x3:
Inst.setOpcode(XCore::SUB_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x4:
Inst.setOpcode(XCore::SHL_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x5:
Inst.setOpcode(XCore::SHR_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x6:
Inst.setOpcode(XCore::EQ_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x7:
Inst.setOpcode(XCore::AND_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x8:
Inst.setOpcode(XCore::OR_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x9:
Inst.setOpcode(XCore::LDW_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x10:
Inst.setOpcode(XCore::LD16S_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x11:
Inst.setOpcode(XCore::LD8U_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x12:
Inst.setOpcode(XCore::ADD_2rus);
return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
case 0x13:
Inst.setOpcode(XCore::SUB_2rus);
return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
case 0x14:
Inst.setOpcode(XCore::SHL_2rus);
return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
case 0x15:
Inst.setOpcode(XCore::SHR_2rus);
return Decode2RUSBitpInstruction(Inst, Insn, Address, Decoder);
case 0x16:
Inst.setOpcode(XCore::EQ_2rus);
return Decode2RUSInstruction(Inst, Insn, Address, Decoder);
case 0x17:
Inst.setOpcode(XCore::TSETR_3r);
return Decode3RImmInstruction(Inst, Insn, Address, Decoder);
case 0x18:
Inst.setOpcode(XCore::LSS_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
case 0x19:
Inst.setOpcode(XCore::LSU_3r);
return Decode3RInstruction(Inst, Insn, Address, Decoder);
}
return MCDisassembler::Fail;
}
MCDisassembler::DecodeStatus WebAssemblyDisassembler::getInstruction(
MCInst &MI, uint64_t &Size, ArrayRef<uint8_t> Bytes, uint64_t /*Address*/,
raw_ostream &OS, raw_ostream &CS) const {
Size = 0;
uint64_t Pos = 0;
// Read the opcode.
if (Pos + sizeof(uint64_t) > Bytes.size())
return MCDisassembler::Fail;
uint64_t Opcode = support::endian::read64le(Bytes.data() + Pos);
Pos += sizeof(uint64_t);
if (Opcode >= WebAssembly::INSTRUCTION_LIST_END)
return MCDisassembler::Fail;
MI.setOpcode(Opcode);
const MCInstrDesc &Desc = MCII->get(Opcode);
unsigned NumFixedOperands = Desc.NumOperands;
// If it's variadic, read the number of extra operands.
unsigned NumExtraOperands = 0;
if (Desc.isVariadic()) {
if (Pos + sizeof(uint64_t) > Bytes.size())
return MCDisassembler::Fail;
NumExtraOperands = support::endian::read64le(Bytes.data() + Pos);
Pos += sizeof(uint64_t);
}
// Read the fixed operands. These are described by the MCInstrDesc.
for (unsigned i = 0; i < NumFixedOperands; ++i) {
const MCOperandInfo &Info = Desc.OpInfo[i];
switch (Info.OperandType) {
case MCOI::OPERAND_IMMEDIATE:
case WebAssembly::OPERAND_P2ALIGN:
case WebAssembly::OPERAND_BASIC_BLOCK: {
if (Pos + sizeof(uint64_t) > Bytes.size())
return MCDisassembler::Fail;
uint64_t Imm = support::endian::read64le(Bytes.data() + Pos);
Pos += sizeof(uint64_t);
MI.addOperand(MCOperand::createImm(Imm));
break;
}
case MCOI::OPERAND_REGISTER: {
if (Pos + sizeof(uint64_t) > Bytes.size())
return MCDisassembler::Fail;
uint64_t Reg = support::endian::read64le(Bytes.data() + Pos);
Pos += sizeof(uint64_t);
MI.addOperand(MCOperand::createReg(Reg));
break;
}
case WebAssembly::OPERAND_FPIMM: {
// TODO: MC converts all floating point immediate operands to double.
// This is fine for numeric values, but may cause NaNs to change bits.
if (Pos + sizeof(uint64_t) > Bytes.size())
return MCDisassembler::Fail;
uint64_t Bits = support::endian::read64le(Bytes.data() + Pos);
Pos += sizeof(uint64_t);
double Imm;
memcpy(&Imm, &Bits, sizeof(Imm));
MI.addOperand(MCOperand::createFPImm(Imm));
break;
}
default:
llvm_unreachable("unimplemented operand kind");
}
}
// Read the extra operands.
assert(NumExtraOperands == 0 || Desc.isVariadic());
for (unsigned i = 0; i < NumExtraOperands; ++i) {
if (Pos + sizeof(uint64_t) > Bytes.size())
return MCDisassembler::Fail;
if (Desc.TSFlags & WebAssemblyII::VariableOpIsImmediate) {
// Decode extra immediate operands.
uint64_t Imm = support::endian::read64le(Bytes.data() + Pos);
MI.addOperand(MCOperand::createImm(Imm));
} else {
// Decode extra register operands.
uint64_t Reg = support::endian::read64le(Bytes.data() + Pos);
MI.addOperand(MCOperand::createReg(Reg));
}
Pos += sizeof(uint64_t);
}
Size = Pos;
return MCDisassembler::Success;
}
