void VerilogDocGen::writeVerilogDeclarations(MemberDef* mdef,OutputList &ol,
ClassDef *cd,NamespaceDef *nd,FileDef *fd,GroupDef *gd,
bool inGroup) {
static bool bComp=false;
//LockingPtr<MemberDef> lock(mdef,mdef);
Definition *d=0;
// ASSERT (cd!=0 || nd!=0 || fd!=0 || gd!=0); // member should belong to something
//static_cast<VPreProcImp*>(m_opaquep);
if (cd) d=cd;
else if (nd) d=(Definition*)nd;
else if (fd) d=fd;
else if (gd) d=(Definition*)gd;
else d=(Definition*)mdef;
//if (cd) d=cd;
// write tag file information of this member
int memType=mdef->getMemberSpecifiers();
if (!Config_getString("GENERATE_TAGFILE").isEmpty())
{
Doxygen::tagFile << " <member kind=\"";
Doxygen::tagFile << VerilogDocGen::convertTypeToString(memType);
Doxygen::tagFile << "\">" << endl;
Doxygen::tagFile << " <type>" << convertToXML(mdef->typeString()) << "</type>" << endl;
Doxygen::tagFile << " <name>" << convertToXML(mdef->name()) << "</name>" << endl;
Doxygen::tagFile << " <anchorfile>" << convertToXML(mdef->getOutputFileBase()+Doxygen::htmlFileExtension) << "</anchorfile>" << endl;
Doxygen::tagFile << " <anchor>" << convertToXML(mdef->anchor()) << "</anchor>" << endl;
if(memType==VerilogDocGen::FUNCTION)
Doxygen::tagFile << " <arglist>" << convertToXML(VhdlDocGen::convertArgumentListToString(mdef->argumentList(),true)) << "</arglist>" << endl;
else if(memType==VerilogDocGen::ALWAYS)
Doxygen::tagFile << " <arglist>" << convertToXML(VhdlDocGen::convertArgumentListToString(mdef->argumentList(),false)) << "</arglist>" << endl;
else{
Doxygen::tagFile << " <arglist>" << convertToXML(mdef->argsString()) << "</arglist>" << endl;
Doxygen::tagFile << " <arglist>" << convertToXML(mdef->typeString()) << "</arglist>" << endl;
}
mdef->writeDocAnchorsToTagFile();
Doxygen::tagFile << " </member>" << endl;
}
// write search index info
if (Doxygen::searchIndex)
{
Doxygen::searchIndex->setCurrentDoc(mdef,mdef->anchor(),FALSE);
Doxygen::searchIndex->addWord(mdef->localName(),TRUE);
Doxygen::searchIndex->addWord(mdef->qualifiedName(),FALSE);
}
QCString cname = d->name();
QCString cfname = mdef->getOutputFileBase();
// HtmlHelp *htmlHelp=0;
// bool hasHtmlHelp = Config_getBool("GENERATE_HTML") && Config_getBool("GENERATE_HTMLHELP");
// if (hasHtmlHelp) htmlHelp = HtmlHelp::getInstance();
// search for the last anonymous scope in the member type
// ClassDef *annoClassDef=mdef->getClassDefOfAnonymousType();
// start a new member declaration
// bool isAnonymous = annoClassDef; // || m_impl->annMemb || m_impl->annEnumType;
///printf("startMemberItem for %s\n",name().data());
// if(mdef->getMemberSpecifiers()==VerilogDocGen::FEATURE)
// ol.startMemberItem(mdef->anchor(),3); //? 1 : m_impl->tArgList ? 3 : 0);
// else
ol.startMemberItem(mdef->anchor(), 0);// ? 1 : m_impl->tArgList ? 3 : 0);
// If there is no detailed description we need to write the anchor here.
bool detailsVisible = mdef->isDetailedSectionLinkable();
if (!detailsVisible) // && !m_impl->annMemb)
{
QCString doxyName=mdef->name().copy();
if (!cname.isEmpty()) doxyName.prepend(cname+"::");
QCString doxyArgs=mdef->argsString();
ol.startDoxyAnchor(cfname,cname,mdef->anchor(),doxyName,doxyArgs);
ol.pushGeneratorState();
ol.disable(OutputGenerator::Man);
ol.disable(OutputGenerator::Latex);
ol.docify("\n");
ol.popGeneratorState();
}
// *** write type
/*Verilog CHANGE */
VerilogDocGen::adjustMemberName(mdef);
QCString ltype(mdef->typeString());
QCString largs(mdef->argsString());
int mm=mdef->getMemberSpecifiers();
ClassDef *kl=NULL;
FileDef *fdd=NULL;
ArgumentList *alp = mdef->argumentList();
QCString nn;
if(gd)gd=NULL;
switch(mm)
{
case VhdlDocGen::MISCELLANEOUS:
VhdlDocGen::writeSource(mdef,ol,nn);
break;
case VhdlDocGen::UCF_CONST:
mm=mdef->name().findRev('_');
if(mm>0)
mdef->setName(mdef->name().left(mm));
writeUCFLink(mdef,ol);
break;
case VerilogDocGen::INCLUDE:
bool ambig;
largs=mdef->name();
fdd=findFileDef(Doxygen::inputNameDict,largs.data(),ambig);
if(fdd){
QCString fbb=fdd->getFileBase();
fbb=fdd->getReference();
fbb= fdd->getOutputFileBase();
fbb=fdd->getSourceFileBase();
fbb=fdd->convertNameToFile(largs.data(),true);
fbb=fdd->getPath();
fbb+=fdd->getOutputFileBase()+".html";
ol.writeObjectLink(fdd->getReference(),
fdd->getOutputFileBase(),
0,
fdd->name());
}
else
VhdlDocGen::formatString(largs,ol,mdef);
break;
case VerilogDocGen::FEATURE:
parseDefineConstruct(largs,mdef,ol);
break;
case VerilogDocGen::MODULE:
ol.startBold();
VhdlDocGen::formatString(ltype,ol,mdef);
ol.endBold();
ol.insertMemberAlign();
//writeLink(mdef,ol);
case VerilogDocGen::PORT:
writeLink(mdef,ol);
ol.insertMemberAlign();
if(largs.length()>0)
VhdlDocGen::formatString(largs,ol,mdef);
if(ltype.length()>0)
VhdlDocGen::formatString(ltype,ol,mdef);
break;
case VerilogDocGen::ALWAYS:
writeLink(mdef,ol);
ol.insertMemberAlign();
VhdlDocGen::writeProcessProto(ol,alp,mdef);
break;
case VerilogDocGen::FUNCTION:
case VerilogDocGen::TASK:
writeLink(mdef,ol);
ol.docify(" ");// need for pdf has no effect in html
ol.insertMemberAlign();
if(ltype.length()>0)
VhdlDocGen::formatString(ltype,ol,mdef);
writeFunctionProto(ol,alp,mdef);
break;
case VerilogDocGen::SIGNAL:
if(largs.length()>0)
VhdlDocGen::formatString(largs,ol,mdef);
ol.docify(" ");
ol.insertMemberAlign();
writeLink(mdef,ol);
ol.docify(" ");
if(ltype.length())
VhdlDocGen::formatString(ltype,ol,mdef);
break;
case VerilogDocGen::CONFIGURATION:
case VerilogDocGen::LIBRARY:
writeLink(mdef,ol);
break;
case VerilogDocGen::INPUT:
case VerilogDocGen::OUTPUT:
case VerilogDocGen::INOUT:
case VerilogDocGen::PARAMETER:
writeLink(mdef,ol);
ol.docify(" ");
ol.insertMemberAlign();
if(ltype.length()>0){
VhdlDocGen::formatString(ltype,ol,mdef);
ol.writeString(" ");
}
//ol.insertMemberAlign();
if(largs.length()>0)
VhdlDocGen::formatString(largs,ol,mdef);
break;
case VerilogDocGen::COMPONENT:
//VhdlDocGen::writeLink(mdef,ol);
if(true)
{
nn=mdef->name();
kl=VhdlDocGen::getClass(nn);
//if(kl==NULL){
ol.startBold();
QCString inst=mdef->name()+"::"+ltype;
ol.writeObjectLink(mdef->getReference(),
mdef->getOutputFileBase(),
mdef->anchor(),
inst.data());
ol.docify(" ");
ol.endBold();
//}
ol.insertMemberAlign();
if(kl) {
nn=kl->getOutputFileBase();
ol.pushGeneratorState();
ol.disableAllBut(OutputGenerator::Html);
ol.docify(" ");
QCString name=VerilogDocGen::getClassTitle(kl);
name=VhdlDocGen::getIndexWord(name.data(),1);
// ol.insertMemberAlign();
ol.startBold();
ol.docify(name.data());
ol.endBold();
ol.startEmphasis();
ol.docify(" ");
ol.writeObjectLink(kl->getReference(),kl->getOutputFileBase(),0,mdef->name().data());
ol.endEmphasis();
ol.popGeneratorState();
}
if(largs.data())
{
ol.docify(" ");
ol.docify(largs.data());
}
}
break;
default: break;
}
bool htmlOn = ol.isEnabled(OutputGenerator::Html);
if (htmlOn && !ltype.isEmpty())
{
ol.disable(OutputGenerator::Html);
}
if (!ltype.isEmpty()) ol.docify(" ");
if (htmlOn)
{
ol.enable(OutputGenerator::Html);
}
if (!detailsVisible)// && !m_impl->annMemb)
{
ol.endDoxyAnchor(cfname,mdef->anchor());
}
//printf("endMember %s annoClassDef=%p annEnumType=%p\n",
// name().data(),annoClassDef,annEnumType);
ol.endMemberItem();
//fprintf(stderr,"\n%d %s",mdef->docLine,mdef->name().data());
if (!mdef->briefDescription().isEmpty() && Config_getBool("BRIEF_MEMBER_DESC") /* && !annMemb */)
{
ol.startMemberDescription(mdef->anchor());
ol.generateDoc(mdef->briefFile(),mdef->briefLine(),mdef->getOuterScope()?mdef->getOuterScope():d,mdef,mdef->briefDescription(),TRUE,FALSE,0,TRUE,FALSE);
if (detailsVisible)
{
ol.pushGeneratorState();
ol.disableAllBut(OutputGenerator::Html);
//ol.endEmphasis();
ol.docify(" ");
if (mdef->getGroupDef()!=0 && gd==0) // forward link to the group
{
ol.startTextLink(mdef->getOutputFileBase(),mdef->anchor());
}
else // local link
{
ol.startTextLink(0,mdef->anchor());
}
ol.endTextLink();
//ol.startEmphasis();
ol.popGeneratorState();
}
//ol.newParagraph();
ol.endMemberDescription();
// if(VhdlDocGen::isComponent(mdef))
// ol.lineBreak();
}
mdef->warnIfUndocumented();
}// end writeVerilogDeclaration
