bool RegisterContextDarwin_arm64::ReadRegister(const RegisterInfo *reg_info,
RegisterValue &value) {
const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
int set = RegisterContextDarwin_arm64::GetSetForNativeRegNum(reg);
if (set == -1)
return false;
if (ReadRegisterSet(set, false) != KERN_SUCCESS)
return false;
switch (reg) {
case gpr_x0:
case gpr_x1:
case gpr_x2:
case gpr_x3:
case gpr_x4:
case gpr_x5:
case gpr_x6:
case gpr_x7:
case gpr_x8:
case gpr_x9:
case gpr_x10:
case gpr_x11:
case gpr_x12:
case gpr_x13:
case gpr_x14:
case gpr_x15:
case gpr_x16:
case gpr_x17:
case gpr_x18:
case gpr_x19:
case gpr_x20:
case gpr_x21:
case gpr_x22:
case gpr_x23:
case gpr_x24:
case gpr_x25:
case gpr_x26:
case gpr_x27:
case gpr_x28:
case gpr_fp:
case gpr_sp:
case gpr_lr:
case gpr_pc:
case gpr_cpsr:
value.SetUInt64(gpr.x[reg - gpr_x0]);
break;
case gpr_w0:
case gpr_w1:
case gpr_w2:
case gpr_w3:
case gpr_w4:
case gpr_w5:
case gpr_w6:
case gpr_w7:
case gpr_w8:
case gpr_w9:
case gpr_w10:
case gpr_w11:
case gpr_w12:
case gpr_w13:
case gpr_w14:
case gpr_w15:
case gpr_w16:
case gpr_w17:
case gpr_w18:
case gpr_w19:
case gpr_w20:
case gpr_w21:
case gpr_w22:
case gpr_w23:
case gpr_w24:
case gpr_w25:
case gpr_w26:
case gpr_w27:
case gpr_w28: {
ProcessSP process_sp(m_thread.GetProcess());
if (process_sp.get()) {
DataExtractor regdata(&gpr.x[reg - gpr_w0], 8, process_sp->GetByteOrder(),
process_sp->GetAddressByteSize());
offset_t offset = 0;
uint64_t retval = regdata.GetMaxU64(&offset, 8);
uint32_t retval_lower32 = static_cast<uint32_t>(retval & 0xffffffff);
value.SetUInt32(retval_lower32);
}
} break;
case fpu_v0:
case fpu_v1:
case fpu_v2:
case fpu_v3:
case fpu_v4:
case fpu_v5:
case fpu_v6:
case fpu_v7:
case fpu_v8:
case fpu_v9:
case fpu_v10:
case fpu_v11:
case fpu_v12:
case fpu_v13:
case fpu_v14:
case fpu_v15:
case fpu_v16:
case fpu_v17:
case fpu_v18:
case fpu_v19:
case fpu_v20:
case fpu_v21:
case fpu_v22:
case fpu_v23:
case fpu_v24:
case fpu_v25:
case fpu_v26:
case fpu_v27:
case fpu_v28:
case fpu_v29:
case fpu_v30:
case fpu_v31:
value.SetBytes(fpu.v[reg].bytes, reg_info->byte_size,
endian::InlHostByteOrder());
break;
case fpu_s0:
case fpu_s1:
case fpu_s2:
case fpu_s3:
case fpu_s4:
case fpu_s5:
case fpu_s6:
case fpu_s7:
case fpu_s8:
case fpu_s9:
case fpu_s10:
case fpu_s11:
case fpu_s12:
case fpu_s13:
case fpu_s14:
case fpu_s15:
case fpu_s16:
case fpu_s17:
case fpu_s18:
case fpu_s19:
case fpu_s20:
case fpu_s21:
case fpu_s22:
case fpu_s23:
case fpu_s24:
case fpu_s25:
case fpu_s26:
case fpu_s27:
case fpu_s28:
case fpu_s29:
case fpu_s30:
case fpu_s31: {
ProcessSP process_sp(m_thread.GetProcess());
if (process_sp.get()) {
DataExtractor regdata(&fpu.v[reg - fpu_s0], 4, process_sp->GetByteOrder(),
process_sp->GetAddressByteSize());
offset_t offset = 0;
value.SetFloat(regdata.GetFloat(&offset));
}
} break;
case fpu_d0:
case fpu_d1:
case fpu_d2:
case fpu_d3:
case fpu_d4:
case fpu_d5:
case fpu_d6:
case fpu_d7:
case fpu_d8:
case fpu_d9:
case fpu_d10:
case fpu_d11:
case fpu_d12:
case fpu_d13:
case fpu_d14:
case fpu_d15:
case fpu_d16:
case fpu_d17:
case fpu_d18:
case fpu_d19:
case fpu_d20:
case fpu_d21:
case fpu_d22:
case fpu_d23:
case fpu_d24:
case fpu_d25:
case fpu_d26:
case fpu_d27:
case fpu_d28:
case fpu_d29:
case fpu_d30:
case fpu_d31: {
ProcessSP process_sp(m_thread.GetProcess());
if (process_sp.get()) {
DataExtractor regdata(&fpu.v[reg - fpu_s0], 8, process_sp->GetByteOrder(),
process_sp->GetAddressByteSize());
offset_t offset = 0;
value.SetDouble(regdata.GetDouble(&offset));
}
} break;
case fpu_fpsr:
value.SetUInt32(fpu.fpsr);
break;
case fpu_fpcr:
value.SetUInt32(fpu.fpcr);
break;
case exc_exception:
value.SetUInt32(exc.exception);
break;
case exc_esr:
value.SetUInt32(exc.esr);
break;
case exc_far:
value.SetUInt64(exc.far);
break;
default:
value.SetValueToInvalid();
return false;
}
return true;
}
bool
RegisterContextDarwin_arm64::ReadRegister (const RegisterInfo *reg_info, RegisterValue &value)
{
const uint32_t reg = reg_info->kinds[eRegisterKindLLDB];
int set = RegisterContextDarwin_arm64::GetSetForNativeRegNum (reg);
if (set == -1)
return false;
if (ReadRegisterSet(set, false) != KERN_SUCCESS)
return false;
switch (reg)
{
case gpr_x0:
case gpr_x1:
case gpr_x2:
case gpr_x3:
case gpr_x4:
case gpr_x5:
case gpr_x6:
case gpr_x7:
case gpr_x8:
case gpr_x9:
case gpr_x10:
case gpr_x11:
case gpr_x12:
case gpr_x13:
case gpr_x14:
case gpr_x15:
case gpr_x16:
case gpr_x17:
case gpr_x18:
case gpr_x19:
case gpr_x20:
case gpr_x21:
case gpr_x22:
case gpr_x23:
case gpr_x24:
case gpr_x25:
case gpr_x26:
case gpr_x27:
case gpr_x28:
case gpr_fp:
case gpr_sp:
case gpr_lr:
case gpr_pc:
case gpr_cpsr:
value.SetUInt64 (gpr.x[reg - gpr_x0]);
break;
case fpu_v0:
case fpu_v1:
case fpu_v2:
case fpu_v3:
case fpu_v4:
case fpu_v5:
case fpu_v6:
case fpu_v7:
case fpu_v8:
case fpu_v9:
case fpu_v10:
case fpu_v11:
case fpu_v12:
case fpu_v13:
case fpu_v14:
case fpu_v15:
case fpu_v16:
case fpu_v17:
case fpu_v18:
case fpu_v19:
case fpu_v20:
case fpu_v21:
case fpu_v22:
case fpu_v23:
case fpu_v24:
case fpu_v25:
case fpu_v26:
case fpu_v27:
case fpu_v28:
case fpu_v29:
case fpu_v30:
case fpu_v31:
value.SetBytes(fpu.v[reg].bytes, reg_info->byte_size, lldb::endian::InlHostByteOrder());
break;
case fpu_fpsr:
value.SetUInt32 (fpu.fpsr);
break;
case fpu_fpcr:
value.SetUInt32 (fpu.fpcr);
break;
case exc_exception:
value.SetUInt32 (exc.exception);
break;
case exc_esr:
value.SetUInt32 (exc.esr);
break;
case exc_far:
value.SetUInt64 (exc.far);
break;
default:
value.SetValueToInvalid();
return false;
}
return true;
}
