void AudDrv_Suspend_Clk_Off(void)
{
    unsigned long flags;
    spin_lock_irqsave(&auddrv_Clk_lock, flags);
    if (Aud_AFE_Clk_cntr > 0)
    {
        PRINTK_AUD_CLK("AudDrv_Suspend_Clk_Off Aud_AFE_Clk_cntr:%d ANA_Clk(%d)\n", Aud_AFE_Clk_cntr, Aud_ANA_Clk_cntr);
#ifdef PM_MANAGER_API
        //Disable AFE clock and I2S clock
        Afe_Set_Reg(AUDIO_TOP_CON0, 0x00004044, 0x00004044); // bit2: afe power off, bit6: I2S power off

        if (disable_clock(MT_CG_AUDIO_AFE, "AUDIO"))
        {
            xlog_printk(ANDROID_LOG_ERROR, "Sound", "AudDrv_Suspend_Clk_Off() disable_clock MT_CG_AUDIO_AFE fail");
        }

        if (Aud_I2S_Clk_cntr > 0)
        {
            if (disable_clock(MT_CG_AUDIO_I2S, "AUDIO"))
            {
                xlog_printk(ANDROID_LOG_ERROR, "Sound", "AudDrv_Suspend_Clk_Off() disable_clock MT_CG_AUDIO_I2S fail");
            }
        }
#else
        Afe_Set_Reg(AUDIO_TOP_CON0, 0x00004044, 0x00004044);  // bit2: afe power off, bit6: I2S power off
#endif
    }
    spin_unlock_irqrestore(&auddrv_Clk_lock, flags);
    if (Aud_ANA_Clk_cntr > 0)
    {
        PRINTK_AUD_CLK("AudDrv_Suspend_Clk_On Aud_AFE_Clk_cntr:%d ANA_Clk(%d) \n", Aud_AFE_Clk_cntr, Aud_ANA_Clk_cntr);
    }
}
static int mtk_pcm_hdmi_stop(struct snd_pcm_substream *substream)
{
    AFE_BLOCK_T *Afe_Block = &(pMemControl->rBlock);

    printk("mtk_pcm_hdmi_stop \n");

    SetIrqEnable(Soc_Aud_IRQ_MCU_MODE_IRQ5_MCU_MODE, false);

    SetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_HDMI, false);

#ifdef _DEBUG_TDM_KERNEL_
    #if 0
    Afe_Set_Reg(AFE_TDM_CON2, 0, 0x00010000); // disable TDM to I2S path
    #endif
    Afe_Set_Reg(AFE_I2S_CON, 0, 0x00000001); // I2S disable
    msleep(1);
#endif
    SetTDMEnable(false); //disable TDM
    SetHDMIEnable(false);
    Afe_Set_Reg(AUDIO_TOP_CON0, 0 << 20,  1 << 20); //  disable HDMI CK
    EnableAfe(false);
    RemoveMemifSubStream(Soc_Aud_Digital_Block_MEM_HDMI, substream);


    Afe_Block->u4DMAReadIdx  = 0;
    Afe_Block->u4WriteIdx  = 0;
    Afe_Block->u4DataRemained = 0;

    return 0;
}
static int mtk_pcm_i2s0_stop(struct snd_pcm_substream *substream)
{
    AFE_BLOCK_T *Afe_Block = &(pI2s0MemControl->rBlock);

    printk("mtk_pcm_i2s0_stop \n");
    SetIrqEnable(Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE, false);

    // here start digital part
    SetConnection(Soc_Aud_InterCon_DisConnect, Soc_Aud_InterConnectionInput_I05, Soc_Aud_InterConnectionOutput_O00);
    SetConnection(Soc_Aud_InterCon_DisConnect, Soc_Aud_InterConnectionInput_I06, Soc_Aud_InterConnectionOutput_O01);
    SetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_DL1, false);

    // stop I2S
    Afe_Set_Reg(AFE_I2S_CON3, 0x0, 0x1);
    Afe_Set_Reg(AFE_I2S_CON, 0x0, 0x1);

    EnableAfe(false);

    // clean audio hardware buffer
    memset(Afe_Block->pucVirtBufAddr, 0, Afe_Block->u4BufferSize);
    RemoveMemifSubStream(Soc_Aud_Digital_Block_MEM_DL1,substream);
    AudDrv_Clk_Off();

    return 0;
}
static void SetHDMIAddress(void)
{
	pr_debug("%s buffer length = %d\n", __func__, (int)HDMI_dma_buf->bytes);
	Afe_Set_Reg(AFE_HDMI_BASE, HDMI_dma_buf->addr, 0xffffffff);
	Afe_Set_Reg(AFE_HDMI_END, HDMI_dma_buf->addr + (HDMI_dma_buf->bytes - 1),
		0xffffffff);
}
static void SetHDMIBuffer(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params)
{

	kal_uint32 volatile u4tmpMrg1;

	struct snd_pcm_runtime *runtime = substream->runtime;
	AFE_BLOCK_T *pblock = &(pMemControl->rBlock);

	pblock->pucPhysBufAddr = runtime->dma_addr;
	pblock->pucVirtBufAddr = runtime->dma_area;
	pblock->u4BufferSize = runtime->dma_bytes;
	pblock->u4SampleNumMask = 0x001f;	/* 32 byte align */
	pblock->u4WriteIdx = 0;
	pblock->u4DMAReadIdx = 0;
	pblock->u4DataRemained = 0;
	pblock->u4fsyncflag = false;
	pblock->uResetFlag = true;

	PRINTK_AUD_HDMI("%s, dma_bytes = %d, dma_area = %p, dma_addr = 0x%x\n",
		__func__, pblock->u4BufferSize, pblock->pucVirtBufAddr,
		pblock->pucPhysBufAddr);

	Afe_Set_Reg(AFE_HDMI_BASE, pblock->pucPhysBufAddr, 0xffffffff);
	Afe_Set_Reg(AFE_HDMI_END, pblock->pucPhysBufAddr + (pblock->u4BufferSize - 1),
		0xffffffff);

	u4tmpMrg1 = Afe_Get_Reg(AFE_HDMI_BASE);

	u4tmpMrg1 &= 0x00ffffff;

	PRINTK_AUD_HDMI("SetHDMIBuffer AFE_HDMI_BASE = 0x%x\n", u4tmpMrg1);
}
bool SetConnectionState(uint32 ConnectionState, uint32 Input, uint32 Output)
{
	/* printk("SetinputConnection ConnectionState = %d
	Input = %d Output = %d\n", ConnectionState, Input, Output); */
	int connectReg = 0;

	switch (ConnectionState) {
	case Soc_Aud_InterCon_DisConnect:
	{
		/* printk("nConnectionState = %d\n", ConnectionState); */
		if ((mConnectionState[Input][Output] & Soc_Aud_InterCon_Connection)
			== Soc_Aud_InterCon_Connection) {

			/* here to disconnect connect bits */
			connectReg = mConnectionReg[Output];
			if (CheckBitsandReg(connectReg, Input)) {
				Afe_Set_Reg(connectReg, 0, 1 << Input);
				mConnectionState[Input][Output] &= ~(Soc_Aud_InterCon_Connection);
			}
		}
		if ((mConnectionState[Input][Output] & Soc_Aud_InterCon_ConnectionShift)
			== Soc_Aud_InterCon_ConnectionShift) {

			/* here to disconnect connect shift bits */
			if (CheckBitsandReg(AFE_CONN_RS, Input)) {
				Afe_Set_Reg(AFE_CONN_RS, 0, 1 << Input);
				mConnectionState[Input][Output] &= ~(Soc_Aud_InterCon_ConnectionShift);
			}
		}
		break;
	}
	case Soc_Aud_InterCon_Connection:
	{
		/* printk("nConnectionState = %d\n", ConnectionState); */
		connectReg = mConnectionReg[Output];
		if (CheckBitsandReg(connectReg, Input)) {
			Afe_Set_Reg(connectReg, 1 << Input, 1 << Input);
			mConnectionState[Input][Output] |= Soc_Aud_InterCon_Connection;
		}
		break;
	}
	case Soc_Aud_InterCon_ConnectionShift:
	{
		/* printk("nConnectionState = %d\n", ConnectionState); */
		if (CheckBitsandReg(AFE_CONN_RS, Input)) {
			Afe_Set_Reg(AFE_CONN_RS, 1 << Input, 1 << Input);
			mConnectionState[Input][Output] |= Soc_Aud_InterCon_ConnectionShift;
		}
		break;
	}
	default:
		pr_err("no this state ConnectionState = %d\n", ConnectionState);
		break;
	}

	return true;
}
static void SetHDMIAddress(void)
{
#if 0
    printk("%s buffer length = %d\n", __func__,    HDMI_dma_buf->bytes);
    Afe_Set_Reg(AFE_HDMI_BASE , HDMI_dma_buf->addr , 0xffffffff);
    Afe_Set_Reg(AFE_HDMI_END  , HDMI_dma_buf->addr + (HDMI_dma_buf->bytes - 1), 0xffffffff);
#else
    printk("%s mt6572 not support!!!\n", __func__);
#endif
}
void AudDrv_APLL2Tuner_Clk_On(void)
{
    unsigned long flags;
    spin_lock_irqsave(&auddrv_Clk_lock, flags);
    if (Aud_APLL2_Tuner_cntr == 0)
    {
        PRINTK_AUD_CLK("+Aud_APLL2_Tuner_cntr, Aud_APLL2_Tuner_cntr:%d \n", Aud_APLL2_Tuner_cntr);
        Afe_Set_Reg(AUDIO_TOP_CON0, 0x0 << 18, 0x1 << 18);
        Afe_Set_Reg(AFE_APLL2_TUNER_CFG, 0x00000033, 0x1 << 19);
    }
    Aud_APLL2_Tuner_cntr++;
    spin_unlock_irqrestore(&auddrv_Clk_lock, flags);
}
Exemple #9
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void AudDrv_ADC2_Clk_Off(void)
{
    //PRINTK_AUDDRV("+%s %d \n", __func__,Aud_ADC2_Clk_cntr);
    mutex_lock(&auddrv_pmic_mutex);
    Aud_ADC2_Clk_cntr--;
    if (Aud_ADC2_Clk_cntr == 0)
    {
        PRINTK_AUDDRV("+%s disable_clock ADC clk(%x)\n", __func__, Aud_ADC2_Clk_cntr);
#if 0 //K2 removed		
#ifdef PM_MANAGER_API
        if (disable_clock(MT_CG_AUDIO_ADDA2, "AUDIO"))
        {
            PRINTK_AUD_CLK("%s fail", __func__);
        }
#else
        Afe_Set_Reg(AUDIO_TOP_CON0, 1 << 23 , 1 << 23); //temp hard code setting, after confirm with enable clock usage, this could be removed.
#endif
#endif
    }
    if (Aud_ADC2_Clk_cntr < 0)
    {
        PRINTK_AUDDRV("%s  <0 (%d) \n", __func__, Aud_ADC2_Clk_cntr);
        Aud_ADC2_Clk_cntr = 0;
    }
    mutex_unlock(&auddrv_pmic_mutex);
    //PRINTK_AUDDRV("-AudDrv_ADC_Clk_Off, Aud_ADC_Clk_cntr:%d \n", Aud_ADC_Clk_cntr);
}
Exemple #10
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void AudDrv_Clk_Off(void)
{
    unsigned long flags;
    PRINTK_AUD_CLK("+!! AudDrv_Clk_Off, Aud_AFE_Clk_cntr:%d \n",Aud_AFE_Clk_cntr);
    spin_lock_irqsave(&auddrv_Clk_lock, flags);

    Aud_AFE_Clk_cntr--;
    if (Aud_AFE_Clk_cntr == 0)
    {
        printk("------------AudDrv_Clk_Off, Aud_AFE_Clk_cntr:%d \n", Aud_AFE_Clk_cntr);
        {
            // Disable AFE clock
#ifdef PM_MANAGER_API
            if (disable_clock(MT_CG_AUDIO_AFE, "AUDIO"))
            {
                xlog_printk(ANDROID_LOG_ERROR, "Sound", "disable_clock MT_CG_AUDIO_AFE fail");
            }
#else
            Afe_Set_Reg(AUDIO_TOP_CON0, 0x06000044, 0x06000044);
#endif

        }
    }
    else if (Aud_AFE_Clk_cntr < 0)
    {
        PRINTK_AUD_ERROR("!! AudDrv_Clk_Off, Aud_AFE_Clk_cntr<0 (%d) \n", Aud_AFE_Clk_cntr);
        AUDIO_ASSERT(true);
        Aud_AFE_Clk_cntr = 0;
    }
    PRINTK_AUD_CLK("-!! AudDrv_Clk_Off, Aud_AFE_Clk_cntr:%d \n",Aud_AFE_Clk_cntr);
    spin_unlock_irqrestore(&auddrv_Clk_lock, flags);
}
void AudDrv_ADC_Clk_Off(void)
{
    //PRINTK_AUDDRV("+AudDrv_ADC_Clk_Off, Aud_ADC_Clk_cntr:%d \n", Aud_ADC_Clk_cntr);
    mutex_lock(&auddrv_pmic_mutex);
    Aud_ADC_Clk_cntr--;
    if (Aud_ADC_Clk_cntr == 0)
    {
        PRINTK_AUDDRV("+AudDrv_ADC_Clk_On disable_clock ADC clk(%x)\n", Aud_ADC_Clk_cntr);
        //Afe_Set_Reg(AUDIO_TOP_CON0, 1 << 24 , 1 << 24);
#ifdef PM_MANAGER_API
#if defined(CONFIG_MTK_LEGACY)

        if (disable_clock(MT_CG_AUDIO_ADC, "AUDIO"))
        {
            PRINTK_AUD_CLK("%s fail", __func__);
        }
#else
        if (paudclk->aud_adc_clk_status)
        {
            clk_disable_unprepare(paudclk->aud_adc_clk);
        }
#endif
#else
        Afe_Set_Reg(AUDIO_TOP_CON0, 1 << 24 , 1 << 24);
#endif
    }
    if (Aud_ADC_Clk_cntr < 0)
    {
        PRINTK_AUDDRV("!! AudDrv_ADC_Clk_Off, Aud_ADC_Clk_cntr<0 (%d) \n", Aud_ADC_Clk_cntr);
        Aud_ADC_Clk_cntr = 0;
    }
    mutex_unlock(&auddrv_pmic_mutex);
    //PRINTK_AUDDRV("-AudDrv_ADC_Clk_Off, Aud_ADC_Clk_cntr:%d \n", Aud_ADC_Clk_cntr);
}
void AudDrv_I2S_Clk_Off(void)
{
    unsigned long flags;
    //PRINTK_AUD_CLK("+AudDrv_I2S_Clk_Off, Aud_I2S_Clk_cntr:%d \n", Aud_I2S_Clk_cntr);
    spin_lock_irqsave(&auddrv_Clk_lock, flags);
    Aud_I2S_Clk_cntr--;
    if (Aud_I2S_Clk_cntr == 0)
    {
#ifdef PM_MANAGER_API
        if (disable_clock(MT_CG_AUDIO_I2S, "AUDIO"))
        {
            PRINTK_AUD_ERROR("disable_clock MT_CG_AUDIO_I2S fail");
        }
#else
        Afe_Set_Reg(AUDIO_TOP_CON0, 0x00000000, 0x00000040);  //power off I2S clock
#endif
    }
    else if (Aud_I2S_Clk_cntr < 0)
    {
        PRINTK_AUD_ERROR("!! AudDrv_I2S_Clk_Off, Aud_I2S_Clk_cntr<0 (%d) \n", Aud_I2S_Clk_cntr);
        AUDIO_ASSERT(true);
        Aud_I2S_Clk_cntr = 0;
    }
    spin_unlock_irqrestore(&auddrv_Clk_lock, flags);
    //PRINTK_AUD_CLK("-AudDrv_I2S_Clk_Off, Aud_I2S_Clk_cntr:%d \n",Aud_I2S_Clk_cntr);
}
Exemple #13
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void AudDrv_Clk_AllOn(void)
{
    unsigned long flags;
    printk("AudDrv_Clk_AllOn \n");
    spin_lock_irqsave(&auddrv_Clk_lock, flags);
    Afe_Set_Reg(AUDIO_TOP_CON0, 0x00004000, 0xffffffff);
    spin_unlock_irqrestore(&auddrv_Clk_lock, flags);
}
Exemple #14
0
void Auddrv_Bus_Init(void)
{
    unsigned long flags;
    printk("%s  \n", __func__);
    spin_lock_irqsave(&auddrv_Clk_lock, flags);
    Afe_Set_Reg(AUDIO_TOP_CON0, 0x00004000, 0x00004000); //must set, system will default set bit14 to 0
    spin_unlock_irqrestore(&auddrv_Clk_lock, flags);
}
static int Audio_Irqcnt2_Set(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
    uint32 irq1_cnt =  ucontrol->value.integer.value[0];
    printk("%s()\n", __func__);
    AudDrv_Clk_On();
    Afe_Set_Reg(AFE_IRQ_MCU_CNT2, irq1_cnt, 0xffffffff);
    AudDrv_Clk_Off();
    return 0;
}
void AudDrv_APLL1Tuner_Clk_Off(void)
{
    unsigned long flags;
    spin_lock_irqsave(&auddrv_Clk_lock, flags);

    Aud_APLL1_Tuner_cntr--;
    if (Aud_APLL1_Tuner_cntr == 0)
    {
        Afe_Set_Reg(AUDIO_TOP_CON0, 0x1 << 19, 0x1 << 19);
        Afe_Set_Reg(AFE_APLL1_TUNER_CFG, 0x00000033, 0x1 << 19);
    }
    // handle for clock error
    else if (Aud_APLL1_Tuner_cntr < 0)
    {
        PRINTK_AUD_ERROR("!! AudDrv_APLLTuner_Clk_Off, Aud_APLL1_Tuner_cntr<0 (%d) \n", Aud_APLL1_Tuner_cntr);
        Aud_APLL1_Tuner_cntr = 0;
    }
    spin_unlock_irqrestore(&auddrv_Clk_lock, flags);
}
static void StartAudioI2S0AWBHardware(struct snd_pcm_substream *substream)
{
    struct snd_pcm_runtime *runtime = substream->runtime;

    uint32 Audio_I2S_Dac = 0;
    uint32 MclkDiv0 = 0;

    const bool bEnablePhaseShiftFix = true;

    printk("StartAudioI2S0AWBHardware \n");


    MclkDiv0 = SetCLkMclk(Soc_Aud_I2S0, runtime->rate); //select I2S
    SetCLkBclk(MclkDiv0,  runtime->rate, runtime->channels, Soc_Aud_I2S_WLEN_WLEN_32BITS);
    
    // 2nd I2S In
    SetSampleRate(Soc_Aud_Digital_Block_MEM_I2S,  runtime->rate);

    Audio_I2S_Dac |= (bEnablePhaseShiftFix << 31);
    Audio_I2S_Dac |= (Soc_Aud_I2S_IN_PAD_SEL_I2S_IN_FROM_IO_MUX << 28);//I2S in from io_mux
    Audio_I2S_Dac |= Soc_Aud_LOW_JITTER_CLOCK << 12 ; //Low jitter mode
    Audio_I2S_Dac |= (Soc_Aud_INV_LRCK_NO_INVERSE << 5);
    Audio_I2S_Dac |= (Soc_Aud_I2S_FORMAT_I2S << 3);
    Audio_I2S_Dac |= (Soc_Aud_I2S_WLEN_WLEN_32BITS << 1);
    Afe_Set_Reg(AFE_I2S_CON, Audio_I2S_Dac | 0x1, MASK_ALL);

    // here to set interrupt
    SetIrqMcuCounter(Soc_Aud_IRQ_MCU_MODE_IRQ2_MCU_MODE, substream->runtime->period_size >> 1);
    SetIrqMcuSampleRate(Soc_Aud_IRQ_MCU_MODE_IRQ2_MCU_MODE, substream->runtime->rate);
    SetIrqEnable(Soc_Aud_IRQ_MCU_MODE_IRQ2_MCU_MODE, true);

    SetSampleRate(Soc_Aud_Digital_Block_MEM_AWB, substream->runtime->rate);
    SetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_AWB, true);
    SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_IN_2, true);

    // here to turn off digital part
#ifdef DUMP_HWGAIN1_AWB
        uint32 REG420 = 0;
        SetConnection(Soc_Aud_InterCon_DisConnect, Soc_Aud_InterConnectionInput_I00, Soc_Aud_InterConnectionOutput_O05);
        SetConnection(Soc_Aud_InterCon_DisConnect, Soc_Aud_InterConnectionInput_I01, Soc_Aud_InterConnectionOutput_O06);
        printk("%s() Soc_Aud_InterCon_Connection  I10  O5\n",  __func__);
        SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I10, Soc_Aud_InterConnectionOutput_O05);
        printk("%s() Soc_Aud_InterCon_Connection  I11  O6\n",  __func__);
        SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I11, Soc_Aud_InterConnectionOutput_O06);

        
        REG420 = Afe_Get_Reg(AFE_GAIN1_CONN);
        printk("%s() AFE_GAIN1_CONN (0X420) =0x%x\n",  __func__, REG420);
#else
        SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I00, Soc_Aud_InterConnectionOutput_O05);
        SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I01, Soc_Aud_InterConnectionOutput_O06);
#endif

    EnableAfe(true);
}
void AudDrv_Clk_AllOn(void)
{
    printk("AudDrv_Clk_AllOn \n");
    unsigned long flags;
    spin_lock_irqsave(&auddrv_Clk_lock, flags);

    Afe_Set_Reg(AUDIO_TOP_CON0, 0x00004000, 0xffffffff);

    spin_unlock_irqrestore(&auddrv_Clk_lock, flags);
    //PRINTK_AUD_CLK("-AudDrv_Clk_On, Aud_AFE_Clk_cntr:%d \n",Aud_AFE_Clk_cntr);
}
static int mtk_uldlloopbackpcm_close(struct snd_pcm_substream *substream)
{
    printk("%s \n", __func__);
    if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
    {
        printk("%s  with SNDRV_PCM_STREAM_CAPTURE \n", __func__);
        return 0;
    }

    // interconnection setting
    SetConnection(Soc_Aud_InterCon_DisConnect, Soc_Aud_InterConnectionInput_I03, Soc_Aud_InterConnectionOutput_O00);
    SetConnection(Soc_Aud_InterCon_DisConnect, Soc_Aud_InterConnectionInput_I04, Soc_Aud_InterConnectionOutput_O01);
    SetConnection(Soc_Aud_InterCon_DisConnect, Soc_Aud_InterConnectionInput_I03, Soc_Aud_InterConnectionOutput_O03);
    SetConnection(Soc_Aud_InterCon_DisConnect, Soc_Aud_InterConnectionInput_I04, Soc_Aud_InterConnectionOutput_O04);

    
    SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_IN_ADC, false);
    if (GetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_IN_ADC) == false)
    {
        SetI2SAdcEnable(false);
    }

    // stop DAC output
    SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, false);
    if (GetI2SDacEnable() == false)
    {
        SetI2SDacEnable(false);
    }

    // stop I2S
    Afe_Set_Reg(AFE_I2S_CON3, 0x0, 0x1);
    Afe_Set_Reg(AFE_I2S_CON, 0x0, 0x1);
    Afe_Set_Reg(AFE_I2S_CON1, 0x0, 0x1);
    Afe_Set_Reg(AFE_I2S_CON2, 0x0, 0x1);

    EnableAfe(false);

    AudDrv_Clk_Off();
    AudDrv_ADC_Clk_Off();
    return 0;
}
static void SetAWBBuffer(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *hw_params)
{
	AFE_BLOCK_T *pblock = &FM_I2S_AWB_Control_context->rBlock;
	struct snd_pcm_runtime *runtime = substream->runtime;
	pr_warn("SetAWBBuffer\n");
	pblock->pucPhysBufAddr = runtime->dma_addr;
	pblock->pucVirtBufAddr = runtime->dma_area;
	pblock->u4BufferSize = runtime->dma_bytes;
	pblock->u4SampleNumMask = 0x001f;	/* 32 byte align */
	pblock->u4WriteIdx = 0;
	pblock->u4DMAReadIdx = 0;
	pblock->u4DataRemained = 0;
	pblock->u4fsyncflag = false;
	pblock->uResetFlag = true;
	pr_warn("dma_bytes = %d dma_area = %p dma_addr = 0x%x\n",
	       pblock->u4BufferSize, pblock->pucVirtBufAddr, pblock->pucPhysBufAddr);
	/* set sram address top hardware */
	Afe_Set_Reg(AFE_AWB_BASE, pblock->pucPhysBufAddr, 0xffffffff);
	Afe_Set_Reg(AFE_AWB_END, pblock->pucPhysBufAddr + (pblock->u4BufferSize - 1), 0xffffffff);

}
static void SetFMTXBuffer(struct snd_pcm_substream *substream,
                          struct snd_pcm_hw_params *hw_params)
{
    struct snd_pcm_runtime *runtime = substream->runtime;
    AFE_BLOCK_T *pblock = &pMemControl->rBlock;
    pblock->pucPhysBufAddr =  runtime->dma_addr;
    pblock->pucVirtBufAddr =  runtime->dma_area;
    pblock->u4BufferSize = runtime->dma_bytes;
    pblock->u4SampleNumMask = 0x001f;  // 32 byte align
    pblock->u4WriteIdx     = 0;
    pblock->u4DMAReadIdx    = 0;
    pblock->u4DataRemained  = 0;
    pblock->u4fsyncflag     = false;
    pblock->uResetFlag      = true;
    printk("SetFMTXBuffer u4BufferSize = %d pucVirtBufAddr = %p pucPhysBufAddr = 0x%x\n",
           pblock->u4BufferSize, pblock->pucVirtBufAddr, pblock->pucPhysBufAddr);
    // set dram address top hardware
    Afe_Set_Reg(AFE_DL1_BASE , pblock->pucPhysBufAddr , 0xffffffff);
    Afe_Set_Reg(AFE_DL1_END  , pblock->pucPhysBufAddr + (pblock->u4BufferSize - 1), 0xffffffff);
    memset((void *)pblock->pucVirtBufAddr, 0, pblock->u4BufferSize);

}
Exemple #22
0
void AudDrv_APLL1Tuner_Clk_On(void)
{
    unsigned long flags;
    spin_lock_irqsave(&auddrv_Clk_lock, flags);
    if (Aud_APLL1_Tuner_cntr == 0)
    {
        PRINTK_AUD_CLK("+AudDrv_APLLTuner_Clk_On, Aud_APLL1_Tuner_cntr:%d \n", Aud_APLL1_Tuner_cntr);
        Afe_Set_Reg(AUDIO_TOP_CON0, 0x0 << 19, 0x1 << 19);
        SetpllCfg(AP_PLL_CON5, 0x1, 0x1);
    }
    Aud_APLL1_Tuner_cntr++;
    spin_unlock_irqrestore(&auddrv_Clk_lock, flags);
}
Exemple #23
0
void AudDrv_ADC_Clk_On(void)
{
    //PRINTK_AUDDRV("+AudDrv_ADC_Clk_On, Aud_ADC_Clk_cntr:%d \n", Aud_ADC_Clk_cntr);
    mutex_lock(&auddrv_pmic_mutex);

    if (Aud_ADC_Clk_cntr == 0)
    {
        PRINTK_AUDDRV("+AudDrv_ADC_Clk_On enable_clock ADC clk(%x)\n", Aud_ADC_Clk_cntr);
        Afe_Set_Reg(AUDIO_TOP_CON0, 0 << 24 , 1 << 24);
    }
    Aud_ADC_Clk_cntr++;
    mutex_unlock(&auddrv_pmic_mutex);
}
static int mtk_pcm_i2s0_start(struct snd_pcm_substream *substream)
{
    struct snd_pcm_runtime *runtime = substream->runtime;
    uint32 u32AudioI2S = 0;
    AudDrv_Clk_On();
    SetMemifSubStream(Soc_Aud_Digital_Block_MEM_DL1, substream);
    if (runtime->format == SNDRV_PCM_FORMAT_S32_LE || runtime->format == SNDRV_PCM_FORMAT_S32_LE)
    {
        SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL1, AFE_WLEN_32_BIT_ALIGN_8BIT_0_24BIT_DATA);
        SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL2, AFE_WLEN_32_BIT_ALIGN_8BIT_0_24BIT_DATA);
    }
    else
    {
        SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL1, AFE_WLEN_16_BIT);
        SetMemIfFetchFormatPerSample(Soc_Aud_Digital_Block_MEM_DL2, AFE_WLEN_16_BIT);
    }

    SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O00);
    SetoutputConnectionFormat(OUTPUT_DATA_FORMAT_16BIT, Soc_Aud_InterConnectionOutput_O01);

    // here start digital part
    SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I05, Soc_Aud_InterConnectionOutput_O00);
    SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I06, Soc_Aud_InterConnectionOutput_O01);


    u32AudioI2S = SampleRateTransform(runtime->rate) << 8;
    u32AudioI2S |= Soc_Aud_I2S_FORMAT_I2S << 3; // us3 I2s format
    u32AudioI2S |= Soc_Aud_I2S_WLEN_WLEN_32BITS << 1; // 32 BITS

    if (mi2s0_hdoutput_control == true)
    {
        u32AudioI2S |= Soc_Aud_LOW_JITTER_CLOCK << 12 ; //Low jitter mode
    }

    printk(" u32AudioI2S= 0x%x\n", u32AudioI2S);
    Afe_Set_Reg(AFE_I2S_CON3, u32AudioI2S | 1, AFE_MASK_ALL);

    SetSampleRate(Soc_Aud_Digital_Block_MEM_DL1, runtime->rate);
    SetChannels(Soc_Aud_Digital_Block_MEM_DL1, runtime->channels);
    SetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_DL1, true);

    // here to set interrupt
    SetIrqMcuCounter(Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE, runtime->period_size);
    SetIrqMcuSampleRate(Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE, runtime->rate);
    SetIrqEnable(Soc_Aud_IRQ_MCU_MODE_IRQ1_MCU_MODE, true);

    EnableAfe(true);

    return 0;
}
static int mtk_pcm_I2S0dl1_close(struct snd_pcm_substream *substream)
{
    struct snd_pcm_runtime *runtime = substream->runtime;
    printk("%s \n", __func__);

    if (mPrepareDone == true)
    {
        // stop DAC output
        SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_DAC, false);
        if (GetI2SDacEnable() == false)
        {
            SetI2SDacEnable(false);
        }
        // stop I2S output
        SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_2, false);
        if (GetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_OUT_2) == false)
        {
            Afe_Set_Reg(AFE_I2S_CON3, 0x0, 0x1);
            //Afe_Set_Reg(AFE_I2S_CON, 0x0, 0x1);//K2 TODO: fix fm playback then mp3, i2s_con is misconfigured...
        }

        RemoveMemifSubStream(Soc_Aud_Digital_Block_MEM_DL1, substream);

        EnableAfe(false);

        if (mI2S0dl1_hdoutput_control == true)
        {
            printk("%s mI2S0dl1_hdoutput_control == %d \n", __func__, mI2S0dl1_hdoutput_control);

            EnableI2SDivPower(AUDIO_APLL12_DIV2, false);
            EnableI2SDivPower(AUDIO_APLL12_DIV4, false);   //Todo do we need open I2S3?

            EnableApll(runtime->rate, false);
            EnableApllTuner(runtime->rate, false);
        }

        mPrepareDone = false;
    }

    if (mPlaybackSramState == SRAM_STATE_PLAYBACKDRAM)
    {
        AudDrv_Emi_Clk_Off();
    }
    AfeControlSramLock();
    ClearSramState(mPlaybackSramState);
    mPlaybackSramState = GetSramState();
    AfeControlSramUnLock();
    AudDrv_Clk_Off();
    return 0;
}
static void StartAudioI2S0AWBHardware(struct snd_pcm_substream *substream)
{
    struct snd_pcm_runtime *runtime = substream->runtime;

    uint32 Audio_I2S_Dac = 0;
    uint32 MclkDiv0 = 0;

    const bool bEnablePhaseShiftFix = true;

    printk("StartAudioI2S0AWBHardware \n");


    MclkDiv0 = SetCLkMclk(Soc_Aud_I2S0, runtime->rate); //select I2S
    SetCLkBclk(MclkDiv0,  runtime->rate, runtime->channels, Soc_Aud_I2S_WLEN_WLEN_32BITS);
    
    // 2nd I2S In
    SetSampleRate(Soc_Aud_Digital_Block_MEM_I2S,  runtime->rate);

    Audio_I2S_Dac |= (bEnablePhaseShiftFix << 31);
    Audio_I2S_Dac |= (Soc_Aud_I2S_IN_PAD_SEL_I2S_IN_FROM_IO_MUX << 28);//I2S in from io_mux
    Audio_I2S_Dac |= Soc_Aud_LOW_JITTER_CLOCK << 12 ; //Low jitter mode
    Audio_I2S_Dac |= (Soc_Aud_INV_LRCK_NO_INVERSE << 5);
    Audio_I2S_Dac |= (Soc_Aud_I2S_FORMAT_I2S << 3);
    Audio_I2S_Dac |= (Soc_Aud_I2S_WLEN_WLEN_32BITS << 1);
    Afe_Set_Reg(AFE_I2S_CON, Audio_I2S_Dac | 0x1, MASK_ALL);
    // here to set interrupt
/*modified by jiaqing.yang for ALPS02074446(For_JHZ6735M_65C_L_ALPS.L1.MP3.V1_P67) 20150706 begin*/
#if 0
    SetIrqMcuCounter(Soc_Aud_IRQ_MCU_MODE_IRQ2_MCU_MODE, substream->runtime->period_size);
#else
	SetIrqMcuCounter(Soc_Aud_IRQ_MCU_MODE_IRQ2_MCU_MODE, substream->runtime->period_size >> 1);
#endif
/*modified by jiaqing.yang for ALPS02074446(For_JHZ6735M_65C_L_ALPS.L1.MP3.V1_P67) 20150706 end*/
    SetIrqMcuSampleRate(Soc_Aud_IRQ_MCU_MODE_IRQ2_MCU_MODE, substream->runtime->rate);
    SetIrqEnable(Soc_Aud_IRQ_MCU_MODE_IRQ2_MCU_MODE, true);

    SetSampleRate(Soc_Aud_Digital_Block_MEM_AWB, substream->runtime->rate);
    SetMemoryPathEnable(Soc_Aud_Digital_Block_MEM_AWB, true);
    SetMemoryPathEnable(Soc_Aud_Digital_Block_I2S_IN_2, true);

    // here to turn off digital part
    SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I00, Soc_Aud_InterConnectionOutput_O05);
    SetConnection(Soc_Aud_InterCon_Connection, Soc_Aud_InterConnectionInput_I01, Soc_Aud_InterConnectionOutput_O06);

    EnableAfe(true);
}
Exemple #27
0
void AudDrv_ADC_Clk_Off(void)
{
    //PRINTK_AUDDRV("+AudDrv_ADC_Clk_Off, Aud_ADC_Clk_cntr:%d \n", Aud_ADC_Clk_cntr);
    mutex_lock(&auddrv_pmic_mutex);
    Aud_ADC_Clk_cntr--;
    if (Aud_ADC_Clk_cntr == 0)
    {
        PRINTK_AUDDRV("+AudDrv_ADC_Clk_On disable_clock ADC clk(%x)\n", Aud_ADC_Clk_cntr);
        Afe_Set_Reg(AUDIO_TOP_CON0, 1 << 24 , 1 << 24);
    }
    if (Aud_ADC_Clk_cntr < 0)
    {
        PRINTK_AUDDRV("!! AudDrv_ADC_Clk_Off, Aud_ADC_Clk_cntr<0 (%d) \n", Aud_ADC_Clk_cntr);
        Aud_ADC_Clk_cntr = 0;
    }
    mutex_unlock(&auddrv_pmic_mutex);
    //PRINTK_AUDDRV("-AudDrv_ADC_Clk_Off, Aud_ADC_Clk_cntr:%d \n", Aud_ADC_Clk_cntr);
}
void AudDrv_ADC_Clk_On(void)
{
    //PRINTK_AUDDRV("+AudDrv_ADC_Clk_On, Aud_ADC_Clk_cntr:%d \n", Aud_ADC_Clk_cntr);
#if !defined(CONFIG_MTK_LEGACY)  
    int ret = 0;
#endif
    mutex_lock(&auddrv_pmic_mutex);

    if (Aud_ADC_Clk_cntr == 0)
    {
        PRINTK_AUDDRV("+AudDrv_ADC_Clk_On enable_clock ADC clk(%x)\n", Aud_ADC_Clk_cntr);
//        Afe_Set_Reg(AUDIO_TOP_CON0, 0 << 24 , 1 << 24);
#ifdef PM_MANAGER_API
#if defined(CONFIG_MTK_LEGACY)
        if (enable_clock(MT_CG_AUDIO_ADC, "AUDIO"))
        {
            PRINTK_AUD_CLK("%s fail", __func__);
        }
#else
        if (paudclk->aud_adc_clk_status)
        {
            ret = clk_prepare_enable(paudclk->aud_adc_clk);
            if (!ret)
            {
                pr_err("%s Aud enable_clock enable_clock ADC fail", __func__);
                BUG();
                return;
            }
        }
        else
        {
            pr_err("%s clk_status error Aud enable_clock ADC fail", __func__);
            BUG();
            return;                                    
        }        

#endif
#else
        Afe_Set_Reg(AUDIO_TOP_CON0, 0 << 24 , 1 << 24);
#endif
    }
    Aud_ADC_Clk_cntr++;
    mutex_unlock(&auddrv_pmic_mutex);
}
/*****************************************************************************
  * FUNCTION
  *  AudDrv_I2S_Clk_On / AudDrv_I2S_Clk_Off
  *
  * DESCRIPTION
  *  Enable/Disable analog part clock
  *
  *****************************************************************************/
void AudDrv_I2S_Clk_On(void)
{
    unsigned long flags;
    //PRINTK_AUD_CLK("+AudDrv_I2S_Clk_On, Aud_I2S_Clk_cntr:%d \n", Aud_I2S_Clk_cntr);
    spin_lock_irqsave(&auddrv_Clk_lock, flags);
    if (Aud_I2S_Clk_cntr == 0)
    {
#ifdef PM_MANAGER_API
        if (enable_clock(MT_CG_AUDIO_I2S, "AUDIO"))
        {
            PRINTK_AUD_ERROR("Aud enable_clock MT65XX_PDN_AUDIO_I2S fail !!!\n");
        }
#else
        Afe_Set_Reg(AUDIO_TOP_CON0, 0x00000040, 0x00000040);  //power on I2S clock
#endif
    }
    Aud_I2S_Clk_cntr++;
    spin_unlock_irqrestore(&auddrv_Clk_lock, flags);
}
Exemple #30
0
void AudDrv_APLL2Tuner_Clk_Off(void)
{
    unsigned long flags;
    spin_lock_irqsave(&auddrv_Clk_lock, flags);

    Aud_APLL2_Tuner_cntr--;
    if (Aud_APLL2_Tuner_cntr == 0)
    {
        Afe_Set_Reg(AUDIO_TOP_CON0, 0x1 << 20, 0x1 << 20);
        SetpllCfg(AP_PLL_CON5, 0x0<<1, 0x1<<1);
    }
    // handle for clock error
    else if (Aud_APLL2_Tuner_cntr < 0)
    {
        PRINTK_AUD_ERROR("!! AudDrv_APLL2Tuner_Clk_Off, Aud_APLL1_Tuner_cntr<0 (%d) \n", Aud_APLL2_Tuner_cntr);
        Aud_APLL2_Tuner_cntr = 0;
    }
    spin_unlock_irqrestore(&auddrv_Clk_lock, flags);
}