m_ctc->trg1(0); m_ctc->trg2(1); m_ctc->trg2(0); } WRITE_LINE_MEMBER( bullet_state::dart_rxtxca_w ) { m_dart->txca_w(state); m_dart->rxca_w(state); } static Z80CTC_INTERFACE( ctc_intf ) { DEVCB_CPU_INPUT_LINE(Z80_TAG, INPUT_LINE_IRQ0), DEVCB_DRIVER_LINE_MEMBER(bullet_state, dart_rxtxca_w), DEVCB_DEVICE_LINE_MEMBER(Z80DART_TAG, z80dart_device, rxtxcb_w), DEVCB_DEVICE_LINE_MEMBER(DEVICE_SELF, z80ctc_device, trg3) }; //------------------------------------------------- // Z80DART_INTERFACE( dart_intf ) //------------------------------------------------- WRITE_LINE_MEMBER( bullet_state::dartardy_w ) { m_dartardy = state; update_dma_rdy(); }
/* Z80-CTC Interface */ WRITE_LINE_MEMBER( poly880_state::ctc_z0_w ) { // SEND } WRITE_LINE_MEMBER( poly880_state::ctc_z1_w ) { } static Z80CTC_INTERFACE( ctc_intf ) { 0, /* timer disables */ DEVCB_CPU_INPUT_LINE(Z80_TAG, INPUT_LINE_IRQ0), /* interrupt handler */ DEVCB_DRIVER_LINE_MEMBER(poly880_state, ctc_z0_w), /* ZC/TO0 callback */ DEVCB_DRIVER_LINE_MEMBER(poly880_state, ctc_z1_w), /* ZC/TO1 callback */ DEVCB_LINE(z80ctc_trg3_w) /* ZC/TO2 callback */ }; /* Z80-PIO Interface */ WRITE8_MEMBER( poly880_state::pio1_pa_w ) { /* bit signal description PA0 SD0 segment E PA1 SD1 segment D PA2 SD2 segment C
INPUT_PORTS_END static IRQ_CALLBACK(multi16_irq_callback) { return pic8259_acknowledge( device->machine().device("pic8259") ); } WRITE_LINE_MEMBER( multi16_state::multi16_set_int_line ) { //printf("%02x\n",interrupt); cputag_set_input_line(machine(), "maincpu", 0, state ? HOLD_LINE : CLEAR_LINE); } static const struct pic8259_interface multi16_pic8259_config = { DEVCB_DRIVER_LINE_MEMBER(multi16_state, multi16_set_int_line), DEVCB_LINE_GND, DEVCB_NULL }; static MACHINE_START(multi16) { device_set_irq_callback(machine.device("maincpu"), multi16_irq_callback); } static MACHINE_RESET(multi16) { } static const mc6845_interface mc6845_intf =
if (m_enable_rtc_int && m_rtc_int) { // trigger RTC interrupt m_maincpu->set_input_line(INPUT_LINE_NMI, ASSERT_LINE); } } } static const mc6845_interface mc6845_intf = { SCREEN_TAG, 8, NULL, trs80m2_update_row, NULL, DEVCB_DRIVER_LINE_MEMBER(trs80m2_state, de_w), DEVCB_NULL, DEVCB_NULL, DEVCB_DRIVER_LINE_MEMBER(trs80m2_state, vsync_w), NULL }; void trs80m2_state::video_start() { // find memory regions m_char_rom = memregion(MC6845_TAG)->base(); // allocate memory m_video_ram.allocate(0x800); }
WRITE_LINE_MEMBER( tandy2k_state::vpac_drb_w ) { m_drb0->tog_w(state); m_drb1->tog_w(state); } static CRT9007_INTERFACE( vpac_intf ) { SCREEN_TAG, 10, DEVCB_DEVICE_LINE(I8259A_1_TAG, pic8259_ir1_w), DEVCB_NULL, // DMAR 80186 HOLD DEVCB_DEVICE_LINE_MEMBER(CRT9021B_TAG, crt9021_device, vsync_w), // VS DEVCB_NULL, // HS DEVCB_DRIVER_LINE_MEMBER(tandy2k_state, vpac_vlt_w), // VLT DEVCB_DEVICE_LINE_MEMBER(CRT9021B_TAG, crt9021_device, cursor_w), // CURS DEVCB_DRIVER_LINE_MEMBER(tandy2k_state, vpac_drb_w), // DRB DEVCB_DEVICE_LINE_MEMBER(CRT9021B_TAG, crt9021_device, retbl_w), // CBLANK DEVCB_DEVICE_LINE_MEMBER(CRT9021B_TAG, crt9021_device, slg_w), // SLG DEVCB_DEVICE_LINE_MEMBER(CRT9021B_TAG, crt9021_device, sld_w) // SLD }; static CRT9212_INTERFACE( drb0_intf ) { DEVCB_NULL, // ROF DEVCB_NULL, // WOF DEVCB_DEVICE_LINE_MEMBER(CRT9007_TAG, crt9007_device, vlt_r), // REN DEVCB_DEVICE_LINE_MEMBER(CRT9007_TAG, crt9007_device, wben_r), // WEN DEVCB_LINE_VCC // WEN2 };
{ m_speaker_en = state; } WRITE_LINE_MEMBER( v6809_state::speaker_w ) { // if (m_speaker_en) // m_speaker->level_w(state); } static const ptm6840_interface mc6840_intf = { XTAL_16MHz / 4, { 4000000/14, 4000000/14, 4000000/14/8 }, { DEVCB_NULL, DEVCB_DRIVER_LINE_MEMBER(v6809_state, speaker_w), DEVCB_DRIVER_LINE_MEMBER(v6809_state, speaker_en_w) }, DEVCB_CPU_INPUT_LINE("maincpu", M6809_IRQ_LINE) }; static ACIA6850_INTERFACE( mc6850_intf ) { 10, 10, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL }; static SLOT_INTERFACE_START( v6809_floppies ) SLOT_INTERFACE( "525dd", FLOPPY_525_DD )
static ADDRESS_MAP_START( sound_portmap, AS_IO, 8, cchasm_state ) ADDRESS_MAP_GLOBAL_MASK(0xff) AM_RANGE(0x00, 0x03) AM_DEVREADWRITE("ctc", z80ctc_device, read, write) ADDRESS_MAP_END WRITE_LINE_MEMBER(cchasm_state::cchasm_6840_irq) { m_maincpu->set_input_line(4, state ? ASSERT_LINE : CLEAR_LINE); } static const ptm6840_interface cchasm_6840_intf = { CCHASM_68K_CLOCK/10, { 0, CCHASM_68K_CLOCK / 10, 0 }, { DEVCB_NULL, DEVCB_NULL, DEVCB_NULL }, DEVCB_DRIVER_LINE_MEMBER(cchasm_state,cchasm_6840_irq) }; /************************************* * * Port definitions * *************************************/ static INPUT_PORTS_START( cchasm ) PORT_START("DSW") PORT_DIPNAME( 0x01, 0x01, DEF_STR( Lives ) ) PORT_DIPSETTING( 0x01, "3" ) PORT_DIPSETTING( 0x00, "5" ) PORT_DIPNAME( 0x06, 0x06, DEF_STR( Bonus_Life ) ) PORT_DIPSETTING( 0x06, "40000" )
} WRITE_LINE_MEMBER( mc80_state::ctc_z1_w ) { } WRITE_LINE_MEMBER(mc80_state::ctc_z2_w) { downcast<z80ctc_device *>(machine().device("z80ctc"))->trg0(state); downcast<z80ctc_device *>(machine().device("z80ctc"))->trg1(state); } Z80CTC_INTERFACE( mc8020_ctc_intf ) { DEVCB_CPU_INPUT_LINE("maincpu", INPUT_LINE_IRQ0), DEVCB_DRIVER_LINE_MEMBER(mc80_state, ctc_z0_w), DEVCB_DRIVER_LINE_MEMBER(mc80_state, ctc_z1_w), DEVCB_DRIVER_LINE_MEMBER(mc80_state,ctc_z2_w) }; READ8_MEMBER( mc80_state::mc80_port_b_r ) { return 0; } READ8_MEMBER( mc80_state::mc80_port_a_r ) { return 0; }
WRITE_LINE_MEMBER(pp01_state::pp01_pit_out0) { } WRITE_LINE_MEMBER(pp01_state::pp01_pit_out1) { } const struct pit8253_config pp01_pit8253_intf = { { { 0, DEVCB_NULL, DEVCB_DRIVER_LINE_MEMBER(pp01_state,pp01_pit_out0) }, { 2000000, DEVCB_NULL, DEVCB_DRIVER_LINE_MEMBER(pp01_state,pp01_pit_out1) }, { 2000000, DEVCB_NULL, DEVCB_DEVICE_LINE("pit8253", pit8253_clk0_w) } } }; READ8_MEMBER(pp01_state::pp01_8255_porta_r)
TIMER_DEVICE_CALLBACK_MEMBER(mstation_state::mstation_kb_timer) { m_irq |= (1<<1); refresh_ints(); } PALETTE_INIT_MEMBER(mstation_state, mstation) { palette.set_pen_color(0, rgb_t(138, 146, 148)); palette.set_pen_color(1, rgb_t(92, 83, 88)); } static RP5C01_INTERFACE( rtc_intf ) { DEVCB_DRIVER_LINE_MEMBER(mstation_state, rtc_irq) }; static MACHINE_CONFIG_START( mstation, mstation_state ) /* basic machine hardware */ MCFG_CPU_ADD("maincpu",Z80, XTAL_4MHz) //unknown clock MCFG_CPU_PROGRAM_MAP(mstation_mem) MCFG_CPU_IO_MAP(mstation_io) /* video hardware */ MCFG_SCREEN_ADD("screen", LCD) MCFG_SCREEN_REFRESH_RATE(50) MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) /* not accurate */ MCFG_SCREEN_UPDATE_DRIVER(mstation_state, screen_update) MCFG_SCREEN_SIZE(320, 128) MCFG_SCREEN_VISIBLE_AREA(0, 320-1, 0, 128-1)
DEVCB_CPU_INPUT_LINE("sub", INPUT_LINE_IRQ0), DEVCB_DRIVER_MEMBER(senjyo_state,pio_pa_r), DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL }; /* z80 ctc */ Z80CTC_INTERFACE( senjyo_ctc_intf ) { DEVCB_CPU_INPUT_LINE("sub", INPUT_LINE_IRQ0), /* interrupt handler */ DEVCB_DEVICE_LINE_MEMBER("z80ctc", z80ctc_device, trg1), /* ZC/TO0 callback */ DEVCB_NULL, /* ZC/TO1 callback */ DEVCB_DRIVER_LINE_MEMBER(senjyo_state, sound_line_clock) /* ZC/TO2 callback */ }; WRITE_LINE_MEMBER(senjyo_state::sound_line_clock) { if (state != 0) { m_dac->write_signed16(2184 * 2 * ((m_sound_state & 8) ? m_single_volume : 0)); m_sound_state++; } } WRITE8_MEMBER(senjyo_state::senjyo_volume_w) { m_single_volume = data & 0x0f; }
WRITE_LINE_MEMBER( c1pmf_state::osi470_pia_cb2_w ) { } static const pia6821_interface osi470_pia_intf = { DEVCB_DRIVER_MEMBER(c1pmf_state, osi470_pia_pa_r), DEVCB_NULL, // read8_machine_func in_b_func, DEVCB_NULL, // read8_machine_func in_ca1_func, DEVCB_NULL, // read8_machine_func in_cb1_func, DEVCB_NULL, // read8_machine_func in_ca2_func, DEVCB_NULL, // read8_machine_func in_cb2_func, DEVCB_DRIVER_MEMBER(c1pmf_state, osi470_pia_pa_w), DEVCB_DRIVER_MEMBER(c1pmf_state, osi470_pia_pb_w), DEVCB_NULL, // write8_machine_func out_ca2_func, DEVCB_DRIVER_LINE_MEMBER(c1pmf_state, osi470_pia_cb2_w), DEVCB_NULL, // void (*irq_a_func)(int state), DEVCB_NULL, // void (*irq_b_func)(int state), }; static const pia6821_interface pia_dummy_intf = { DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL,
PORT_MODIFY("DSW") PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unused ) ) PORT_DIPLOCATION("DSW:4") PORT_DIPSETTING( 0x80, DEF_STR( Off ) ) PORT_DIPSETTING( 0x00, DEF_STR( On ) ) INPUT_PORTS_END WRITE_LINE_MEMBER(sg1000a_state::vdp_interrupt) { cputag_set_input_line(machine(), "maincpu", INPUT_LINE_IRQ0, state); } static TMS9928A_INTERFACE(sg1000a_tms9928a_interface) { "screen", 0x4000, DEVCB_DRIVER_LINE_MEMBER(sg1000a_state,vdp_interrupt) }; WRITE8_MEMBER(sg1000a_state::sg1000a_coin_counter_w) { coin_counter_w(machine(), 0, data & 0x01); } static I8255_INTERFACE( ppi8255_intf ) { DEVCB_INPUT_PORT("P1"), DEVCB_NULL, DEVCB_INPUT_PORT("P2"), DEVCB_NULL, DEVCB_INPUT_PORT("DSW"), DEVCB_DRIVER_MEMBER(sg1000a_state,sg1000a_coin_counter_w)
//------------------------------------------------- // COM8116_INTERFACE( brg_intf ) //------------------------------------------------- WRITE_LINE_MEMBER( super6_state::fr_w ) { z80dart_rxca_w(m_dart, state); z80dart_txca_w(m_dart, state); z80ctc_trg1_w(m_ctc, state); } static COM8116_INTERFACE( brg_intf ) { DEVCB_NULL, DEVCB_DRIVER_LINE_MEMBER(super6_state, fr_w), DEVCB_DEVICE_LINE(Z80DART_TAG, z80dart_rxtxcb_w), { 6336, 4224, 2880, 2355, 2112, 1056, 528, 264, 176, 158, 132, 88, 66, 44, 33, 16 }, // from WD1943-00 datasheet { 6336, 4224, 2880, 2355, 2112, 1056, 528, 264, 176, 158, 132, 88, 66, 44, 33, 16 }, }; //------------------------------------------------- // floppy_interface super6_floppy_interface //------------------------------------------------- static const floppy_interface super6_floppy_interface = { DEVCB_NULL, DEVCB_NULL, DEVCB_NULL,
16*16 }; static GFXDECODE_START( tokib ) GFXDECODE_ENTRY( "gfx1", 0, tokib_charlayout, 16*16, 16 ) GFXDECODE_ENTRY( "gfx2", 0, tokib_spriteslayout, 0*16, 16 ) GFXDECODE_ENTRY( "gfx3", 0, tokib_tilelayout, 32*16, 16 ) GFXDECODE_ENTRY( "gfx4", 0, tokib_tilelayout, 48*16, 16 ) GFXDECODE_END /*****************************************************************************/ static const msm5205_interface msm5205_config = { DEVCB_DRIVER_LINE_MEMBER(toki_state,toki_adpcm_int), /* interrupt function */ MSM5205_S96_4B /* 4KHz */ }; static MACHINE_CONFIG_START( toki, toki_state ) /* KOYO 20.000MHz near the cpu */ /* basic machine hardware */ MCFG_CPU_ADD("maincpu", M68000,XTAL_20MHz /2) /* verified on pcb */ MCFG_CPU_PROGRAM_MAP(toki_map) MCFG_CPU_VBLANK_INT_DRIVER("screen", toki_state, irq1_line_hold)/* VBL */ SEIBU_SOUND_SYSTEM_CPU(XTAL_14_31818MHz/4) /* verifed on pcb */ /* video hardware */ MCFG_BUFFERED_SPRITERAM16_ADD("spriteram")
if (m_data_selector_rts == 0 && m_data_selector_dtr == 0) m_sio->txca_w(state); // transmit and receive clock via timer 2 if (m_data_selector_rts == 1 && m_data_selector_dtr == 0) { m_sio->txca_w(state); m_sio->rxca_w(state); } } static const struct pit8253_interface apricot_pit8253_intf = { { { XTAL_4MHz / 16, DEVCB_LINE_VCC, DEVCB_DEVICE_LINE_MEMBER("ic31", pic8259_device, ir6_w) }, { XTAL_4MHz / 2, DEVCB_LINE_VCC, DEVCB_DRIVER_LINE_MEMBER(apricot_state, timer_out1) }, { XTAL_4MHz / 2, DEVCB_LINE_VCC, DEVCB_DRIVER_LINE_MEMBER(apricot_state, timer_out2) } } }; static Z80SIO_INTERFACE( apricot_z80sio_intf ) { 0, 0, XTAL_4MHz / 16, XTAL_4MHz / 16, // channel a DEVCB_DEVICE_LINE_MEMBER("rs232", serial_port_device, tx), DEVCB_DEVICE_LINE_MEMBER("rs232", rs232_port_device, dtr_w), DEVCB_DEVICE_LINE_MEMBER("rs232", rs232_port_device, rts_w), DEVCB_DEVICE_LINE_MEMBER("ic71", i8089_device, drq2_w), DEVCB_NULL,
output_set_value("led_halt", ~data & I8085_STATUS_HLTA); // operate the HOLD LED - this should connect to the HLDA pin, // but it isn't emulated, using WO instead (whatever that does). output_set_value("led_hold", data & I8085_STATUS_WO); } WRITE_LINE_MEMBER( mmd1_state::mmd2_inte_callback ) { // operate the INTE LED output_set_value("led_inte", state); } static I8085_CONFIG( mmd2_cpu_config ) { DEVCB_DRIVER_MEMBER(mmd1_state, mmd2_status_callback), /* Status changed callback */ DEVCB_DRIVER_LINE_MEMBER(mmd1_state, mmd2_inte_callback), /* INTE changed callback */ DEVCB_NULL, /* SID changed callback (I8085A only) */ DEVCB_NULL /* SOD changed callback (I8085A only) */ }; MACHINE_RESET_MEMBER(mmd1_state,mmd1) { m_return_code = 0xff; } MACHINE_RESET_MEMBER(mmd1_state,mmd2) { membank("bank1")->set_entry(0); membank("bank2")->set_entry(0); membank("bank3")->set_entry(0); membank("bank4")->set_entry(0);
READ8_MEMBER( vip_state::dma_r ) { return m_exp->dma_r(space, offset); } WRITE8_MEMBER( vip_state::dma_w ) { m_vdc->dma_w(space, offset, data); m_exp->dma_w(space, offset, data); } static COSMAC_INTERFACE( cosmac_intf ) { DEVCB_LINE_VCC, DEVCB_DRIVER_LINE_MEMBER(vip_state, clear_r), DEVCB_DRIVER_LINE_MEMBER(vip_state, ef1_r), DEVCB_DRIVER_LINE_MEMBER(vip_state, ef2_r), DEVCB_DRIVER_LINE_MEMBER(vip_state, ef3_r), DEVCB_DRIVER_LINE_MEMBER(vip_state, ef4_r), DEVCB_DRIVER_LINE_MEMBER(vip_state, q_w), DEVCB_DRIVER_MEMBER(vip_state, dma_r), DEVCB_DRIVER_MEMBER(vip_state, dma_w), vip_sc_w, DEVCB_NULL, DEVCB_NULL }; //------------------------------------------------- // CDP1861_INTERFACE( vdc_intf )
m_x_pia_irqa = state; update_irq(); } WRITE_LINE_MEMBER( tek4051_state::x_pia_irqb_w ) { m_x_pia_irqb = state; update_irq(); } static const pia6821_interface x_pia_intf = { DEVCB_DRIVER_MEMBER(tek4051_state, x_pia_pa_r), DEVCB_NULL, DEVCB_NULL, DEVCB_DRIVER_LINE_MEMBER(tek4051_state, viewcause_r), DEVCB_NULL, DEVCB_NULL, DEVCB_DRIVER_MEMBER(tek4051_state, x_pia_pa_w), DEVCB_DRIVER_MEMBER(tek4051_state, x_pia_pb_w), DEVCB_DRIVER_LINE_MEMBER(tek4051_state, adot_w), DEVCB_DRIVER_LINE_MEMBER(tek4051_state, bufclk_w), DEVCB_DRIVER_LINE_MEMBER(tek4051_state, x_pia_irqa_w), DEVCB_DRIVER_LINE_MEMBER(tek4051_state, x_pia_irqb_w) }; //------------------------------------------------- // pia6821_interface y_pia_intf //-------------------------------------------------
static ADDRESS_MAP_START( draco_page_ram, 0, 8 ) ADDRESS_MAP_UNMAP_HIGH AM_RANGE(0x000, 0x7ff) AM_RAM ADDRESS_MAP_END /* CDP1869 Interface */ static CDP1869_INTERFACE( destryer_cdp1869_intf ) { SCREEN_TAG, 0, CDP1869_PAL, cidelsa_pcb_r, cidelsa_charram_r, cidelsa_charram_w, DEVCB_DRIVER_LINE_MEMBER(cidelsa_state, prd_w) }; static CDP1869_INTERFACE( altair_cdp1869_intf ) { SCREEN_TAG, 0, CDP1869_PAL, cidelsa_pcb_r, cidelsa_charram_r, cidelsa_charram_w, DEVCB_DRIVER_LINE_MEMBER(cidelsa_state, prd_w) }; static CDP1869_INTERFACE( draco_cdp1869_intf ) {
DEVCB_DRIVER_MEMBER(mirage_state, mirage_via_write_porta), DEVCB_DRIVER_MEMBER(mirage_state, mirage_via_write_portb), DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_CPU_INPUT_LINE("maincpu", M6809_IRQ_LINE) }; static ACIA6850_INTERFACE( mirage_acia6850_interface ) { 0, // tx clock 0, // rx clock DEVCB_NULL, // rx out DEVCB_NULL, // rts out DEVCB_DRIVER_LINE_MEMBER(mirage_state, acia_irq_w) }; static MACHINE_CONFIG_START( mirage, mirage_state ) MCFG_CPU_ADD("maincpu", M6809E, 4000000) MCFG_CPU_PROGRAM_MAP(mirage_map) MCFG_DEFAULT_LAYOUT( layout_mirage ) MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker") MCFG_ES5503_ADD("es5503", 7000000, 2, mirage_doc_irq, mirage_adc_read) MCFG_SOUND_ROUTE(0, "lspeaker", 1.0) MCFG_SOUND_ROUTE(1, "rspeaker", 1.0) MCFG_VIA6522_ADD("via6522", 1000000, mirage_via)
} z80pio_bstb_w(m_pio1, 1); z80pio_bstb_w(m_pio1, 0); } } static Z80PIO_INTERFACE( pio1_intf ) { DEVCB_CPU_INPUT_LINE(Z80_TAG, INPUT_LINE_IRQ0), /* callback when change interrupt status */ DEVCB_DRIVER_MEMBER(c80_state, pio1_pa_r), /* port A read callback */ DEVCB_DRIVER_MEMBER(c80_state, pio1_pa_w), /* port A write callback */ DEVCB_NULL, /* portA ready active callback */ DEVCB_NULL, /* port B read callback */ DEVCB_DRIVER_MEMBER(c80_state, pio1_pb_w), /* port B write callback */ DEVCB_DRIVER_LINE_MEMBER(c80_state, pio1_brdy_w) /* portB ready active callback */ }; static Z80PIO_INTERFACE( pio2_intf ) { DEVCB_CPU_INPUT_LINE(Z80_TAG, INPUT_LINE_IRQ0), /* callback when change interrupt status */ DEVCB_NULL, /* port A read callback */ DEVCB_NULL, /* port A write callback */ DEVCB_NULL, /* portA ready active callback */ DEVCB_NULL, /* port B read callback */ DEVCB_NULL, /* port B write callback */ DEVCB_NULL /* portB ready active callback */ }; /* Z80 Daisy Chain */
DEVCB_NULL, DEVCB_NULL, DEVCB_NULL, DEVCB_NULL }; WRITE_LINE_MEMBER(goal92_state::goal92_adpcm_int) { m_msm->data_w(m_msm5205next); m_msm5205next >>= 4; m_adpcm_toggle^= 1; if (m_adpcm_toggle) m_audiocpu->set_input_line(INPUT_LINE_NMI, PULSE_LINE); } static const msm5205_interface msm5205_config = { DEVCB_DRIVER_LINE_MEMBER(goal92_state,goal92_adpcm_int), /* interrupt function */ MSM5205_S96_4B /* 4KHz 4-bit */ }; static const gfx_layout layout_8x8x4 = { 8,8, RGN_FRAC(1,4), 4, { RGN_FRAC(3,4),RGN_FRAC(2,4),RGN_FRAC(1,4),RGN_FRAC(0,4) }, { STEP8(0,1) }, { STEP8(0,8) }, 8*8 }; static const gfx_layout layout_16x16x4 =