/** * GNB Scs interface * * * * @param[in] StdHeader Standard configuration header * @retval AGESA_STATUS */ AGESA_STATUS GnbScsInterfaceML ( IN AMD_CONFIG_PARAMS *StdHeader ) { AGESA_STATUS Status; AGESA_STATUS AgesaStatus; GNB_HANDLE *GnbHandle; UINTN ScsDataAddress; UINTN ScsDataSize; GNB_BUILD_OPTIONS_ML *GnbBuildOptionData; IDS_HDT_CONSOLE (GNB_TRACE, "GnbScsInterfaceML Enter\n"); AgesaStatus = AGESA_SUCCESS; Status = AGESA_SUCCESS; GnbBuildOptionData = GnbLocateHeapBuffer (AMD_GNB_BUILD_OPTIONS_HANDLE, StdHeader); ASSERT (GnbBuildOptionData != NULL); if ((GnbBuildOptionData->CfgUseSMUServices == TRUE) && (GnbBuildOptionData->GnbCommonOptions.CfgScsSupport == TRUE)) { IDS_HDT_CONSOLE (GNB_TRACE, "GnbScsInterfaceML Supported\n"); GnbHandle = GnbGetHandle (StdHeader); Status = GnbGetScsDataML (&ScsDataAddress, &ScsDataSize); ASSERT (ScsDataAddress != NULL); Status = GnbSmuLoadScsDataV7 (GnbHandle, (UINT8 *)ScsDataAddress, StdHeader); AGESA_STATUS_UPDATE (Status, AgesaStatus); } IDS_HDT_CONSOLE (GNB_TRACE, "GnbScsInterfaceML Exit [0x%x]\n", Status); return AgesaStatus; }
AGESA_STATUS GnbEarlierInterfaceML ( IN AMD_CONFIG_PARAMS *StdHeader ) { AGESA_STATUS Status; AGESA_STATUS AgesaStatus; GNB_HANDLE *GnbHandle; UINT32 D0F0xBC_xC00C002C; FIRMWARE_HEADER_V7 *SmuFwHeader; UINTN SmuFwSize; GNB_BUILD_OPTIONS_ML *GnbBuildOptionData; UINT32 PspMBox; AgesaStatus = AGESA_SUCCESS; Status = AGESA_SUCCESS; IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlierInterfaceML Enter\n"); GnbHandle = GnbGetHandle (StdHeader); Status = GnbProcessTable ( GnbHandle, GnbEarlierInitTableBeforeSmuML, 0, 0, StdHeader ); AGESA_STATUS_UPDATE (Status, AgesaStatus); SmuFwHeader = NULL; GnbRegisterReadML (GnbHandle, D0F0xBC_xC00C002C_TYPE, D0F0xBC_xC00C002C_ADDRESS, &D0F0xBC_xC00C002C, 0, StdHeader); D0F0xBC_xC00C002C &= (BIT1 + BIT2 + BIT3 + BIT4 + BIT5); IDS_HDT_CONSOLE (GNB_TRACE, " D0F0xBC_xC00C002C = 0x%x\n", D0F0xBC_xC00C002C); Status = GnbLoadBuildOptionDataML (StdHeader); AGESA_STATUS_UPDATE (Status, AgesaStatus); GnbBuildOptionData = GnbLocateHeapBuffer (AMD_GNB_BUILD_OPTIONS_HANDLE, StdHeader); ASSERT (GnbBuildOptionData != NULL); //Load the SMU for non secure part & blank part if ((D0F0xBC_xC00C002C == 0) || (D0F0xBC_xC00C002C == BIT5 + BIT3)) { Status = GnbGetSmuFirmwareML ((UINTN *)&SmuFwHeader, &SmuFwSize); ASSERT (SmuFwHeader != NULL); AGESA_STATUS_UPDATE (Status, AgesaStatus); Status = GnbSmuFirmwareLoadV7 (GnbHandle, SmuFwHeader, StdHeader); AGESA_STATUS_UPDATE (Status, AgesaStatus); } else { Status = GnbPspMBoxRead (&PspMBox, GnbHandle, StdHeader); IDS_HDT_CONSOLE (GNB_TRACE, " PSP Mailbox Status = 0x%x\n", PspMBox); if (Status == AGESA_SUCCESS) { if ((PspMBox & MBOX_STATUS_RECOVERY) == MBOX_STATUS_RECOVERY) { /// SET CfgUseSMUServices flag for recovery mode GnbBuildOptionData->CfgUseSMUServices = FALSE; } } } IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlierInterfaceML Exit [0x%x]\n", Status); return AgesaStatus; }
AGESA_STATUS PcieAlibUpdatePcieData ( IN OUT VOID *DataBuffer, IN AMD_CONFIG_PARAMS *StdHeader ) { PCIe_PLATFORM_CONFIG *Pcie; AMD_LATE_PARAMS *LateParamsPtr; AGESA_STATUS Status; BOOLEAN DcTdpEnable; GNB_BUILD_OPTIONS_COMMON *GnbCommonOptions; IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdatePcieData Enter\n"); ASSERT (DataBuffer != NULL); Status = AGESA_SUCCESS; GnbCommonOptions = GnbLocateHeapBuffer (AMD_GNB_BUILD_OPTIONS_HANDLE, StdHeader); if (GnbCommonOptions != NULL) { DcTdpEnable = GnbCommonOptions->CfgDcTdpEnable; } else { GnbCommonOptions = (GNB_BUILD_OPTIONS_COMMON*) GnbFmGnbBuildOptions (StdHeader); DcTdpEnable = GnbCommonOptions->CfgDcTdpEnable; } // // Locate PCIe platform config // if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) { // // Update policy data // ((ALIB_DATA *) DataBuffer)->Data.Data.PsppPolicy = Pcie->PsppPolicy; // // Update data for each port // PcieConfigRunProcForAllEngines ( DESCRIPTOR_PCIE_ENGINE, PcieAlibUpdatePciePortDataCallback, DataBuffer, Pcie ); } else { ASSERT (FALSE); Status = AGESA_FATAL; } LateParamsPtr = (AMD_LATE_PARAMS *) StdHeader; ((ALIB_DATA *) DataBuffer)->Data.Data.DockedTdpHeadroom = LateParamsPtr->GnbLateConfiguration.DockedTdpHeadroom; IDS_HDT_CONSOLE (GNB_TRACE, " DockedTdpHeadroom = %02x\n", LateParamsPtr->GnbLateConfiguration.DockedTdpHeadroom); IDS_HDT_CONSOLE (GNB_TRACE, " DcTdpEnable = %x\n", DcTdpEnable); ((ALIB_DATA *) DataBuffer)->Data.Data.DcTdpEnable = DcTdpEnable; IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdatePcieData Exit\n"); return Status; }
AGESA_STATUS GfxLocateConfigData ( IN AMD_CONFIG_PARAMS *StdHeader, OUT GFX_PLATFORM_CONFIG **Gfx ) { *Gfx = GnbLocateHeapBuffer (AMD_GFX_PLATFORM_CONFIG_HANDLE, StdHeader); if (*Gfx == NULL) { IDS_ERROR_TRAP; return AGESA_FATAL; } (*Gfx)->StdHeader = /* (PVOID) */(UINT32) StdHeader; return AGESA_SUCCESS; }
AGESA_STATUS PcieAlibUpdateVoltageData ( IN OUT VOID *DataBuffer, IN AMD_CONFIG_PARAMS *StdHeader ) { PP_FUSE_ARRAY_V2 *PpFuseArray; AGESA_STATUS Status; ALIB_DATA *AlibData; IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdateVoltageData Enter\n"); Status = AGESA_SUCCESS; ASSERT (DataBuffer != NULL); AlibData = (ALIB_DATA *) DataBuffer; // // Locate Fuse table // PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); ASSERT (PpFuseArray != NULL); if (PpFuseArray != NULL) { // // Update GEN1 Vid // AlibData->Data.Data.PcieVidGen1 = PpFuseArray->VddNbVid[0]; // // Update GEN2 Vid // AlibData->Data.Data.PcieVidGen2 = PpFuseArray->VddNbVid[PpFuseArray->PcieGen2Vid]; // // Update GEN3 Vid // AlibData->Data.Data.PcieVidGen3 = PpFuseArray->VddNbVid[PpFuseArray->PcieGen3Vid]; // // Update DPM Mask // AlibData->Data.Data.DpmMask = (PpFuseArray->PerfFlag + 1); IDS_HDT_CONSOLE (GNB_TRACE, " DpmMask = %02x\n", AlibData->Data.Data.DpmMask); // // Update Boost data // AlibData->Data.Data.NumBoostStates = (PpFuseArray->NumBoostStates); IDS_HDT_CONSOLE (GNB_TRACE, " NumBoost = %02x\n", AlibData->Data.Data.NumBoostStates); } else { Status = AGESA_ERROR; } IDS_HDT_CONSOLE (GNB_TRACE, "PcieAlibUpdateVoltageData Exit\n"); return Status; }
VOID GfxGetUmaInfo ( OUT UMA_INFO *UmaInfo, IN AMD_CONFIG_PARAMS *StdHeader ) { UMA_INFO *MemUmaInfo; MemUmaInfo = GnbLocateHeapBuffer (AMD_UMA_INFO_HANDLE, StdHeader); if (MemUmaInfo == NULL) { LibAmdMemFill (UmaInfo, 0x00, sizeof (UMA_INFO), StdHeader); UmaInfo->UmaMode = UMA_NONE; } else { LibAmdMemCopy (UmaInfo, MemUmaInfo, sizeof (UMA_INFO), StdHeader); if ((UmaInfo->UmaBase == 0) || (UmaInfo->UmaSize == 0)) { UmaInfo->UmaMode = UMA_NONE; } } }
AGESA_STATUS PcieFmAlibBuildAcpiTable ( IN VOID *AlibSsdtPtr, IN AMD_CONFIG_PARAMS *StdHeader ) { AGESA_STATUS AgesaStatus; D18F4x15C_STRUCT D18F4x15C; PP_FUSE_ARRAY *PpFuseArray; UINT32 AmlObjName; VOID *AmlObjPtr; IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmAlibBuildAcpiTable Enter\n"); AgesaStatus = AGESA_SUCCESS; // Set voltage configuration PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); ASSERT (PpFuseArray != NULL); if (PpFuseArray != NULL) { GnbLibPciRead ( MAKE_SBDFO (0, 0, 0x18, 0x4, D18F4x15C_ADDRESS), AccessWidth32, &D18F4x15C.Value, StdHeader ); if (D18F4x15C.Field.BoostSrc != 0 || PpFuseArray->GpuBoostCap != 0) { // AmlObjName = 'B0DA'; AmlObjName = Int32FromChar ('A', 'D', '0', 'B'); AmlObjPtr = GnbLibFind (AlibSsdtPtr, ((ACPI_TABLE_HEADER*) &AlibSsdt[0])->TableLength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { *(UINT8*)((UINT8*) AmlObjPtr + 5) = 1; } else { AgesaStatus = AGESA_FATAL; } } } else { AgesaStatus = AGESA_FATAL; } IDS_HDT_CONSOLE (GNB_TRACE, "PcieFmAlibBuildAcpiTable Exit[0x%x]\n", AgesaStatus); return AgesaStatus; }
AGESA_STATUS GnbEarlyInterfaceML ( IN AMD_CONFIG_PARAMS *StdHeader ) { AGESA_STATUS Status; AGESA_STATUS AgesaStatus; GNB_HANDLE *GnbHandle; UINT32 Property; GNB_BUILD_OPTIONS_ML *GnbBuildOptionData; AgesaStatus = AGESA_SUCCESS; IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlyInterfaceML Enter\n"); GnbHandle = GnbGetHandle (StdHeader); GnbBuildOptionData = GnbLocateHeapBuffer (AMD_GNB_BUILD_OPTIONS_HANDLE, StdHeader); ASSERT (GnbBuildOptionData != NULL); Property = TABLE_PROPERTY_DEFAULT; Property |= UserOptions.CfgGnbSyncFloodPinAsNmi ? TABLE_PROPERTY_NMI_SYNCFLOOD : 0; IDS_OPTION_HOOK (IDS_GNB_PROPERTY, &Property, StdHeader); IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PACKAGE_POWER_CONFIG, GnbHandle, StdHeader); GnbInitSmuBiosTableML (StdHeader); Status = GnbProcessTable ( GnbHandle, GnbEarlyInitTableML, Property, 0, StdHeader ); AGESA_STATUS_UPDATE (Status, AgesaStatus); if (GnbBuildOptionData->CfgUseSMUServices == TRUE) { GnbRequestVddNbPminML (GnbHandle, StdHeader); } Status = GfxGBifEnableML (StdHeader); ASSERT (Status == AGESA_SUCCESS); IDS_HDT_CONSOLE (GNB_TRACE, "GnbEarlyInterfaceML Exit [0x%x]\n", AgesaStatus); return AgesaStatus; }
/** * PCIe Post Init * * * * @param[in] StdHeader Standard configuration header * @retval AGESA_STATUS */ AGESA_STATUS PciePostInterfaceML ( IN AMD_CONFIG_PARAMS *StdHeader ) { AGESA_STATUS AgesaStatus; AGESA_STATUS Status; PCIe_PLATFORM_CONFIG *Pcie; GNB_BUILD_OPTIONS_ML *GnbBuildOptionData; IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInterfaceML Enter\n"); AgesaStatus = AGESA_SUCCESS; Status = PcieLocateConfigurationData (StdHeader, &Pcie); IDS_OPTION_HOOK (IDS_BEFORE_GEN2_INIT, Pcie, StdHeader); AGESA_STATUS_UPDATE (Status, AgesaStatus); GnbBuildOptionData = GnbLocateHeapBuffer (AMD_GNB_BUILD_OPTIONS_HANDLE, StdHeader); ASSERT (GnbBuildOptionData != NULL); if ((Status == AGESA_SUCCESS) && (GnbBuildOptionData->CfgUseSMUServices == TRUE)) { PciePortsVisibilityControlV5 (UnhidePorts, Pcie); Status = PciePostInitML (Pcie); AGESA_STATUS_UPDATE (Status, AgesaStatus); ASSERT (Status == AGESA_SUCCESS); Status = PciePostPortInitML (Pcie); AGESA_STATUS_UPDATE (Status, AgesaStatus); ASSERT (Status == AGESA_SUCCESS); Status = PcieTrainingV2 (Pcie); AGESA_STATUS_UPDATE (Status, AgesaStatus); ASSERT (Status == AGESA_SUCCESS); IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_PCIE_PHY_CONFIG, Pcie, StdHeader); GnbSmuBiosTableGetPcieInfoML (StdHeader, Pcie); PciePortsVisibilityControlV5 (HidePorts, Pcie); } IDS_HDT_CONSOLE (GNB_TRACE, "PciePostInterfaceML Exit [0x%x]\n", AgesaStatus); return AgesaStatus; }
/** * Get min WRCK * * * @param[in] StdHeader Standard configuration header * @retval Min WRCK in 10 khZ */ UINT32 GfxLibGetWrCk ( IN AMD_CONFIG_PARAMS *StdHeader ) { PP_FUSE_ARRAY *PpFuseArray; UINT8 WrCk; PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); ASSERT (PpFuseArray != NULL); if (PpFuseArray != NULL) { if (PpFuseArray->WrCkDid == 0x0) { WrCk = 2; } else if (PpFuseArray->WrCkDid <= 0x10) { WrCk = PpFuseArray->WrCkDid + 1; } else if (PpFuseArray->WrCkDid <= 0x1C) { WrCk = 24 + 8 * (PpFuseArray->WrCkDid - 0x10); } else { WrCk = 128; } } else { WrCk = 2; } return 100 * 100 / WrCk; }
/** * Request boot up voltage * * * * @param[in] LinkCap Global GEN capability * @param[in] Pcie Pointer to PCIe configuration data area */ VOID PcieSetVoltageCZ ( IN PCIE_LINK_SPEED_CAP LinkCap, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT8 TargetVid; UINT8 MinVidIndex; UINT8 VddNbVid[8]; UINT8 Index; PP_FUSE_ARRAY_V2 *PpFuseArray; UINT32 Millivolt[6]; D0F0xBC_xC0014004_STRUCT D0F0xBC_xC0014004; D0F0xBC_xC0014007_STRUCT D0F0xBC_xC0014007; D0F0xBC_xC0014008_STRUCT D0F0xBC_xC0014008; D0F0xBC_xC00160C4_STRUCT D0F0xBC_xC00160C4; D0F0xBC_xC00160C7_STRUCT D0F0xBC_xC00160C7; D0F0xBC_xC00160C8_STRUCT D0F0xBC_xC00160C8; D0F0xBC_xC001706C_STRUCT D0F0xBC_xC001706C; IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetVoltageCZ Enter\n"); Index = 0; PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Pcie)); if (PpFuseArray == NULL) { GnbRegisterReadCZ (GnbGetHandle (GnbLibGetHeader (Pcie)), D0F0xBC_xC0014004_TYPE, D0F0xBC_xC0014004_ADDRESS, &D0F0xBC_xC0014004, 0, GnbLibGetHeader (Pcie)); GnbRegisterReadCZ (GnbGetHandle (GnbLibGetHeader (Pcie)), D0F0xBC_xC0014007_TYPE, D0F0xBC_xC0014007_ADDRESS, &D0F0xBC_xC0014007, 0, GnbLibGetHeader (Pcie)); GnbRegisterReadCZ (GnbGetHandle (GnbLibGetHeader (Pcie)), D0F0xBC_xC0014008_TYPE, D0F0xBC_xC0014008_ADDRESS, &D0F0xBC_xC0014008, 0, GnbLibGetHeader (Pcie)); GnbRegisterReadCZ (GnbGetHandle (GnbLibGetHeader (Pcie)), D0F0xBC_xC00160C4_TYPE, D0F0xBC_xC00160C4_ADDRESS, &D0F0xBC_xC00160C4, 0, GnbLibGetHeader (Pcie)); GnbRegisterReadCZ (GnbGetHandle (GnbLibGetHeader (Pcie)), D0F0xBC_xC00160C7_TYPE, D0F0xBC_xC00160C7_ADDRESS, &D0F0xBC_xC00160C7, 0, GnbLibGetHeader (Pcie)); GnbRegisterReadCZ (GnbGetHandle (GnbLibGetHeader (Pcie)), D0F0xBC_xC00160C8_TYPE, D0F0xBC_xC00160C8_ADDRESS, &D0F0xBC_xC00160C8, 0, GnbLibGetHeader (Pcie)); GnbRegisterReadCZ (GnbGetHandle (GnbLibGetHeader (Pcie)), D0F0xBC_xC001706C_TYPE, D0F0xBC_xC001706C_ADDRESS, &D0F0xBC_xC001706C, 0, GnbLibGetHeader (Pcie)); VddNbVid[0] = (UINT8) D0F0xBC_xC0014004.Field.GnbVid0; VddNbVid[1] = (UINT8) D0F0xBC_xC0014004.Field.GnbVid1; VddNbVid[2] = (UINT8) D0F0xBC_xC0014007.Field.GnbVid2; VddNbVid[3] = (UINT8) D0F0xBC_xC0014008.Field.GnbVid3; VddNbVid[4] = (UINT8) D0F0xBC_xC0014008.Field.GnbVid4; VddNbVid[5] = (UINT8) D0F0xBC_xC00160C4.Field.GnbVid5; VddNbVid[6] = (UINT8) D0F0xBC_xC00160C7.Field.GnbVid6; VddNbVid[7] = (UINT8) D0F0xBC_xC00160C8.Field.GnbVid7; if (LinkCap <= PcieGen2) { Index = (UINT8) D0F0xBC_xC001706C.Field.PcieGen2Vid; } else if (LinkCap >= PcieGen3) { Index = (UINT8) D0F0xBC_xC001706C.Field.PcieGen3Vid; } } else { VddNbVid[0] = PpFuseArray->VddNbVid[0]; VddNbVid[1] = PpFuseArray->VddNbVid[1]; VddNbVid[2] = PpFuseArray->VddNbVid[2]; VddNbVid[3] = PpFuseArray->VddNbVid[3]; VddNbVid[4] = PpFuseArray->VddNbVid[4]; VddNbVid[5] = PpFuseArray->VddNbVid[5]; VddNbVid[6] = PpFuseArray->VddNbVid[6]; VddNbVid[7] = PpFuseArray->VddNbVid[7]; if (LinkCap <= PcieGen2) { Index = PpFuseArray->PcieGen2Vid; } else if (LinkCap >= PcieGen3) { Index = PpFuseArray->PcieGen3Vid; } } if (LinkCap > PcieGen1) { ASSERT (VddNbVid[Index] != 0); TargetVid = VddNbVid[Index]; } else { MinVidIndex = 0; for (Index = 0; Index < (sizeof (VddNbVid) / sizeof (VddNbVid[0])); Index++) { IDS_HDT_CONSOLE (PCIE_MISC, " VddNbVid[%d] %x\n", Index, VddNbVid[Index]); if (VddNbVid[Index] > VddNbVid[MinVidIndex]) { MinVidIndex = (UINT8) Index; } } //ASSERT (VddNbVid[MinVidIndex] != 0); TargetVid = VddNbVid[MinVidIndex]; } Millivolt[0] = GnbTranslateVidCodeToMillivoltV5 (TargetVid, GnbLibGetHeader (Pcie)) * 4 / 100; IDS_HDT_CONSOLE (PCIE_MISC, " Set Voltage for Gen %d, Vid code %d, Millivolt with 2 fraction = %d\n", LinkCap, TargetVid, Millivolt[0]); Millivolt[1] = 0; Millivolt[2] = 0; Millivolt[3] = 0; Millivolt[4] = 0; Millivolt[5] = 0; if (TargetVid != 0) { GnbRegisterWriteCZ (GnbGetHandle (GnbLibGetHeader (Pcie)), TYPE_SMU_MSG, SMC_MSG_VddNbRequest, Millivolt, 0, GnbLibGetHeader (Pcie)); } IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetVoltageCZ Exit\n"); }
/** * Build integrated info table * * * * @param[in] Gfx Gfx configuration info * @retval AGESA_STATUS */ AGESA_STATUS GfxIntegratedInfoTableInit ( IN GFX_PLATFORM_CONFIG *Gfx ) { AGESA_STATUS Status; AGESA_STATUS AgesaStatus; ATOM_FUSION_SYSTEM_INFO_V1 SystemInfoV1Table; PP_FUSE_ARRAY *PpFuseArray; PCIe_PLATFORM_CONFIG *Pcie; UINT32 IntegratedInfoAddress; ATOM_PPLIB_POWERPLAYTABLE3 *PpTable; UINT8 Channel; AgesaStatus = AGESA_SUCCESS; IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInit Enter\n"); LibAmdMemFill (&SystemInfoV1Table, 0x00, sizeof (ATOM_FUSION_SYSTEM_INFO_V1), GnbLibGetHeader (Gfx)); SystemInfoV1Table.sIntegratedSysInfo.sHeader.usStructureSize = sizeof (ATOM_INTEGRATED_SYSTEM_INFO_V6); ASSERT (SystemInfoV1Table.sIntegratedSysInfo.sHeader.usStructureSize == 512); SystemInfoV1Table.sIntegratedSysInfo.sHeader.ucTableFormatRevision = 1; SystemInfoV1Table.sIntegratedSysInfo.sHeader.ucTableContentRevision = 6; SystemInfoV1Table.sIntegratedSysInfo.ulDentistVCOFreq = GfxLibGetMainPllFreq (GnbLibGetHeader (Gfx)) * 100; SystemInfoV1Table.sIntegratedSysInfo.ulBootUpUMAClock = Gfx->UmaInfo.MemClock * 100; SystemInfoV1Table.sIntegratedSysInfo.usRequestedPWMFreqInHz = Gfx->LcdBackLightControl; SystemInfoV1Table.sIntegratedSysInfo.ucUMAChannelNumber = ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_INTERLEAVE) == 0) ? 1 : 2; SystemInfoV1Table.sIntegratedSysInfo.ucMemoryType = 3; //DDR3 SystemInfoV1Table.sIntegratedSysInfo.ulBootUpEngineClock = 200 * 100; //Set default engine clock to 200MhZ SystemInfoV1Table.sIntegratedSysInfo.usBootUpNBVoltage = GfxLibMaxVidIndex (GnbLibGetHeader (Gfx)); SystemInfoV1Table.sIntegratedSysInfo.ulMinEngineClock = GfxLibGetMinSclk (GnbLibGetHeader (Gfx)); SystemInfoV1Table.sIntegratedSysInfo.usPanelRefreshRateRange = Gfx->DynamicRefreshRate; SystemInfoV1Table.sIntegratedSysInfo.usLvdsSSPercentage = Gfx->LvdsSpreadSpectrum; SystemInfoV1Table.sIntegratedSysInfo.usLvdsSSpreadRateIn10Hz = Gfx->LvdsSpreadSpectrumRate; SystemInfoV1Table.sIntegratedSysInfo.usPCIEClkSSPercentage = Gfx->PcieRefClkSpreadSpectrum; // SystemInfoV1Table.sIntegratedSysInfo.ucLvdsMisc = Gfx->LvdsMiscControl.Value; //Locate PCIe configuration data to get definitions of display connectors SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.sHeader.usStructureSize = sizeof (ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO); SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableFormatRevision = 1; SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableContentRevision = 1; SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.uc3DStereoPinId = Gfx->Gnb3dStereoPinIndex; ASSERT ((Gfx->UmaInfo.UmaAttributes & (UMA_ATTRIBUTE_ON_DCT0 | UMA_ATTRIBUTE_ON_DCT1)) != 0); if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT0) != 0) { Channel = 0; } else { Channel = 1; } if (GfxLibGetCsrPhySrPllPdMode (Channel, GnbLibGetHeader (Gfx)) != 0) { SystemInfoV1Table.sIntegratedSysInfo.ulSystemConfig |= BIT2; } if (GfxLibGetDisDllShutdownSR (Channel, GnbLibGetHeader (Gfx)) == 0) { SystemInfoV1Table.sIntegratedSysInfo.ulSystemConfig |= BIT1; } Status = PcieLocateConfigurationData (GnbLibGetHeader (Gfx), &Pcie); ASSERT (Status == AGESA_SUCCESS); AGESA_STATUS_UPDATE (Status, AgesaStatus); if (Status == AGESA_SUCCESS) { Status = GfxIntegratedEnumerateAllConnectors ( &SystemInfoV1Table.sIntegratedSysInfo.sExtDispConnInfo.sPath[0], Pcie, Gfx ); AGESA_STATUS_UPDATE (Status, AgesaStatus); } SystemInfoV1Table.sIntegratedSysInfo.usExtDispConnInfoOffset = offsetof (ATOM_INTEGRATED_SYSTEM_INFO_V6, sExtDispConnInfo); // Build PP table PpTable = (ATOM_PPLIB_POWERPLAYTABLE3*) &SystemInfoV1Table.ulPowerplayTable; // Build PP table Status = GfxPowerPlayBuildTable (PpTable, Gfx); AGESA_STATUS_UPDATE (Status, AgesaStatus); // Build info from fuses PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx)); ASSERT (PpFuseArray != NULL); if (PpFuseArray != NULL) { // Build Display clock info GfxIntegratedInfoInitDispclkTable (PpFuseArray, &SystemInfoV1Table.sIntegratedSysInfo, Gfx); // Build Sclk info table GfxIntegratedInfoInitSclkTable (PpFuseArray, &SystemInfoV1Table.sIntegratedSysInfo, Gfx); } else { Status = AGESA_ERROR; AGESA_STATUS_UPDATE (Status, AgesaStatus); } // Fill in HTC Data GfxFillHtcData (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); // Fill in NB P states VID GfxFillNbPStateVid (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); // Fill in NCLK info GfxFillNclkInfo (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); // Fill in the M3 arbitration control tables GfxFillM3ArbritrationControl (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); // Fill South bridge MMIO Base address GfxFillSbMmioBaseAddress (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); // Family specific data update GfxFmIntegratedInfoTableInit (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG, &SystemInfoV1Table.sIntegratedSysInfo, GnbLibGetHeader (Gfx)); //Copy integrated info table to Frame Buffer. (Do not use LibAmdMemCopy, routine not guaranteed access to above 4G memory in 32 bit mode.) IntegratedInfoAddress = (UINT32) (Gfx->UmaInfo.UmaSize - sizeof (ATOM_FUSION_SYSTEM_INFO_V1)); GfxLibCopyMemToFb ((VOID *) (&SystemInfoV1Table), IntegratedInfoAddress, sizeof (ATOM_FUSION_SYSTEM_INFO_V1), Gfx); IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInit Exit [0x%x]\n", Status); return Status; }
STATIC AGESA_STATUS GnbLclkDpmInitTN ( IN AMD_CONFIG_PARAMS *StdHeader ) { AGESA_STATUS Status; PCIe_PLATFORM_CONFIG *Pcie; PP_FUSE_ARRAY *PpFuseArray; PCI_ADDR GnbPciAddress; UINT32 Index; UINT8 LclkDpmMode; D0F0xBC_x1F200_STRUCT D0F0xBC_x1F200[NUM_DPM_STATES]; D0F0xBC_x1F208_STRUCT D0F0xBC_x1F208[NUM_DPM_STATES]; D0F0xBC_x1F210_STRUCT D0F0xBC_x1F210[NUM_DPM_STATES]; D0F0xBC_x1F300_STRUCT D0F0xBC_x1F300; ex1003_STRUCT ex1003 [NUM_DPM_STATES]; DOUBLE PcieCacLut; ex1072_STRUCT ex1072 ; D0F0xBC_x1FE00_STRUCT D0F0xBC_x1FE00; D0F0xBC_x1F30C_STRUCT D0F0xBC_x1F30C; D18F3x64_STRUCT D18F3x64; IDS_HDT_CONSOLE (GNB_TRACE, "GnbLclkDpmInitTN Enter\n"); Status = AGESA_SUCCESS; LclkDpmMode = GnbBuildOptions.LclkDpmEn ? LclkDpmRcActivity : LclkDpmDisabled; IDS_OPTION_HOOK (IDS_GNB_LCLK_DPM_EN, &LclkDpmMode, StdHeader); if (LclkDpmMode == LclkDpmRcActivity) { PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); if (PpFuseArray != NULL) { Status = PcieLocateConfigurationData (StdHeader, &Pcie); if (Status == AGESA_SUCCESS) { GnbPciAddress.AddressValue = MAKE_SBDFO (0, 0, 0, 0, 0); //Clear DPM_EN bit in LCLK_DPM_CNTL register //Call BIOS service SMC_MSG_CONFIG_LCLK_DPM to disable LCLK DPM GnbRegisterReadTN (D0F0xBC_x1F300_TYPE, D0F0xBC_x1F300_ADDRESS, &D0F0xBC_x1F300.Value, 0, StdHeader); D0F0xBC_x1F300.Field.LclkDpmEn = 0x0; GnbRegisterWriteTN (D0F0xBC_x1F300_TYPE, D0F0xBC_x1F300_ADDRESS, &D0F0xBC_x1F300.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); GnbSmuServiceRequestV4 ( GnbPciAddress, SMC_MSG_CONFIG_LCLK_DPM, GNB_REG_ACC_FLAG_S3SAVE, StdHeader ); //Initialize LCLK states LibAmdMemFill (D0F0xBC_x1F200, 0x00, sizeof (D0F0xBC_x1F200), StdHeader); LibAmdMemFill (D0F0xBC_x1F208, 0x00, sizeof (D0F0xBC_x1F208), StdHeader); LibAmdMemFill (ex1003, 0x00, sizeof (D0F0xBC_x1F208), StdHeader); D0F0xBC_x1F200[0].Field.LclkDivider = PpFuseArray->LclkDpmDid[0]; D0F0xBC_x1F200[0].Field.VID = PpFuseArray->SclkVid[PpFuseArray->LclkDpmVid[0]]; D0F0xBC_x1F200[0].Field.LowVoltageReqThreshold = 0xa; D0F0xBC_x1F210[0].Field.ActivityThreshold = 0xf; D0F0xBC_x1F200[5].Field.LclkDivider = PpFuseArray->LclkDpmDid[1]; D0F0xBC_x1F200[5].Field.VID = PpFuseArray->SclkVid[PpFuseArray->LclkDpmVid[1]]; D0F0xBC_x1F200[5].Field.LowVoltageReqThreshold = 0xa; D0F0xBC_x1F210[5].Field.ActivityThreshold = 0x32; D0F0xBC_x1F200[5].Field.StateValid = 0x1; D0F0xBC_x1F200[6].Field.LclkDivider = PpFuseArray->LclkDpmDid[2]; D0F0xBC_x1F200[6].Field.VID = PpFuseArray->SclkVid[PpFuseArray->LclkDpmVid[2]]; D0F0xBC_x1F200[6].Field.LowVoltageReqThreshold = 0xa; D0F0xBC_x1F210[6].Field.ActivityThreshold = 0x32; D0F0xBC_x1F200[6].Field.StateValid = 0x1; GnbRegisterReadTN (TYPE_D0F0xBC , 0x1f920 , &ex1072.Value, 0, StdHeader); PcieCacLut = 0.0000057028 * (1 << ex1072.Field.ex1072_0 ); IDS_HDT_CONSOLE (GNB_TRACE, "LCLK DPM1 10khz %x (%d)\n", GfxFmCalculateClock (PpFuseArray->LclkDpmDid[1], StdHeader), GfxFmCalculateClock (PpFuseArray->LclkDpmDid[1], StdHeader)); D0F0xBC_x1FE00.Field.Data = (UINT32) GnbFpLibDoubleToInt32 (PcieCacLut * GfxFmCalculateClock (PpFuseArray->LclkDpmDid[1], StdHeader)); GnbRegisterWriteTN (D0F0xBC_x1FE00_TYPE, D0F0xBC_x1FE00_ADDRESS, &D0F0xBC_x1FE00.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); PcieCacLut = 0.00000540239329 * (1 << ex1072.Field.ex1072_0 ); ex1003[6].Field.ex1003_0 = (UINT32) GnbFpLibDoubleToInt32 (PcieCacLut * GfxFmCalculateClock (PpFuseArray->LclkDpmDid[2], StdHeader)); IDS_HDT_CONSOLE (GNB_TRACE, "LCLK DPM2 10khz %x (%d)\n", GfxFmCalculateClock (PpFuseArray->LclkDpmDid[2], StdHeader), GfxFmCalculateClock (PpFuseArray->LclkDpmDid[2], StdHeader)); for (Index = 0; Index < NUM_DPM_STATES; ++Index) { GnbRegisterWriteTN ( D0F0xBC_x1F200_TYPE, D0F0xBC_x1F200_ADDRESS + Index * 0x20, &D0F0xBC_x1F200[Index].Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader ); GnbRegisterWriteTN ( D0F0xBC_x1F208_TYPE, D0F0xBC_x1F208_ADDRESS + Index * 0x20, &D0F0xBC_x1F208[Index].Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader ); GnbRegisterWriteTN ( D0F0xBC_x1F210_TYPE, D0F0xBC_x1F210_ADDRESS + Index * 0x20, &D0F0xBC_x1F210[Index].Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader ); GnbRegisterWriteTN ( TYPE_D0F0xBC , 0x1f940 + Index * 4, &ex1003[Index].Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader ); } //Enable LCLK DPM Voltage Scaling GnbRegisterReadTN (D0F0xBC_x1F300_TYPE, D0F0xBC_x1F300_ADDRESS, &D0F0xBC_x1F300.Value, 0, StdHeader); D0F0xBC_x1F300.Field.VoltageChgEn = 0x1; D0F0xBC_x1F300.Field.LclkDpmEn = 0x1; D0F0xBC_x1F300.Field.LclkDpmBootState = 0x5; GnbRegisterWriteTN (D0F0xBC_x1F300_TYPE, D0F0xBC_x1F300_ADDRESS, &D0F0xBC_x1F300.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); //Programming Lclk Thermal Throttling Threshold GnbRegisterReadTN (D18F3x64_TYPE, D18F3x64_ADDRESS, &D18F3x64.Value, 0, StdHeader); GnbRegisterReadTN (D0F0xBC_x1F30C_TYPE, D0F0xBC_x1F30C_ADDRESS, &D0F0xBC_x1F30C.Value, 0, StdHeader); D0F0xBC_x1F30C.Field.LowThreshold = (UINT16) (((D18F3x64.Field.HtcTmpLmt / 2 + 52) - 1 + 49) * 8); D0F0xBC_x1F30C.Field.HighThreshold = (UINT16) (((D18F3x64.Field.HtcTmpLmt / 2 + 52) + 49) * 8); GnbRegisterWriteTN (D0F0xBC_x1F30C_TYPE, D0F0xBC_x1F30C_ADDRESS, &D0F0xBC_x1F30C.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); GnbSmuServiceRequestV4 ( GnbPciAddress, SMC_MSG_CONFIG_LCLK_DPM, GNB_REG_ACC_FLAG_S3SAVE, StdHeader ); } } else { Status = AGESA_ERROR; } } IDS_HDT_CONSOLE (GNB_TRACE, "GnbLclkDpmInitTN Exit [0x%x]\n", Status); return Status; }
VOID STATIC PcieHwInitPowerGatingCZ ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT8 Pif; UINT32 Value; D0F0xE4_PIF_0004_STRUCT D0F0xE4_PIF_0004; D0F0xE4_PIF_0008_STRUCT D0F0xE4_PIF_0008; D0F0xE4_PIF_000A_STRUCT D0F0xE4_PIF_000A; D0F0xE4_CORE_012A_STRUCT D0F0xE4_CORE_012A; D0F0xE4_CORE_012C_STRUCT D0F0xE4_CORE_012C; D0F0xE4_CORE_012D_STRUCT D0F0xE4_CORE_012D; GNB_BUILD_OPTIONS_CZ *GnbBuildOptionData; IDS_HDT_CONSOLE (GNB_TRACE, "PcieHwInitPowerGatingCZ Enter\n"); GnbBuildOptionData = GnbLocateHeapBuffer (AMD_GNB_BUILD_OPTIONS_HANDLE, GnbLibGetHeader (Pcie)); ASSERT (GnbBuildOptionData != NULL); Value = 0x0; if ((GnbBuildOptionData->CfgPcieHwInitPwerGating & PcieHwInitPwrGatingL1Pg) == PcieHwInitPwrGatingL1Pg) { Value = 0x1; } PcieRegisterWriteField ( Wrapper, CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_003D_ADDRESS), D0F0xE4_CORE_003D_LC_L1_POWER_GATING_EN_OFFSET, D0F0xE4_CORE_003D_LC_L1_POWER_GATING_EN_WIDTH, Value, TRUE, Pcie ); for (Pif = 0; Pif < Wrapper->NumberOfPIFs; Pif++) { D0F0xE4_PIF_0008.Value = PcieRegisterRead ( Wrapper, PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0008_ADDRESS), Pcie ); D0F0xE4_PIF_000A.Value = PcieRegisterRead ( Wrapper, PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_000A_ADDRESS), Pcie ); D0F0xE4_PIF_0008.Field.TxpwrInOff = GnbBuildOptionData->CfgPcieTxpwrInOff; D0F0xE4_PIF_000A.Field.RxpwrInOff = GnbBuildOptionData->CfgPcieRxpwrInOff; D0F0xE4_PIF_000A.Field.RxEiDetInPs2Degrade = 0x0; D0F0xE4_PIF_0008.Field.TxpwrGatingInL1 = 0x0; D0F0xE4_PIF_000A.Field.RxpwrGatingInL1 = 0x0; if ((GnbBuildOptionData->CfgPcieHwInitPwerGating & PcieHwInitPwrGatingL1Pg) == PcieHwInitPwrGatingL1Pg) { D0F0xE4_PIF_0008.Field.TxpwrGatingInL1 = 0x1; D0F0xE4_PIF_000A.Field.RxpwrGatingInL1 = 0x1; } D0F0xE4_PIF_0008.Field.TxpwrGatingInUnused = 0x0; D0F0xE4_PIF_000A.Field.RxpwrGatingInUnused = 0x0; if ((GnbBuildOptionData->CfgPcieHwInitPwerGating & PcieHwInitPwrGatingOffPg) == PcieHwInitPwrGatingOffPg) { D0F0xE4_PIF_0008.Field.TxpwrGatingInUnused = 0x1; D0F0xE4_PIF_000A.Field.RxpwrGatingInUnused = 0x1; } PcieRegisterWrite ( Wrapper, PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0008_ADDRESS), D0F0xE4_PIF_0008.Value, TRUE, Pcie ); PcieRegisterWrite ( Wrapper, PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_000A_ADDRESS), D0F0xE4_PIF_000A.Value, TRUE, Pcie ); D0F0xE4_PIF_0004.Value = PcieRegisterRead ( Wrapper, PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0004_ADDRESS), Pcie ); D0F0xE4_PIF_0004.Field.PifDegradePwrPllMode = 0x0; PcieRegisterWrite ( Wrapper, PIF_SPACE (Wrapper->WrapId, Pif, D0F0xE4_PIF_0004_ADDRESS), D0F0xE4_PIF_0004.Value, TRUE, Pcie ); } D0F0xE4_CORE_012A.Value = PcieRegisterRead ( Wrapper, CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_012A_ADDRESS), Pcie ); D0F0xE4_CORE_012C.Value = PcieRegisterRead ( Wrapper, CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_012C_ADDRESS), Pcie ); D0F0xE4_CORE_012D.Value = PcieRegisterRead ( Wrapper, CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_012D_ADDRESS), Pcie ); D0F0xE4_CORE_012A.Field.LMLaneDegrade0 = 1; D0F0xE4_CORE_012A.Field.LMLaneDegrade1 = 1; D0F0xE4_CORE_012A.Field.LMLaneDegrade2 = 1; D0F0xE4_CORE_012A.Field.LMLaneDegrade3 = 1; D0F0xE4_CORE_012C.Field.LMLaneUnused0 = 1; D0F0xE4_CORE_012C.Field.LMLaneUnused1 = 1; D0F0xE4_CORE_012C.Field.LMLaneUnused2 = 1; D0F0xE4_CORE_012D.Field.LMLaneUnused3 = 1; PcieRegisterWrite ( Wrapper, CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_012A_ADDRESS), D0F0xE4_CORE_012A.Value, TRUE, Pcie ); PcieRegisterWrite ( Wrapper, CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_012C_ADDRESS), D0F0xE4_CORE_012C.Value, TRUE, Pcie ); PcieRegisterWrite ( Wrapper, CORE_SPACE (Wrapper->StartPcieCoreId, D0F0xE4_CORE_012D_ADDRESS), D0F0xE4_CORE_012D.Value, TRUE, Pcie ); IDS_HDT_CONSOLE (GNB_TRACE, "PcieHwInitPowerGatingCZ Exit\n"); }
/** * Per wrapper Pcie Init prior training. * * * @param[in] Wrapper Pointer to wrapper configuration descriptor * @param[in] Buffer Pointer buffer * @param[in] Pcie Pointer to global PCIe configuration */ AGESA_STATUS STATIC PcieEarlyInitCallbackCZ ( IN PCIe_WRAPPER_CONFIG *Wrapper, IN OUT VOID *Buffer, IN PCIe_PLATFORM_CONFIG *Pcie ) { AGESA_STATUS Status; BOOLEAN CoreConfigChanged; BOOLEAN PllConfigChanged; BOOLEAN AriSupportEnable; GNB_BUILD_OPTIONS_CZ *GnbBuildOptionData; IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitCallbackCZ Enter\n"); CoreConfigChanged = FALSE; PllConfigChanged = FALSE; GnbBuildOptionData = GnbLocateHeapBuffer (AMD_GNB_BUILD_OPTIONS_HANDLE, GnbLibGetHeader (Pcie)); ASSERT (GnbBuildOptionData != NULL); AriSupportEnable = GnbBuildOptionData->CfgAriSupport; if (AriSupportEnable == TRUE) { // Enable Alternative Routing-ID Interpretation GnbLibPciIndirectRMW ( MAKE_SBDFO (0,0,0,0, D0F0x60_ADDRESS), D0F0x64_x46_ADDRESS, AccessWidth32, (UINT32)~D0F0x64_x46_IocAriSupported_MASK, (1 << D0F0x64_x46_IocAriSupported_OFFSET), GnbLibGetHeader (Pcie) ); PcieRegisterRMW ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_0000_ADDRESS), D0F0xE4_WRAP_0000_StrapBif2AriEn_MASK, (1 << D0F0xE4_WRAP_0000_StrapBif2AriEn_OFFSET), TRUE, Pcie ); } if (GnbBuildOptionData->CfgACSEnable == TRUE) { // Enable Access Control Services PcieRegisterRMW ( Wrapper, WRAP_SPACE (Wrapper->WrapId, D0F0xE4_WRAP_000A_ADDRESS), 0xFFFFFFF8, (BIT0 | BIT1 | BIT2), TRUE, Pcie ); } IDS_OPTION_HOOK (IDS_BEFORE_RECONFIGURATION, Pcie, (AMD_CONFIG_PARAMS *)Pcie->StdHeader); PcieTopologyPrepareForReconfigCZ (Wrapper, Pcie); //step 2 Status = PcieTopologySetCoreConfigCZ (Wrapper, &CoreConfigChanged, Pcie); //step 3 ASSERT (Status == AGESA_SUCCESS); PcieTopologyApplyLaneMuxCZ (Wrapper, Pcie); //step 4 // PciePifSetRxDetectPowerMode (Wrapper, Pcie); // PciePifSetLs2ExitTime (Wrapper, Pcie); // PciePifApplyGanging (Wrapper, Pcie); // PciePhyApplyGangingCZ (Wrapper, Pcie); PcieTopologySelectMasterPllCZ (Wrapper, &PllConfigChanged, Pcie); //step 5 if (CoreConfigChanged) { PcieTopologyExecuteReconfigCZ (Wrapper, Pcie); // step 6 } PcieEarlyWrapperTxPresetLoadingSequenceCZ (Wrapper, Pcie); PcieTopologyCleanUpReconfigCZ (Wrapper, Pcie); // step 7 PcieTopologySetLinkReversalV4 (Wrapper, Pcie); // step 8 // PciePifPllConfigureCZ (Wrapper, Pcie); PcieTopologyLaneControlCZ ( DisableLanes, PcieUtilGetWrapperLaneBitMap (LANE_TYPE_CORE_ALL, LANE_TYPE_PCIE_CORE_ALLOC, Wrapper), Wrapper, Pcie ); //step 9 // PciePollPifForCompeletion (Wrapper, Pcie); // PciePhyAvertClockPickersCZ (Wrapper, Pcie); PcieEarlyCoreInitCZ (Wrapper, Pcie); PcieSetSsidCZ (UserOptions.CfgGnbPcieSSID, Wrapper, Pcie); PcieHwInitPowerGatingCZ (Wrapper, Pcie); IDS_HDT_CONSOLE (GNB_TRACE, "PcieEarlyInitCallbackCZ Exit [%x]\n", Status); return Status; }
AGESA_STATUS PcieAlibBuildAcpiTable ( IN AMD_CONFIG_PARAMS *StdHeader, OUT VOID **AlibSsdtPtr ) { AGESA_STATUS Status; UINT32 AmlObjName; PCIe_PLATFORM_CONFIG *Pcie; PP_FUSE_ARRAY *PpFuseArray; VOID *AlibSsdtBuffer; VOID *AmlObjPtr; UINT8 SclkVidArray[4]; UINT8 BootUpVid; UINT8 BootUpVidIndex; UINT8 Gen1VidIndex; UINTN Index; UINTN AlibSsdtlength; Status = AGESA_SUCCESS; AlibSsdtlength = ((ACPI_TABLE_HEADER*) &AlibSsdt[0])->TableLength; if (*AlibSsdtPtr == NULL) { AlibSsdtBuffer = GnbAllocateHeapBuffer ( AMD_ACPI_ALIB_BUFFER_HANDLE, AlibSsdtlength, StdHeader ); ASSERT (AlibSsdtBuffer != NULL); if (AlibSsdtBuffer == NULL) { return AGESA_ERROR; } *AlibSsdtPtr = AlibSsdtBuffer; } else { AlibSsdtBuffer = *AlibSsdtPtr; } // Copy template to buffer LibAmdMemCopy (AlibSsdtBuffer, &AlibSsdt[0], AlibSsdtlength, StdHeader); // Set PCI MMIO configuration // AmlObjName = '10DA'; AmlObjName = Int32FromChar ('A', 'D', '0', '1'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); if (AmlObjPtr != NULL) { UINT64 MsrReg; LibAmdMsrRead (MSR_MMIO_Cfg_Base, &MsrReg, StdHeader); if ((MsrReg & BIT0) != 0 && (MsrReg & 0xFFFFFFFF00000000) == 0) { *(UINT32*)((UINT8*)AmlObjPtr + 5) = (UINT32)(MsrReg & 0xFFFFF00000); } else { Status = AGESA_ERROR; } } else { Status = AGESA_ERROR; } // Set voltage configuration PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); if (PpFuseArray != NULL) { // AmlObjName = '30DA'; AmlObjName = Int32FromChar ('A', 'D', '0', '3'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { *(UINT8*)((UINT8*)AmlObjPtr + 5) = PpFuseArray->PcieGen2Vid; } else { Status = AGESA_ERROR; } } else { Status = AGESA_ERROR; } GnbLibPciRead ( MAKE_SBDFO ( 0, 0, 0x18, 3, D18F3x15C_ADDRESS), AccessWidth32, &SclkVidArray[0], StdHeader ); Gen1VidIndex = 0; BootUpVidIndex = 0; BootUpVid = 0xff; for (Index = 0; Index < 4; Index++) { if (SclkVidArray[Index] > SclkVidArray[Gen1VidIndex]) { Gen1VidIndex = (UINT8) Index; } if (SclkVidArray[Index] != 0 && SclkVidArray[Index] < BootUpVid) { BootUpVid = SclkVidArray[Index]; BootUpVidIndex = (UINT8) Index; } } // AmlObjName = '40DA'; AmlObjName = Int32FromChar ('A', 'D', '0', '4'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { *(UINT8*)((UINT8*)AmlObjPtr + 5) = Gen1VidIndex; } else { Status = AGESA_ERROR; } // AmlObjName = '50DA'; AmlObjName = Int32FromChar ('A', 'D', '0', '5'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { *(UINT8*)((UINT8*)AmlObjPtr + 5) = BootUpVidIndex; } else { Status = AGESA_ERROR; } // Set PCIe configuration if (PcieLocateConfigurationData (StdHeader, &Pcie) == AGESA_SUCCESS) { // AmlObjName = '20DA'; AmlObjName = Int32FromChar ('A', 'D', '0', '2'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { *(UINT8*)((UINT8*)AmlObjPtr + 5) = Pcie->PsppPolicy; } else { Status = AGESA_ERROR; } // AmlObjName = '60DA'; AmlObjName = Int32FromChar ('A', 'D', '0', '6'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { PcieConfigRunProcForAllEngines ( DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, PcieAlibSetPortMaxSpeedCallback, (UINT8*)((UINT8*)AmlObjPtr + 7), Pcie ); } else { Status = AGESA_ERROR; } // AmlObjName = '80DA'; AmlObjName = Int32FromChar ('A', 'D', '0', '8'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { PcieConfigRunProcForAllEngines ( DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, PcieAlibSetPortOverrideSpeedCallback, (UINT8*)((UINT8*)AmlObjPtr + 7), Pcie ); } else { Status = AGESA_ERROR; } // AmlObjName = '70DA'; AmlObjName = Int32FromChar ('A', 'D', '0', '7'); AmlObjPtr = GnbLibFind (AlibSsdtBuffer, AlibSsdtlength, (UINT8*) &AmlObjName, sizeof (AmlObjName)); ASSERT (AmlObjPtr != NULL); if (AmlObjPtr != NULL) { PcieConfigRunProcForAllEngines ( DESCRIPTOR_ALLOCATED | DESCRIPTOR_PCIE_ENGINE, PcieAlibSetPortInfoCallback, (UINT8*)((UINT8*)AmlObjPtr + 4), Pcie ); } else { Status = AGESA_ERROR; } } else { ASSERT (FALSE); Status = AGESA_ERROR; } if (Status == AGESA_SUCCESS) { Status = PcieFmAlibBuildAcpiTable (AlibSsdtBuffer, StdHeader); } if (Status != AGESA_SUCCESS) { //Shrink table length to size of the header ((ACPI_TABLE_HEADER*) AlibSsdtBuffer)->TableLength = sizeof (ACPI_TABLE_HEADER); } ChecksumAcpiTable ((ACPI_TABLE_HEADER*) AlibSsdtBuffer, StdHeader); return Status; }
/** * Build integrated info table * * * * @param[in] Gfx Gfx configuration info * @retval AGESA_STATUS */ AGESA_STATUS STATIC GfxIntInfoTableInitTN ( IN GFX_PLATFORM_CONFIG *Gfx ) { AGESA_STATUS Status; AGESA_STATUS AgesaStatus; ATOM_FUSION_SYSTEM_INFO_V2 SystemInfoTableV2; PP_FUSE_ARRAY *PpFuseArray; PCIe_PLATFORM_CONFIG *Pcie; ATOM_PPLIB_POWERPLAYTABLE3 *PpTable; UINT8 Channel; AgesaStatus = AGESA_SUCCESS; IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInitTN Enter\n"); LibAmdMemFill (&SystemInfoTableV2, 0x00, sizeof (ATOM_FUSION_SYSTEM_INFO_V2), GnbLibGetHeader (Gfx)); SystemInfoTableV2.sIntegratedSysInfo.sHeader.usStructureSize = sizeof (ATOM_INTEGRATED_SYSTEM_INFO_V1_7); ASSERT (SystemInfoTableV2.sIntegratedSysInfo.sHeader.usStructureSize == 512); SystemInfoTableV2.sIntegratedSysInfo.sHeader.ucTableFormatRevision = 1; SystemInfoTableV2.sIntegratedSysInfo.sHeader.ucTableContentRevision = 7; SystemInfoTableV2.sIntegratedSysInfo.ulDentistVCOFreq = GfxLibGetSytemPllCofTN (GnbLibGetHeader (Gfx)) * 100; SystemInfoTableV2.sIntegratedSysInfo.ulBootUpUMAClock = Gfx->UmaInfo.MemClock * 100; SystemInfoTableV2.sIntegratedSysInfo.usRequestedPWMFreqInHz = Gfx->LcdBackLightControl; SystemInfoTableV2.sIntegratedSysInfo.ucUMAChannelNumber = ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_INTERLEAVE) == 0) ? 1 : 2; SystemInfoTableV2.sIntegratedSysInfo.ucMemoryType = 3; //DDR3 SystemInfoTableV2.sIntegratedSysInfo.ulBootUpEngineClock = 200 * 100; //Set default engine clock to 200MhZ SystemInfoTableV2.sIntegratedSysInfo.usBootUpNBVoltage = GnbLocateHighestVidIndex (GnbLibGetHeader (Gfx)); SystemInfoTableV2.sIntegratedSysInfo.ulMinEngineClock = 200 * 100; SystemInfoTableV2.sIntegratedSysInfo.usPanelRefreshRateRange = Gfx->DynamicRefreshRate; SystemInfoTableV2.sIntegratedSysInfo.usLvdsSSPercentage = Gfx->LvdsSpreadSpectrum; //Locate PCIe configuration data to get definitions of display connectors SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sHeader.usStructureSize = sizeof (ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO); SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableFormatRevision = 1; SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sHeader.ucTableContentRevision = 1; SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.uc3DStereoPinId = Gfx->Gnb3dStereoPinIndex; SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.ucRemoteDisplayConfig = Gfx->GnbRemoteDisplaySupport; SystemInfoTableV2.sIntegratedSysInfo.usExtDispConnInfoOffset = offsetof (ATOM_INTEGRATED_SYSTEM_INFO_V1_7, sExtDispConnInfo); SystemInfoTableV2.sIntegratedSysInfo.ulSB_MMIO_Base_Addr = SbGetSbMmioBaseAddress (GnbLibGetHeader (Gfx)); SystemInfoTableV2.sIntegratedSysInfo.usPCIEClkSSPercentage = Gfx->PcieRefClkSpreadSpectrum; SystemInfoTableV2.sIntegratedSysInfo.ucLvdsMisc = Gfx->LvdsMiscControl.Value; IDS_HDT_CONSOLE (GNB_TRACE, "Lvds Misc control : %x\n", Gfx->LvdsMiscControl.Value); if (Gfx->LvdsMiscControl.Field.TravisLvdsVoltOverwriteEn) { SystemInfoTableV2.sIntegratedSysInfo.gnbgfxline429 = Gfx->gfxplmcfg0 ; IDS_HDT_CONSOLE (GNB_TRACE, "TravisLVDSVoltAdjust : %x\n", Gfx->gfxplmcfg0 ); } SystemInfoTableV2.sIntegratedSysInfo.ulOtherDisplayMisc = Gfx->DisplayMiscControl.Value; IDS_HDT_CONSOLE (GNB_TRACE, "Display Misc control : %x\n", Gfx->DisplayMiscControl.Value); // LVDS SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOnSeqDIGONtoDE_in4Ms = Gfx->LvdsPowerOnSeqDigonToDe; SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms = Gfx->LvdsPowerOnSeqDeToVaryBl; SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms = Gfx->LvdsPowerOnSeqVaryBlToDe; SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOffSeqDEtoDIGON_in4Ms = Gfx->LvdsPowerOnSeqDeToDigon; SystemInfoTableV2.sIntegratedSysInfo.ucLVDSOffToOnDelay_in4Ms = Gfx->LvdsPowerOnSeqOnToOffDelay; SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms = Gfx->LvdsPowerOnSeqVaryBlToBlon; SystemInfoTableV2.sIntegratedSysInfo.ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms = Gfx->LvdsPowerOnSeqBlonToVaryBl; SystemInfoTableV2.sIntegratedSysInfo.ulLCDBitDepthControlVal = Gfx->LcdBitDepthControlValue; SystemInfoTableV2.sIntegratedSysInfo.usMaxLVDSPclkFreqInSingleLink = Gfx->LvdsMaxPixelClockFreq; Status = PcieLocateConfigurationData (GnbLibGetHeader (Gfx), &Pcie); ASSERT (Status == AGESA_SUCCESS); AGESA_STATUS_UPDATE (Status, AgesaStatus); if (Status == AGESA_SUCCESS) { Status = GfxIntegratedEnumerateAllConnectors ( &SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.sPath[0], Pcie, Gfx ); AGESA_STATUS_UPDATE (Status, AgesaStatus); } SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.uceDPToLVDSRxId = eDP_TO_LVDS_RX_DISABLE; PcieConfigRunProcForAllEngines ( DESCRIPTOR_ALLOCATED | DESCRIPTOR_VIRTUAL | DESCRIPTOR_DDI_ENGINE, GfxIntegrateducEDPToLVDSRxIdCallback, &SystemInfoTableV2.sIntegratedSysInfo.sExtDispConnInfo.uceDPToLVDSRxId, Pcie ); // Build PP table PpTable = (ATOM_PPLIB_POWERPLAYTABLE3*) &SystemInfoTableV2.ulPowerplayTable; // Build PP table Status = GfxPowerPlayBuildTable (PpTable, Gfx); AGESA_STATUS_UPDATE (Status, AgesaStatus); // Assign usFormatID to 0x000B to represent Trinity PpTable->usFormatID = 0xB; // Build info from fuses PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Gfx)); ASSERT (PpFuseArray != NULL); if (PpFuseArray != NULL) { // Build Display clock info GfxIntInfoTableInitDispclkTable (PpFuseArray, &SystemInfoTableV2.sIntegratedSysInfo, Gfx); // Build Sclk info table GfxIntInfoTableInitSclkTable (PpFuseArray, &SystemInfoTableV2.sIntegratedSysInfo, Gfx); } else { Status = AGESA_ERROR; AGESA_STATUS_UPDATE (Status, AgesaStatus); } //@todo review if thouse parameters needed // Fill in Nb P-state MemclkFreq Data GfxFillNbPstateMemclkFreqTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx); // Fill in HTC Data GfxFillHtcDataTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx); // Fill in NB P states VID GfxFillNbPStateVidTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx); // Fill in NCLK info //GfxFillNclkInfo (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); // Fill in the M3 arbitration control tables //GfxFillM3ArbritrationControl (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); // Family specific data update // Determine ulGMCRestoreResetTime Status = GfxCalculateRestoreResetTimeTN (&SystemInfoTableV2.sIntegratedSysInfo, Gfx, PpFuseArray); AGESA_STATUS_UPDATE (Status, AgesaStatus); //GfxFmIntegratedInfoTableInit (&SystemInfoV1Table.sIntegratedSysInfo, Gfx); SystemInfoTableV2.sIntegratedSysInfo.ulDDR_DLL_PowerUpTime = 4940; SystemInfoTableV2.sIntegratedSysInfo.ulDDR_PLL_PowerUpTime = 2000; if ((Gfx->UmaInfo.UmaAttributes & UMA_ATTRIBUTE_ON_DCT0) != 0) { Channel = 0; } else { Channel = 1; } if (GfxLibGetMemPhyPllPdModeTN (Channel, GnbLibGetHeader (Gfx)) != 0) { SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig |= BIT2; } if (GfxLibGetDisDllShutdownSRTN (Channel, GnbLibGetHeader (Gfx)) == 0) { SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig |= BIT1; } if (GnbBuildOptions.CfgPciePowerGatingFlags != (PCIE_POWERGATING_SKIP_CORE | PCIE_POWERGATING_SKIP_PHY)) { SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig |= BIT0; } SystemInfoTableV2.sIntegratedSysInfo.ulGPUCapInfo = GPUCAPINFO_TMDS_HDMI_USE_CASCADE_PLL_MODE | GPUCAPINFO_DP_USE_SINGLE_PLL_MODE; IDS_HDT_CONSOLE (GNB_TRACE, "ulSystemConfig : %x\n", SystemInfoTableV2.sIntegratedSysInfo.ulSystemConfig); IDS_OPTION_CALLOUT (IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG, &SystemInfoTableV2.sIntegratedSysInfo, GnbLibGetHeader (Gfx)); //Copy integrated info table to Frame Buffer. (Do not use LibAmdMemCopy, routine not guaranteed access to above 4G memory in 32 bit mode.) GfxIntInfoTabablePostToFb (&SystemInfoTableV2, Gfx); IDS_HDT_CONSOLE (GNB_TRACE, "GfxIntegratedInfoTableInit Exit [0x%x]\n", Status); return Status; }
/** * Request boot up voltage * * * * @param[in] LinkCap Global GEN capability * @param[in] Pcie Pointer to PCIe configuration data area */ VOID PcieSetVoltageML ( IN PCIE_LINK_SPEED_CAP LinkCap, IN PCIe_PLATFORM_CONFIG *Pcie ) { UINT8 TargetVid; UINT8 MinVidIndex; UINT8 VddNbVid[5]; UINT8 Index; PP_FUSE_ARRAY_V2 *PpFuseArray; UINT32 Millivolt; D0F0xBC_xC0104007_STRUCT D0F0xBC_xC0104007; D0F0xBC_xC0104008_STRUCT D0F0xBC_xC0104008; D0F0xBC_xC010407C_STRUCT D0F0xBC_xC010407C; D0F0xBC_xC0107064_STRUCT D0F0xBC_xC0107064; IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetVoltageML Enter\n"); PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, GnbLibGetHeader (Pcie)); if (PpFuseArray == NULL) { IDS_HDT_CONSOLE (GNB_TRACE, " PpFuseArray is NULL\n"); GnbRegisterReadML (GnbGetHandle (GnbLibGetHeader (Pcie)), D0F0xBC_xC0104007_TYPE, D0F0xBC_xC0104007_ADDRESS, &D0F0xBC_xC0104007, 0, GnbLibGetHeader (Pcie)); GnbRegisterReadML (GnbGetHandle (GnbLibGetHeader (Pcie)), D0F0xBC_xC0104008_TYPE, D0F0xBC_xC0104008_ADDRESS, &D0F0xBC_xC0104008, 0, GnbLibGetHeader (Pcie)); GnbRegisterReadML (GnbGetHandle (GnbLibGetHeader (Pcie)), D0F0xBC_xC010407C_TYPE, D0F0xBC_xC010407C_ADDRESS, &D0F0xBC_xC010407C, 0, GnbLibGetHeader (Pcie)); GnbRegisterReadML (GnbGetHandle (GnbLibGetHeader (Pcie)), D0F0xBC_xC0107064_TYPE, D0F0xBC_xC0107064_ADDRESS, &D0F0xBC_xC0107064, 0, GnbLibGetHeader (Pcie)); VddNbVid[0] = (UINT8) D0F0xBC_xC0104007.Field.VddNbVid0; VddNbVid[1] = (UINT8) D0F0xBC_xC0104008.Field.VddNbVid1; VddNbVid[2] = (UINT8) D0F0xBC_xC0104008.Field.VddNbVid2; VddNbVid[3] = (UINT8) D0F0xBC_xC0104008.Field.VddNbVid3; VddNbVid[4] = (UINT8) D0F0xBC_xC010407C.Field.VddNbVid4; Index = (UINT8) D0F0xBC_xC0107064.Field.PcieGen2Vid; } else { IDS_HDT_CONSOLE (GNB_TRACE, " PpFuseArray is Active\n"); VddNbVid[0] = PpFuseArray->VddNbVid[0]; VddNbVid[1] = PpFuseArray->VddNbVid[1]; VddNbVid[2] = PpFuseArray->VddNbVid[2]; VddNbVid[3] = PpFuseArray->VddNbVid[3]; VddNbVid[4] = PpFuseArray->VddNbVid[4]; Index = PpFuseArray->PcieGen2Vid; } IDS_HDT_CONSOLE (GNB_TRACE, " VddNbVid 0 - %x\n", VddNbVid[0]); IDS_HDT_CONSOLE (GNB_TRACE, " VddNbVid 1 - %x\n", VddNbVid[1]); IDS_HDT_CONSOLE (GNB_TRACE, " VddNbVid 2 - %x\n", VddNbVid[2]); IDS_HDT_CONSOLE (GNB_TRACE, " VddNbVid 3 - %x\n", VddNbVid[3]); IDS_HDT_CONSOLE (GNB_TRACE, " VddNbVid 4 - %x\n", VddNbVid[4]); IDS_HDT_CONSOLE (GNB_TRACE, " PcieGen2Vid Index - %x\n", Index); if (LinkCap > PcieGen1) { ASSERT (VddNbVid[Index] != 0); TargetVid = VddNbVid[Index]; IDS_HDT_CONSOLE (GNB_TRACE, " Gen2 TargetVid - %x\n", TargetVid); } else { MinVidIndex = 0; for (Index = 0; Index < 5; Index++) { if (VddNbVid[Index] > VddNbVid[MinVidIndex]) { MinVidIndex = (UINT8) Index; } } IDS_HDT_CONSOLE (GNB_TRACE, " MinVidIndex - %x\n", MinVidIndex); ASSERT (VddNbVid[MinVidIndex] != 0); TargetVid = VddNbVid[MinVidIndex]; IDS_HDT_CONSOLE (GNB_TRACE, " Gen1 TargetVid - %x\n", TargetVid); } IDS_HDT_CONSOLE (PCIE_MISC, " Set Voltage for Gen %d, Vid code %d\n", LinkCap, TargetVid); Millivolt = GnbTranslateVidCodeToMillivoltV5 (TargetVid, GnbLibGetHeader (Pcie)) * 4 / 100; GnbRegisterWriteML (GnbGetHandle (GnbLibGetHeader (Pcie)), TYPE_SMU_MSG, SMC_MSG_VDDNB_REQUEST, &Millivolt, 0, GnbLibGetHeader (Pcie)); IDS_HDT_CONSOLE (GNB_TRACE, "PcieSetVoltageML Exit\n"); }
AGESA_STATUS GnbEnvInterfaceTN ( IN AMD_CONFIG_PARAMS *StdHeader ) { AGESA_STATUS Status; AMD_ENV_PARAMS *EnvParamsPtr; UINT32 Property; GNB_HANDLE *GnbHandle; D18F5x170_STRUCT D18F5x170; D0F0xBC_x1F8DC_STRUCT D0F0xBC_x1F8DC; PP_FUSE_ARRAY *PpFuseArray; IDS_HDT_CONSOLE (GNB_TRACE, "GnbEnvInterfaceTN Enter\n"); Property = TABLE_PROPERTY_DEFAULT; EnvParamsPtr = (AMD_ENV_PARAMS *) StdHeader; GnbHandle = GnbGetHandle (StdHeader); ASSERT (GnbHandle != NULL); GnbLoadFuseTableTN (StdHeader); Status = GnbSetTom (GnbGetHostPciAddress (GnbHandle), StdHeader); GnbOrbDynamicWake (GnbGetHostPciAddress (GnbHandle), StdHeader); GnbClumpUnitIdV4 (GnbHandle, StdHeader); GnbLpcDmaDeadlockPreventionV4 (GnbHandle, StdHeader); Property |= GnbBuildOptionsTN.CfgLoadlineEnable ? TABLE_PROPERTY_LOADLINE_ENABLE : 0; if (!EnvParamsPtr->GnbEnvConfiguration.IommuSupport) { Property |= TABLE_PROPERTY_IOMMU_DISABLED; } else { // Force disable iommu if non-FM2 // PACKAGE_TYPE_FP2 1 // PACKAGE_TYPE_FS1r2 2 // PACKAGE_TYPE_FM2 4 if (LibAmdGetPackageType (StdHeader) != PACKAGE_TYPE_FM2) { EnvParamsPtr->GnbEnvConfiguration.IommuSupport = FALSE; Property |= TABLE_PROPERTY_IOMMU_DISABLED; } else { Property |= GnbBuildOptionsTN.GnbCommonOptions.CfgIommuL1ClockGatingEnable ? TABLE_PROPERTY_IOMMU_L1_CLOCK_GATING : 0; Property |= GnbBuildOptionsTN.GnbCommonOptions.CfgIommuL2ClockGatingEnable ? TABLE_PROPERTY_IOMMU_L2_CLOCK_GATING : 0; } } if (GnbBuildOptionsTN.CfgNbdpmEnable) { GnbRegisterReadTN ( TYPE_D18F5, D18F5x170_ADDRESS, &D18F5x170.Value, 0, StdHeader ); // Check if NbPstate enable if ((D18F5x170.Field.SwNbPstateLoDis != 1) && (D18F5x170.Field.NbPstateMaxVal != 0)) { Property |= TABLE_PROPERTY_NBDPM; PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); if (PpFuseArray != NULL) { // NBDPM is requesting SclkVid0 from the register. // Write them back if SclkVid has been changed in PpFuseArray. GnbRegisterReadTN (D0F0xBC_x1F8DC_TYPE, D0F0xBC_x1F8DC_ADDRESS, &D0F0xBC_x1F8DC.Value, 0, StdHeader); if ((D0F0xBC_x1F8DC.Field.SClkVid0 != PpFuseArray->SclkVid[0]) || (D0F0xBC_x1F8DC.Field.SClkVid1 != PpFuseArray->SclkVid[1]) || (D0F0xBC_x1F8DC.Field.SClkVid2 != PpFuseArray->SclkVid[2]) || (D0F0xBC_x1F8DC.Field.SClkVid3 != PpFuseArray->SclkVid[3])) { D0F0xBC_x1F8DC.Field.SClkVid0 = PpFuseArray->SclkVid[0]; D0F0xBC_x1F8DC.Field.SClkVid1 = PpFuseArray->SclkVid[1]; D0F0xBC_x1F8DC.Field.SClkVid2 = PpFuseArray->SclkVid[2]; D0F0xBC_x1F8DC.Field.SClkVid3 = PpFuseArray->SclkVid[3]; GnbRegisterWriteTN (D0F0xBC_x1F8DC_TYPE, D0F0xBC_x1F8DC_ADDRESS, &D0F0xBC_x1F8DC.Value, GNB_REG_ACC_FLAG_S3SAVE, StdHeader); } } } } IDS_OPTION_HOOK (IDS_GNB_PROPERTY, &Property, StdHeader); Status = GnbProcessTable ( GnbHandle, GnbEnvInitTableTN, Property, GNB_TABLE_FLAGS_FORCE_S3_SAVE, StdHeader ); IDS_HDT_CONSOLE (GNB_TRACE, "GnbEnvInterfaceTN Exit [0x%x]\n", Status); return Status; }
AGESA_STATUS NbFmInitLclkDpmRcActivity ( IN AMD_CONFIG_PARAMS *StdHeader ) { AGESA_STATUS Status; PP_FUSE_ARRAY *PpFuseArray; INT8 Index; UINTN LclkState; Status = AGESA_SUCCESS; IDS_HDT_CONSOLE (GNB_TRACE, "NbFmInitLclkDpmRcActivity F14 Enter\n"); PpFuseArray = GnbLocateHeapBuffer (AMD_PP_FUSE_TABLE_HANDLE, StdHeader); if (PpFuseArray != NULL) { UINT32 ActivityThreshold [8]; UINT16 SamplingPeriod [10]; UINT8 LclkScalingDid [4]; UINT8 LclkScalingVid [4]; UINT32 LclkDpmValid; UINT32 MainPllVcoKHz; LibAmdMemFill (&ActivityThreshold[0], 0, sizeof (ActivityThreshold), StdHeader); LibAmdMemFill (&SamplingPeriod[0], 0, sizeof (SamplingPeriod), StdHeader); MainPllVcoKHz = GfxLibGetMainPllFreq (StdHeader) * 100; LclkDpmValid = 0; LclkState = 7; for (Index = 3; Index >= 0; Index--) { if (PpFuseArray->LclkDpmValid [Index] != 0) { // Set valid DPM state LclkDpmValid |= (1 << (LclkState)); // Set LCLK scaling DID LclkScalingDid [7 - LclkState] = PpFuseArray->LclkDpmDid [Index]; // Set LCLK scaling VID LclkScalingVid [7 - LclkState] = PpFuseArray->LclkDpmVid [Index]; // Set sampling period SamplingPeriod [LclkState] = 0xC350; // Changed from 0xC350 to 0x1388 for DPM 0 if (Index == 0) { SamplingPeriod [LclkState] = 0x1388; } // Set activity threshold from BKDG: // Raising -- ActivityThreshold [LclkState] = ((102 * (GfxLibCalculateClk (LclkScalingDid [7 - LclkState], MainPllVcoKHz) / 100)) - 10) / 10; // Lowering -- ActivityThreshold [LclkState] |= (((407 * (GfxLibCalculateClk (LclkScalingDid [7 - LclkState], MainPllVcoKHz) / 100)) + 99) / 10) << 16; // For ON specific enable LCLK DPM : ActivityThreshold [LclkState] = LclkDpmActivityThresholdTable [Index]; IDS_HDT_CONSOLE (GNB_TRACE, "Fused State Index:%d LCLK DPM State [%d]: LclkScalingDid - 0x%x, ActivityThreshold - 0x%x, SamplingPeriod - 0x%x\n", Index, LclkState, LclkScalingDid [7 - LclkState], ActivityThreshold [LclkState], SamplingPeriod [LclkState] ); LclkState--; } } if (LclkState != 7) { SMUx33_STRUCT SMUx33; SMUx0B_x8434_STRUCT SMUx0B_x8434; FCRxFF30_01E4_STRUCT FCRxFF30_01E4; UINT8 CurrentUnit; UINT16 FinalUnit; UINT16 FinalPeriod; UINT32 Freq; UINT32 FreqDelta; UINT32 Value; ASSERT (LclkScalingDid [0] != 0); FreqDelta = 0xffffffff; FinalPeriod = 0; FinalUnit = 0; Freq = (65535 * 100 * 100) / GfxLibCalculateClk (LclkScalingDid [0], MainPllVcoKHz); for (CurrentUnit = 0; CurrentUnit < 16; CurrentUnit++) { UINT32 CurrentFreqDelta; UINT32 CurrentPeriod; UINT32 Temp; Temp = GnbLibPowerOf (4, CurrentUnit); CurrentPeriod = Freq / Temp; if (CurrentPeriod <= 0xFFFF) { CurrentFreqDelta = Freq - Temp * CurrentPeriod; if (FreqDelta > CurrentFreqDelta) { FinalUnit = CurrentUnit; FinalPeriod = (UINT16) CurrentPeriod; FreqDelta = CurrentFreqDelta; } } } //Process to enablement LCLK DPM States NbSmuIndirectRead (SMUx33_ADDRESS, AccessWidth32, &SMUx33.Value, StdHeader); SMUx33.Field.BusyCntSel = 0x3; SMUx33.Field.LclkActMonUnt = FinalUnit; SMUx33.Field.LclkActMonPrd = FinalPeriod; NbSmuIndirectWrite (SMUx33_ADDRESS, AccessS3SaveWidth32, &SMUx33.Value, StdHeader); SMUx0B_x8434.Value = 0; SMUx0B_x8434.Field.LclkDpmType = 0x1; SMUx0B_x8434.Field.LclkDpmEn = 0x1; SMUx0B_x8434.Field.LclkTimerPeriod = 0x0C350; SMUx0B_x8434.Field.LclkTimerPrescalar = 0x1; NbSmuRcuRegisterWrite ( SMUx0B_x8434_ADDRESS, &SMUx0B_x8434.Value, 1, TRUE, StdHeader ); NbSmuRcuRegisterWrite ( 0x84AC, &LclkDpmCacTable[0], sizeof (LclkDpmCacTable) / sizeof (UINT32), TRUE, StdHeader ); // Program activity threshold IDS_HDT_CONSOLE (GNB_TRACE, "ActivityThreshold[4] - 0x%x ActivityThreshold[5] - 0x%x ActivityThreshold[6] - 0x%x ActivityThreshold[7] - 0x%x\n", ActivityThreshold[4], ActivityThreshold[5], ActivityThreshold[6], ActivityThreshold [7] ); NbSmuRcuRegisterWrite ( SMUx0B_x8470_ADDRESS, &ActivityThreshold[4], 4, TRUE, StdHeader ); // Program sampling period for (Index = 0; Index < (sizeof (SamplingPeriod) / sizeof (SamplingPeriod[0])); Index = Index + 2) { UINT16 Temp; Temp = SamplingPeriod[Index]; SamplingPeriod[Index] = SamplingPeriod[Index + 1]; SamplingPeriod[Index + 1] = Temp; } IDS_HDT_CONSOLE (GNB_TRACE, "SamplingPeriod[4] - 0x%x SamplingPeriod[5] - 0x%x SamplingPeriod[6] - 0x%x SamplingPeriod[7] - 0x%x \n", SamplingPeriod[4], SamplingPeriod[5], SamplingPeriod[6], SamplingPeriod[7] ); NbSmuRcuRegisterWrite ( SMUx0B_x8440_ADDRESS, (UINT32*) &SamplingPeriod[4], 2, TRUE, StdHeader ); // Program LCK scaling DID NbSmuRcuRegisterWrite ( SMUx0B_x848C_ADDRESS, (UINT32*) &LclkScalingDid[0], 1, TRUE, StdHeader ); // Program LCK scaling VID NbSmuRcuRegisterWrite ( SMUx0B_x8498_ADDRESS, (UINT32*) &LclkScalingVid[0], 1, TRUE, StdHeader ); // Program valid LCLK DPM states LclkDpmValid = NbFmDpmStateBootupInit (LclkDpmValid, StdHeader); NbSmuRcuRegisterWrite ( SMUx0B_x8490_ADDRESS, &LclkDpmValid, 1, TRUE, StdHeader ); //Setup Activity Monitor Coefficients Value = (0x24 << SMUx35_DownTrendCoef_OFFSET) | (0x24 << SMUx35_UpTrendCoef_OFFSET); NbSmuIndirectWrite (SMUx35_ADDRESS, AccessS3SaveWidth32, &Value, StdHeader); Value = (0x22 << SMUx35_DownTrendCoef_OFFSET) | (0x22 << SMUx35_UpTrendCoef_OFFSET); for (Index = SMUx37_ADDRESS; Index <= SMUx51_ADDRESS; Index = Index + 2) { NbSmuIndirectWrite (Index, AccessS3SaveWidth32, &Value, StdHeader); } // Enable LCLK DPM as voltage client NbSmuSrbmRegisterRead (FCRxFF30_01E4_ADDRESS, &FCRxFF30_01E4.Value, StdHeader); FCRxFF30_01E4.Field.VoltageChangeEn = 0x1; NbSmuSrbmRegisterWrite (FCRxFF30_01E4_ADDRESS, &FCRxFF30_01E4.Value, TRUE, StdHeader); // Start LCLK service NbSmuServiceRequest (0x8, TRUE, StdHeader); } } else { IDS_HDT_CONSOLE (GNB_TRACE, " ERROR! Cannot locate fuse table\n"); Status = AGESA_ERROR; } IDS_HDT_CONSOLE (GNB_TRACE, "NbFmInitLclkDpmRcActivity F14 Exit [0x%x]\n", Status); return Status; }