//------------------------------------------------------------------------------ // // Function: OALTimerUpdate // // This function is called to change length of actual system timer period. // If end of actual period is closer than margin period isn't changed (so // original period elapse). Function returns time which already expires // in new period length units. If end of new period is closer to actual time // than margin period end is shifted by margin (but next period should fix // this shift - this is reason why OALTimerRecharge doesn't read back // compare register and it uses saved value instead). // UINT32 OALTimerUpdate(UINT32 period, UINT32 margin) { #if (BSP_TYPE == BSP_SMDK2443) UINT32 tcon, ret; ret = OALTimerCountsSinceSysTick(); OUTREG32(&g_pPWMRegs->TCNTB4, period); tcon = INREG32(&g_pPWMRegs->TCON) & ~(0x0F << 20); OUTREG32(&g_pPWMRegs->TCON, tcon | (0x2 << 20) ); OUTREG32(&g_pPWMRegs->TCON, tcon | (0x5 << 20) ); return (ret); #elif (BSP_TYPE == BSP_SMDK2450) #if 0 // Fixed Tick do not Update TImer UINT32 tcon, ret; ret = OALTimerCountsSinceSysTick(); OUTREG32(&g_pPWMRegs->TCNTB4, period); tcon = INREG32(&g_pPWMRegs->TCON) & ~(0x0F << 20); OUTREG32(&g_pPWMRegs->TCON, tcon | (0x2 << 20) ); OUTREG32(&g_pPWMRegs->TCON, tcon | (0x5 << 20) ); return (ret); #else return 0; #endif #endif }
//------------------------------------------------------------------------------ void PrcmVoltSetInitVddLevel( VoltageProcessor_e vp, UINT initVolt ) { UINT val; switch (vp) { case kVoltageProcessor1: val = INREG32(&g_pPrcmPrm->pOMAP_GLOBAL_PRM->PRM_VP1_CONFIG); val &= ~SMPS_INITVOLTAGE_MASK; val |= ((initVolt << SMPS_INITVOLTAGE_SHIFT) & SMPS_INITVOLTAGE_MASK); OUTREG32(&g_pPrcmPrm->pOMAP_GLOBAL_PRM->PRM_VP1_CONFIG, val); break; case kVoltageProcessor2: val = INREG32(&g_pPrcmPrm->pOMAP_GLOBAL_PRM->PRM_VP2_CONFIG); val &= ~SMPS_INITVOLTAGE_MASK; val |= ((initVolt << SMPS_INITVOLTAGE_SHIFT) & SMPS_INITVOLTAGE_MASK); OUTREG32(&g_pPrcmPrm->pOMAP_GLOBAL_PRM->PRM_VP2_CONFIG, val); break; } }
//------------------------------------------------------------------------------ // // Function: Omap37xx_dpll4_init // // Helper function to initialize OMAP 37xx/36xx DPLL4 . // void Omap37xx_dpll4_init(void) { OMAP_PRCM_EMU_CM_REGS* pPrcmEmuCM = OALPAtoUA(OMAP_PRCM_EMU_CM_REGS_PA); OMAP_PRCM_CAM_CM_REGS* pPrcmCamCM = OALPAtoUA(OMAP_PRCM_CAM_CM_REGS_PA); OMAP_PRCM_CLOCK_CONTROL_CM_REGS* pPrcmClkCM = OALPAtoUA(OMAP_PRCM_CLOCK_CONTROL_CM_REGS_PA); //OMAP_PRCM_SGX_CM_REGS* pPrcmSgxCM = OALPAtoUA(OMAP_PRCM_SGX_CM_REGS_PA); unsigned int val; // configure timings for all related peripherals OUTREG32(&pPrcmEmuCM->CM_CLKSEL1_EMU, BSP_CM_CLKSEL1_EMU); OUTREG32(&pPrcmCamCM->CM_CLKSEL_CAM, BSP_CM_CLKSEL_CAM); OUTREG32(&pPrcmClkCM->CM_CLKSEL3_PLL, BSP_CM_CLKSEL3_PLL); //OUTREG32(&pPrcmSgxCM->CM_CLKSEL_SGX, BSP_CM_CLKSEL_SGX); /* Omap37xx using low jitter DPLL, the output freq is one half of OMAP 35xx DPLL4 */ val = INREG32(&pPrcmClkCM->CM_CLKSEL2_PLL) & 0xfff00000; val |= (BSP_PERIPH_DPLL_MULT_37xx | BSP_PERIPH_DPLL_DIV); OUTREG32(&pPrcmClkCM->CM_CLKSEL2_PLL, val); // lock dpll with correct frequency selection val = BSP_CM_CLKEN_PLL & (~(7 << 4)); OUTREG32(&pPrcmClkCM->CM_CLKEN_PLL, val); while ((INREG32(&pPrcmClkCM->CM_IDLEST_CKGEN) & DPLL_STATUS_MASK) != DPLL_STATUS_LOCKED); }
//----------------------------------------------------------------------------- BOOL PrcmVoltIdleCheck( VoltageProcessor_e vp ) { UINT vpStatus; BOOL rc = FALSE; switch (vp) { case kVoltageProcessor1: vpStatus = INREG32(&g_pPrcmPrm->pOMAP_GLOBAL_PRM->PRM_VP1_STATUS); break; case kVoltageProcessor2: vpStatus = INREG32(&g_pPrcmPrm->pOMAP_GLOBAL_PRM->PRM_VP2_STATUS); break; default: goto cleanUp; } if (vpStatus & SMPS_VPINIDLE) { rc = TRUE; } cleanUp: return rc; }
////////// // Function Name : OTGDevice_DeInit // Function Desctiption : This function de-initializes OTG PHY and LINK. // Input : NONE // Output : NONE // Version : void OTGDevice_DeInit() { DWORD epNum; // Clear USB Interrupt enable registers OUTREG32(GINTMSK, 0); // Disable all RX, TX EPs if (INREG32(DIEPCTL0) & DEPCTL_EPENA) OUTREG32(DIEPCTL0, DEPCTL_EPDIS); if (INREG32(DOEPCTL0) & DEPCTL_EPENA) OUTREG32(DOEPCTL0, DEPCTL_EPDIS); for (epNum = 1; epNum < MAX_ENDPTS; epNum++) { if (INREG32(DIEPCTL[epNum]) & DEPCTL_EPENA) OUTREG32(DIEPCTL[epNum], DEPCTL_EPDIS); if (INREG32(DOEPCTL[epNum]) & DEPCTL_EPENA) OUTREG32(DOEPCTL[epNum], DEPCTL_EPDIS); } SETREG32(PCGCCTL, (1<<0)); //stop pclk }
// Called from OEMPowerOff - no system calls, critical sections, OALMSG, etc., are allowed //------------------------------------------------------------------------------ // WARNING: This function is called from OEMPowerOff - no system calls, critical // sections, OALMSG, etc., may be used by this function or any function that it calls. //------------------------------------------------------------------------------ void OALWatchdogEnable(BOOL bEnable) { if (g_WatchdogDevice != OMAP_DEVICE_NONE) { if (bEnable == TRUE) { // Enable clock EnableDeviceClocks(g_WatchdogDevice, TRUE); // Refresh the watchdog timer while( INREG32(&g_pWatchogTimerRegs->WWPS) ); OUTREG32(&g_pWatchogTimerRegs->WTGR, INREG32(&g_pWatchogTimerRegs->WTGR) + 1); // Start Watchdog OUTREG32(&g_pWatchogTimerRegs->WSPR, WDOG_ENABLE_SEQ1); while( INREG32(&g_pWatchogTimerRegs->WWPS) ); OUTREG32(&g_pWatchogTimerRegs->WSPR, WDOG_ENABLE_SEQ2); } else { // Ensure the timer is stopped OUTREG32(&g_pWatchogTimerRegs->WSPR, WDOG_DISABLE_SEQ1); while( INREG32(&g_pWatchogTimerRegs->WWPS) ); OUTREG32(&g_pWatchogTimerRegs->WSPR, WDOG_DISABLE_SEQ2); while( INREG32(&g_pWatchogTimerRegs->WWPS) ); // Disable clock EnableDeviceClocks(g_WatchdogDevice, FALSE); } } }
//////////////////////////////////////////////////// // 功能: 关闭声音设备 // 输入: // 输出: // 返回: // 说明: //////////////////////////////////////////////////// void CloseMediaDevice(char channel) { int arg; int time; arg = ((channel == 0) ? RECORD_CHANNEL : PLAYBACK_CHANNEL ); //等待DMA结束 time = 0; while( INREG32(A_DMA_DTC(arg)) ) { #ifdef KPRINTF_DEF kprintf("close media device : count = %x\n",INREG32(A_DMA_DTC(arg))); #endif sTimerSleep(10, NULL); //加入延迟处理,防止死锁 time++; if( time > 10 ) { kdebug(mod_media, PRINT_WARNING, "close media device timer out\n"); break; } } //stop dma CLRREG32(A_DMA_DCS(arg), DCS_AR | DCS_HLT | DCS_CTE | DCS_CT); //close aic CLRREG32(AIC_CR, AIC_CR_ERPL); SETREG32(AIC_CR, AIC_CR_FLUSH_FIFO); OUTREG32(AIC_SR, 0x00000000); #ifndef CODEC_ALWAYS_OPEN CloseMediaCodecDevice(); #endif }
// Function: reset_display_controller // This function resets the display subsystem void reset_display_controller(void){ unsigned int reg_val,timeout,fclk, iclk; unsigned short count; // Enable all display clocks fclk = INREG32(0x4a009120);//CM_DSS_DSS_CLKCTRL // iclk = INREG32(CM_ICLKEN_DSS); // SETREG32(0x4a009120, 0x0502);//enable dss fclk // OUTREG32(0x4a009120, 0x00000502);//enable dss fclk // SETREG32(CM_ICLKEN_DSS, CM_CLKEN_DSS); // Reset the display controller OUTREG32(0x48041010, 1<<1);//DSI_SYSCONFIG // Wait until reset completes or timeout occurs timeout=10000; while(!((reg_val=INREG32(0x48041014)) & 1<<0) && (timeout > 0)){ //sys state for(count=0; count<DELAY_COUNT; ++count); timeout--; } if(!(reg_val & 1<<0)){ //puts("reset_display_controller: DSS reset timeout.\n"); } reg_val=INREG32(0x48041010);//DSI_SYSCONFIG reg_val &=~(1<<1); OUTREG32(0x48041010,reg_val); // Restore old clock settings OUTREG32(0x4a009120, fclk);//CM_DSS_DSS_CLKCTRL //OUTREG32(CM_ICLKEN_DSS, iclk); }
static void CheckDMAStatus(OMAP2420_DMA_REGS *pDMAReg, BOOL fEnabled) { DWORD dwCount = 0; DWORD dwValConfirm = INREG32(&pDMAReg->DMA4_CCR); if (fEnabled) { while ( !( dwValConfirm & DMA_CCR_ENABLE ) ) { // Put safety checking in case something is wrong if (dwCount++>DMA_SAFETY_LOOP_NUM) break; dwValConfirm = INREG32(&pDMAReg->DMA4_CCR); DEBUGMSG(ZONE_ERROR, (L"OMAP2420DMAContext::HWMapDMAMemory: " L"ERROR DMA safety checking = %d %08X\r\n", fEnabled, dwValConfirm )); } } else { while ( dwValConfirm & DMA_CCR_ENABLE ) { // Put safety checking in case something is wrong if (dwCount++>DMA_SAFETY_LOOP_NUM) break; dwValConfirm = INREG32(&pDMAReg->DMA4_CCR); DEBUGMSG(ZONE_ERROR, (L"OMAP2420DMAContext::HWMapDMAMemory: " L"ERROR DMA safety checking = %d %08X\r\n", fEnabled, dwValConfirm )); } } }
//------------------------------------------------------------------------------ void PrcmVoltSetErrorConfiguration( VoltageProcessor_e vp, UINT errorOffset, UINT errorGain ) { UINT val; switch (vp) { case kVoltageProcessor1: val = INREG32(&g_pPrcmPrm->pOMAP_GLOBAL_PRM->PRM_VP1_CONFIG); val &= ~(SMPS_ERROROFFSET_MASK | SMPS_ERRORGAIN_MASK); val |= ((errorGain << SMPS_ERRORGAIN_SHIFT) & SMPS_ERRORGAIN_MASK); val |= ((errorOffset << SMPS_ERROROFFSET_SHIFT) & SMPS_ERROROFFSET_MASK); OUTREG32(&g_pPrcmPrm->pOMAP_GLOBAL_PRM->PRM_VP1_CONFIG, val); break; case kVoltageProcessor2: val = INREG32(&g_pPrcmPrm->pOMAP_GLOBAL_PRM->PRM_VP2_CONFIG); val &= ~(SMPS_ERROROFFSET_MASK | SMPS_ERRORGAIN_MASK); val |= ((errorGain << SMPS_ERRORGAIN_SHIFT) & SMPS_ERRORGAIN_MASK); val |= ((errorOffset << SMPS_ERROROFFSET_SHIFT) & SMPS_ERROROFFSET_MASK); OUTREG32(&g_pPrcmPrm->pOMAP_GLOBAL_PRM->PRM_VP2_CONFIG, val); break; } }
/***************************************************************************** * 函 数 名 : nandReadBl * * 功能描述 : 根据实际长度读取BootLoader * * 输入参数 : dest BootLoader读取的目的地 * 输出参数 : * * 返 回 值 : OK 读取成功 * NAND_ECC_ERR ECC出现不可纠正的错误 * SEC_IMAGE_LEN_ERROR 长度错误 * * 其它说明 : * *****************************************************************************/ int nandReadBl( UINT32 dest ) { UINT32 blLen; UINT32 ulEccType; /* 配置IO复用,NAND取默认配置。*/ NF_IOS_SYS_CONFIG(); /* 配置脉宽为16 */ OUTREG32(NANDC_PWIDTH, 0x555); delay(10); /* 检查是否为Boot模式,如果不是,则直接重启,再次尝试读取 */ if(NANDC_OPMODE_BOOT != (INREG32(NANDC_CON) & NANDC_OPMODE_MASK)) { print_info("\r\nnot in boot mode,reboot to try..."); setErrno(NAND_NO_IN_BOOTMODE); wdtRebootDelayMs(TIME_DELAY_MS_6000_FOR_NF_OPBOOT); } /* 获取BootLoader长度 */ blLen = *(volatile UINT32 *)(FLASH_BOOT_ADDR+BL_LEN_INDEX); /* 获取ECC Type */ ulEccType = INREG32(NANDC_CON) & NAND_ECC_TYPE_MASK; /* 使能ECC情况下,产生ECC不可纠正的错误 */ if((NAND_ECC_TYPE_0 != ulEccType) && (INREG32(NANDC_INTS) & ECC_ERR_INVALID)) { print_info("\r\necc err!"); return NAND_ECC_ERR; } /* 判断长度是否合法:不为零/字对齐/不翻转/不过大 */ /* 0x1234ABCD - read retry failed */ /* 0xABCD1234 - all block(0 to 7) is bad */ if((0 == blLen) || (blLen % 4) || (blLen + IDIO_LEN + OEM_CA_LEN + IDIO_LEN < blLen) || (blLen + IDIO_LEN + OEM_CA_LEN + IDIO_LEN > BOOTLOAD_SIZE_MAX)) { print_info_with_u32("\r\nBL len err:", blLen); return SEC_IMAGE_LEN_ERROR; } /* 加上镜像签名、OEM CA和OEM CA签名的长度 (安全校验时才添加)*/ blLen += IDIO_LEN + OEM_CA_LEN + IDIO_LEN; delay(10); /* Boot模式下直接读取整个BootLoader */ memcpy((void*)dest, (void*)FLASH_BOOT_ADDR, blLen); return OK; }
U32 PDrvCryptoSaveDESRegisters(PUBLIC_CRYPTO_DES_DES3_CONTEXT * pDesDes3Ctx) { /* (1) : Save the IV if we are in CBC mode */ if (DES_CTRL_GET_MODE(INREG32(&g_pDESReg_t->DES_CTRL)) == DES_CTRL_MODE_CBC) { pDesDes3Ctx->registers.DES_IV_L = INREG32(&g_pDESReg_t->DES_IV_L); pDesDes3Ctx->registers.DES_IV_H = INREG32(&g_pDESReg_t->DES_IV_H); } return PUBLIC_CRYPTO_OPERATION_SUCCESS; }
void UFOE_DumpRegisters(void) { unsigned int i = 0; for (i = 0; i < 32; i += 16) { printk("UFOE+%04x : 0x%08x 0x%08x 0x%08x 0x%08x\n", i, INREG32((DISP_UFOE_BASE + 0x800+i)), INREG32((DISP_UFOE_BASE + 0x800+i+0x4)), INREG32((DISP_UFOE_BASE + 0x800+i+0x8)), INREG32((DISP_UFOE_BASE + 0x800+i+0xc))); } for (i = 0x700; i < 0x700 + 96; i += 16) { printk("UFOE+%04x : 0x%08x 0x%08x 0x%08x 0x%08x\n", i+0x800, INREG32((DISP_UFOE_BASE + 0x800+i)), INREG32((DISP_UFOE_BASE + 0x800+i+0x4)), INREG32((DISP_UFOE_BASE + 0x800+i+0x8)), INREG32((DISP_UFOE_BASE + 0x800+i+0xc))); } }
/*------------------------------------------------------------------------- *Save HWA registers into the specified operation state structure *-------------------------------------------------------------------------*/ static void PDrvCryptoSaveDESRegisters(u32 DES_CTRL, struct PUBLIC_CRYPTO_DES_OPERATION_STATE *pDESState) { dprintk(KERN_INFO "PDrvCryptoSaveDESRegisters in pDESState=%p CTRL=0x%08x\n", pDESState, DES_CTRL); /*Save the IV if we are in CBC mode */ if (DES_CTRL_GET_MODE(DES_CTRL) == DES_CTRL_MODE_CBC) { pDESState->DES_IV_L = INREG32(&pDESReg_t->DES_IV_L); pDESState->DES_IV_H = INREG32(&pDESReg_t->DES_IV_H); } }
LCD_STATUS LCD_Set_DrivingCurrent(LCM_PARAMS *lcm_params) { printf("LCD_Init_Driving:0x%x,0x%x,0x%x\n",INREG32(INFRA_DRV12),INREG32(INFRA_DRV5),INREG32(INFRA_DRV6)); if(1 == lcm_params->io_select_mode){// if DBI share DPI data pin MASKREG32(INFRA_DRV12, 0x0ffff000,(((lcm_params->dbi.io_driving_current >> 4) - 1) << 24)| (((lcm_params->dbi.io_driving_current >> 4) - 1) << 20)| (((lcm_params->dbi.io_driving_current >> 4) - 1) << 16)| (((lcm_params->dbi.io_driving_current >> 4) - 1) << 12)); MASKREG32(INFRA_DRV5, 0xffff0000,(((lcm_params->dbi.io_driving_current >> 4) - 1) << 28)| (((lcm_params->dbi.io_driving_current >> 4) - 1) << 24)| (((lcm_params->dbi.io_driving_current >> 4) - 1) << 20)| (((lcm_params->dbi.io_driving_current >> 4) - 1) << 16)); }
DSI_STATUS DSI_handle_TE(void) { unsigned int data_array; //data_array=0x00351504; //DSI_set_cmdq(&data_array, 1, 1); //lcm_mdelay(10); // RACT //data_array=1; //OUTREG32(&DSI_REG->DSI_RACK, data_array); // TE + BTA data_array=0x24; DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "[DISP] DSI_handle_TE TE + BTA !! \n"); OUTREG32(&DSI_CMDQ_REG->data0, data_array); //DSI_CMDQ_REG->data0.byte0=0x24; //DSI_CMDQ_REG->data0.byte1=0; //DSI_CMDQ_REG->data0.byte2=0; //DSI_CMDQ_REG->data0.byte3=0; DSI_REG->DSI_CMDQ_SIZE.CMDQ_SIZE=1; DSI_REG->DSI_START.DSI_START=0; DSI_REG->DSI_START.DSI_START=1; // wait TE Trigger status // printk("[DISP] wait TE Trigger status !! \n"); // do // { lcm_mdelay(10); data_array=INREG32(&DSI_REG->DSI_INTSTA); DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "[DISP] DSI INT state : %x !! \n", data_array); data_array=INREG32(&DSI_REG->DSI_TRIG_STA); DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "[DISP] DSI TRIG TE status check : %x !! \n", data_array); // } while(!(data_array&0x4)); // RACT DISP_LOG_PRINT(ANDROID_LOG_INFO, "DSI", "[DISP] DSI Set RACT !! \n"); data_array=1; OUTREG32(&DSI_REG->DSI_RACK, data_array); return DSI_STATUS_OK; }
//------------------------------------------------------------------------------ // // Function: OALStall // // Wait for time specified in parameter in microseconds (busy wait). This // function can be called in hardware/kernel initialization process. // // NOTE: This function should not be called before the TMU is enabled. // // NOTE: This function should only be used to delay for short amounts // of time. See comments in the code below. // // NOTE: This function will wait for a minimum of microSec microseconds. // It may wait longer than that if the system is busy handling // many interrupts, or if the owner process gets put to sleep // by the kernel scheduler. // VOID OALStall(UINT32 microSec) { UINT32 baseTime, curTime, delta; UINT64 numWaitCounts, elapsedWaitCounts = 0; volatile SH4_TMU_REGS *pTMURegs = OALPAtoUA(SH4_REG_PA_TMU); // First, get current TMU counter value baseTime = INREG32(&pTMURegs->TCNT0); // Check for invalid parameters and status if (microSec == 0 || g_oalTimer.countsPerMSec == 0) { return; } // If called with a large value for the microSec parameter // and the timer ticks at a high frequency (i.e., there are a // large number of ticks in each millisecond), it is possible // that this calculation will overflow, and thus this function // will wait for less time than was requested. numWaitCounts = (microSec * g_oalTimer.countsPerMSec) / 1000; while ( elapsedWaitCounts < numWaitCounts ) { // To wait for an accurate number of milliseconds, we need to // account for timer underflow. Thus, we need to calculate // the delta seen in the TMU between this iteration of the // while loop and the previous iteration, and use the delta as // the basis for updating the elapsed time. curTime = INREG32(&pTMURegs->TCNT0); if (curTime < baseTime) // Timer unit has counted down, but no underflow { delta = (baseTime - curTime); } else if (baseTime < curTime) // Timer unit has underflowed and rolled over { delta = g_oalTimer.countsPerMSec - curTime + baseTime + 1; } else { delta = 0; } elapsedWaitCounts += delta; // Update the TMU base count for the next iteration baseTime = curTime; } }
//------------------------------------------------------------------------------ // // Function: reset_display_controller // // This function resets the Display Sub System on omap24xx // void reset_display_controller( void ) { UINT32 reg_val; UINT16 count; UINT32 timeout; UINT32 fclk, iclk; OMAP_PRCM_DSS_CM_REGS *pPrcmRegs = OALPAtoUA(OMAP_PRCM_DSS_CM_REGS_PA); OMAP_DISPC_REGS *pDisplayRegs = OALPAtoUA(OMAP_DISC1_REGS_PA); //OALMSG(OAL_INFO, (L"reset_display_controller+\r\n")); // enable all display clocks fclk = INREG32(&pPrcmRegs->CM_FCLKEN_DSS); iclk = INREG32(&pPrcmRegs->CM_ICLKEN_DSS); OUTREG32(&pPrcmRegs->CM_FCLKEN_DSS, (fclk | CM_CLKEN_DSS1 | CM_CLKEN_DSS2 | CM_CLKEN_TV)); OUTREG32(&pPrcmRegs->CM_ICLKEN_DSS, (iclk | CM_CLKEN_DSS)); // disable the display controller disable_dss(); // reset the display controller OUTREG32(&pDisplayRegs->DISPC_SYSCONFIG, DISPC_SYSCONFIG_SOFTRESET); // wait until reset completes OR timeout occurs timeout=10000; while(!((reg_val=INREG32(&pDisplayRegs->DISPC_SYSSTATUS)) & DISPC_SYSSTATUS_RESETDONE) && (timeout > 0)) { // delay for(count=0;count<DELAY_COUNT;++count); timeout--; } if(!(reg_val & DISPC_SYSSTATUS_RESETDONE)) { // OALMSG(OAL_INFO, (L"reset_display_controller: DSS reset timeout\r\n")); } reg_val=INREG32(&pDisplayRegs->DISPC_SYSCONFIG); reg_val &=~(DISPC_SYSCONFIG_SOFTRESET); OUTREG32(&pDisplayRegs->DISPC_SYSCONFIG,reg_val); // restore old clock settings OUTREG32(&pPrcmRegs->CM_FCLKEN_DSS, fclk); OUTREG32(&pPrcmRegs->CM_ICLKEN_DSS, iclk); //OALMSG(OAL_INFO, (L"reset_display_controller-\r\n")); }
/*---------------------------------------------------------------------------- *Save HWA registers into the specified operation state structure *--------------------------------------------------------------------------*/ static void tf_aes_save_registers( struct tf_crypto_aes_operation_state *aes_state) { dprintk(KERN_INFO "tf_aes_save_registers: " "aes_state(%p) <- paes_reg(%p): CTRL=0x%08x\n", aes_state, paes_reg, aes_state->CTRL); /*Save the IV if we are in CBC or CTR mode (not required for ECB) */ if (!AES_CTRL_IS_MODE_ECB(aes_state->CTRL)) { aes_state->AES_IV_0 = INREG32(&paes_reg->AES_IV_IN_0); aes_state->AES_IV_1 = INREG32(&paes_reg->AES_IV_IN_1); aes_state->AES_IV_2 = INREG32(&paes_reg->AES_IV_IN_2); aes_state->AES_IV_3 = INREG32(&paes_reg->AES_IV_IN_3); } }
void LcdPdd_LCD_Initialize(void){ unsigned int val = 0; val = INREG32(0x4a009120);//CM_DSS_DSS_CLKCTRL val = val & ~(0x0502); // Setup the DSS1 clock divider - disable DSS1 clock, change divider, enable DSS clock OUTREG32(0x4a009120, val);//CM_DSS_DSS_CLKCTRL udelay(10000); SETREG32(0x4a00815c, 8<<0);//CM_DIV_M5_DPLL_PER udelay(10000); //printf("CM_CLKSEL_DSS= %x\n",INREG32(CM_CLKSEL_DSS)); val = INREG32(0x4a009120) ;//CM_DSS_DSS_CLKCTRL val = val | 0x0502; OUTREG32(0x4a009120, 0x00000502); udelay(10000); // LCD control xxxx xxxx xxxx 0000 0000 0010 0000 1001 OUTREG32(0x48041238, DISPC_CONTROL_TFTDATALINES_24 | DISPC_CONTROL_STNTFT);//DISPC_CONTROL2 // Default Color OUTREG32(0x480413ac, 0x00000000);//DISPC_DEFAULT_COLOR2 // LCD control xxxx xxxx xxxx 0000 0000 0010 0000 1001 SETREG32(0x48041238, 0<<12);//DISPC_CONTROL2 OVERLAYOPTIMIZATION // Default Transparency Color OUTREG32(0x480413b0, 0);//DISPC_TRANS_COLOR2 SETREG32(0x48041044, 0x4<<0);//DISPC_CONFIG1 LOAD_MODE: Frame data only loaded every frame //////////////////////////////////////////////////////////////////////////////////////////////////////////// // Signal configuration // OUTREG32(0x48041408,DISPC_POL_FREQ_ONOFF);//DISPC_POL_FREQ2 OUTREG32(0x48041408,0x00003000);//DISPC_POL_FREQ2 udelay(10000); // Configure the divisor OUTREG32(0x4804140c,DISPC_DIVISOR_R(LCD_PIXCLKDIV,LCD_LOGCLKDIV));//DISPC_DIVISOR2 (PCD 4,LCD 1) // Configure the panel size OUTREG32(0x480413cc,DISPC_SIZE_LCD_R(LCD_HEIGHT,LCD_WIDTH));//DISPC_SIZE_LCD2 (1024,600) // Timing logic for HSYNC signal OUTREG32(0x48041400,DISPC_TIMING(LCD_HSW-1,LCD_HFP-1,LCD_HBP-1));//DISPC_TIMING_H2 // Timing logic for VSYNC signal OUTREG32(0x48041404,DISPC_TIMING(LCD_VSW-1,LCD_VFP,LCD_VBP));//DISPC_TIMING_V2 /////////////////////////////////////////////////////////////////////////////////////////////////////////////// }
U32 PDrvCryptoUpdateDES(PUBLIC_CRYPTO_DES_DES3_CONTEXT * pDesDes3Ctx, U8 * pSrc, U8 * pDest, U32 nbBlocks, U32 dmaUse) { U32 nbr_of_blocks; U8 * pProcessSrc; U8 * pProcessDest; U32 vTemp; pProcessSrc = pSrc; pProcessDest = pDest; if ((dmaUse == PUBLIC_CRYPTO_DMA_USE_POLLING) || (dmaUse == PUBLIC_CRYPTO_DMA_USE_IRQ)) { return PDrvCryptoUpdateDESWithDMA(pDesDes3Ctx, pSrc, pDest, nbBlocks, dmaUse); } for (nbr_of_blocks = 0; nbr_of_blocks < nbBlocks ; nbr_of_blocks++) { /* (2) : We wait for the input ready */ if (scxPublicCryptoWaitForReadyBit((VU32 *) &g_pDESReg_t->DES_CTRL, DES_CTRL_INPUT_READY_BIT) != PUBLIC_CRYPTO_OPERATION_SUCCESS) { return PUBLIC_CRYPTO_ERR_TIMEOUT; } /* (3) : We copy the 8 bytes of data src->reg */ vTemp = (U32) BYTES_TO_LONG(pProcessSrc); OUTREG32(&g_pDESReg_t->DES_DATA_L, vTemp); pProcessSrc += 4; vTemp = (U32) BYTES_TO_LONG(pProcessSrc); OUTREG32(&g_pDESReg_t->DES_DATA_H, vTemp); pProcessSrc += 4; /* (4) : We wait for the output ready */ if (scxPublicCryptoWaitForReadyBit((VU32 *) &g_pDESReg_t->DES_CTRL, DES_CTRL_OUTPUT_READY_BIT) != PUBLIC_CRYPTO_OPERATION_SUCCESS) { return PUBLIC_CRYPTO_ERR_TIMEOUT; } /* (5) : We copy the 8 bytes of data reg->dest */ vTemp = INREG32(&g_pDESReg_t->DES_DATA_L); LONG_TO_BYTE(pProcessDest, vTemp); pProcessDest += 4; vTemp = INREG32(&g_pDESReg_t->DES_DATA_H); LONG_TO_BYTE(pProcessDest, vTemp); pProcessDest += 4; } return PUBLIC_CRYPTO_OPERATION_SUCCESS; }
static void enable_tv_detect(bool tv_enable) { // disable ACCDET unit before switch the detect way OUTREG32(ACCDET_CTRL, ACCDET_DISABLE); OUTREG32(ACCDET_STATE_SWCTRL, 0); if(tv_enable) { } else { // switch analog switch from tv out to mic OUTREG32(ACCDET_STATE_SWCTRL, ACCDET_SWCTRL_EN); // init the accdet MIC detect unit SETREG32(ACCDET_RSTB, MIC_INIT_BIT); CLRREG32(ACCDET_RSTB, MIC_INIT_BIT); } ACCFIX_DEBUG("[accfix]enable_tv_detect:ACCDET_STATE_SWCTRL =%x\n", INREG32(ACCDET_STATE_SWCTRL)); // enable ACCDET unit OUTREG32(ACCDET_CTRL, ACCDET_ENABLE); }
uint32 ReadReg32(uint32 addr) { if (gInfo.sharedInfo->chipType == S3_TRIO64) return ReadPIO(addr, 4); return INREG32(addr); }
//------------------------------------------------------------------------------ // // Function: Omap37xx_per_dpll_init // // Helper function to initialize OMAP 37xx/36xx Peripheral DPLL. // void Omap37xx_per_dpll_init(void) { OMAP_PRCM_CLOCK_CONTROL_CM_REGS* pPrcmClkCM = OALPAtoUA(OMAP_PRCM_CLOCK_CONTROL_CM_REGS_PA); unsigned int val; //--------------------------------- // setup dpll timings for core and peripheral dpll // // configure clock ratios for 120m OUTREG32(&pPrcmClkCM->CM_CLKSEL5_PLL, BSP_CM_CLKSEL5_PLL); // configure m:n clock ratios as well as frequency selection for core dpll OUTREG32(&pPrcmClkCM->CM_CLKSEL4_PLL, BSP_CM_CLKSEL4_PLL); // lock dpll with correct frequency selection /* val = (BSP_EN_PERIPH2_DPLL_LPMODE | BSP_PERIPH2_DPLL_RAMPTIME | \ BSP_EN_PERIPH2_DPLL_DRIFTGUARD | BSP_EN_PERIPH2_DPLL);*/ val = (BSP_EN_PERIPH2_DPLL_LPMODE | BSP_PERIPH2_DPLL_RAMPTIME | \ BSP_EN_PERIPH2_DPLL); OUTREG32(&pPrcmClkCM->CM_CLKEN2_PLL, val); while ((INREG32(&pPrcmClkCM->CM_IDLEST2_CKGEN) & DPLL_STATUS_MASK) != DPLL_STATUS_LOCKED); }
//------------------------------------------------------------------------------ BOOL InitSystemControl() { #if 0 OALMSG(OAL_ETHER&&OAL_FUNC, (L"+USBFN:: Initialize System Control\r\n")); { DWORD temp, mode; OMAP2420_SYSC1_REGS *pSysConRegs = OALPAtoUA(OMAP2420_SYSC1_REGS_PA); temp = INREG32(&pSysConRegs->ulCONTROL_DEVCONF); mode = USBX_TRX_MODE; // Clear USBT0WRIMODEI. This places the USB Controls in Unidirectional Mode temp &= 0xFF3FFFFF; // Set the Transceiver Interface Mode for USB Port 0 if ((mode == 0x01) || (mode == 0x02)) { // Change the mode to Bidirectional. temp |= 0x00800000; } // Make sure the USB Enable signal is being used as an Active-High signal temp &= 0xFFFEFFFF; // Make sure the USB module standby signal is not asserted temp &= 0xFFFF7FFF; OUTREG32(&pSysConRegs->ulCONTROL_DEVCONF, temp); } OALMSG(OAL_ETHER&&OAL_FUNC, (L"-USBFN:: Initialize System Control\r\n")); #endif return TRUE; }
//------------------------------------------------------------------------------ BOOL PrcmDomainResetStatus( UINT powerDomain, UINT *pResetStatus, BOOL bClear ) { // get the prm register for the domain // BOOL rc = FALSE; UINT resetStatus; OMAP_PRM_REGS *pPrmRegs = GetPrmRegisterSet(powerDomain); if (powerDomain == POWERDOMAIN_WAKEUP || pPrmRegs == NULL) goto cleanUp; // get current status resetStatus = INREG32(&pPrmRegs->RM_RSTST_xxx); if (pResetStatus) *pResetStatus = resetStatus; // clear status if requested if (bClear) OUTREG32(&pPrmRegs->RM_RSTST_xxx, resetStatus); rc = TRUE; cleanUp: return rc; }
* 返 回 值 : * * 其它说明 : * *****************************************************************************/ INT32 handerExecDataPkt( apDlCtrlS *pstDlCtrl ) { INT32 iRet; int BOOT_RST_Addr; if(!pstDlCtrl->bComplete) { (void)sendRepPkt(pstDlCtrl, REP_FILE_RECV_ERR); return ERROR; } iRet = apSecChk(pstDlCtrl->ulAddress); if(SEC_SUCCESS == iRet ||SEC_EFUSE_NOT_WRITE == iRet) { #ifdef START_TIME_TEST print_info_with_u32("\r\ntime(ms):", (TIMER5_INIT_VALUE - INREG32(TIMER5_REGOFF_VALUE))/MS_TICKS); #endif ocrShareSave(); (void)sendRepPkt(pstDlCtrl, REP_ACK); /* 不再返回 */ BOOT_RST_Addr = *(volatile UINT32 *)(pstDlCtrl->ulAddress + BOOT_RST_ADDR_OFFEST); go((FUNCPTR)(pstDlCtrl->ulAddress + BOOT_RST_Addr)); } else { /* 发送校验失败,等待AP复位,不再返回 */
//------------------------------------------------------------------------------ // // Function: OEMPlatformDeinit // static VOID OEMPlatformDeinit( ) { OMAP_GPTIMER_REGS *pTimerRegs = OALPAtoUA(OMAP_GPTIMER1_REGS_PA); // Soft reset GPTIMER OUTREG32(&pTimerRegs->TIOCP, SYSCONFIG_SOFTRESET); // While until done while ((INREG32(&pTimerRegs->TISTAT) & GPTIMER_TISTAT_RESETDONE) == 0); // Disable device clocks that were used by the bootloader EnableDeviceClocks(OMAP_DEVICE_GPIO1,FALSE); EnableDeviceClocks(OMAP_DEVICE_GPIO2,FALSE); EnableDeviceClocks(OMAP_DEVICE_GPIO3,FALSE); EnableDeviceClocks(OMAP_DEVICE_GPIO4,FALSE); EnableDeviceClocks(OMAP_DEVICE_GPIO5,FALSE); EnableDeviceClocks(OMAP_DEVICE_GPIO6,FALSE); EnableDeviceClocks(OMAP_DEVICE_GPTIMER2,FALSE); EnableDeviceClocks(OMAP_DEVICE_UART1,FALSE); EnableDeviceClocks(OMAP_DEVICE_UART2,FALSE); EnableDeviceClocks(OMAP_DEVICE_UART3,FALSE); EnableDeviceClocks(OMAP_DEVICE_MMC1,FALSE); EnableDeviceClocks(OMAP_DEVICE_MMC2,FALSE); EnableDeviceClocks(OMAP_DEVICE_I2C1,FALSE); EnableDeviceClocks(OMAP_DEVICE_I2C2,FALSE); EnableDeviceClocks(OMAP_DEVICE_I2C3,FALSE); }
void OMAP2420DMAContext::HWStopOutputDMA() { OMAP2420_DMA_REGS *pDMAReg; DWORD i, dwVal; DEBUGMSG(ZONE_FUNCTION, (L"+OMAP2420DMAContext::HWStopOutputDMA()\r\n")); pDMAReg = m_pOutDMAReg; // disable the DMA channel link and wait for writing to finish CLRREG32(&pDMAReg->DMA4_CLNK_CTRL, DMA_CLNK_CTRL_ENABLE_LINK); dwVal = INREG32(&pDMAReg->DMA4_CCR); for (i = 0; (i < DMA_SAFETY_LOOP_NUM) && (dwVal & DMA_CCR_WR_ACTIVE); i++) { Sleep(1); dwVal = INREG32(&pDMAReg->DMA4_CCR); } // disable DMA on the channel CLRREG32(&pDMAReg->DMA4_CCR, DMA_CCR_ENABLE); // clear pending interrupts OUTREG32(&pDMAReg->DMA4_CSR, INREG32(&pDMAReg->DMA4_CSR)); DMA_ControllerSet(m_hCont, DMACP_L2IntAck, 1 << AUDIO_OUTPUT_DMA_CHANNEL); // disable the rest of the channel HWEnableOutputChannel(FALSE); #if defined(DEBUG) DumpDMA_LC(L"Stop Output", pDMAReg); CheckDMAStatus(pDMAReg, FALSE); #endif #ifdef PROFILE_MIXER LARGE_INTEGER liTotalTime; LARGE_INTEGER liMixerTime; GetOutputDeviceContext(0)->StopMixerProfiler(&liTotalTime,&liMixerTime); DEBUGMSG(ZONE_DMA,(L"OMAP2420DMAContext::HWStopOutputDMA: " L"Total play time: %dms, %dms while mixing\r\n", (DWORD) (liTotalTime.QuadPart), (DWORD) (liMixerTime.QuadPart) )); #endif DEBUGMSG(ZONE_FUNCTION, (L"-OMAP2420DMAContext::HWStopOutputDMA()\r\n")); }
//------------------------------------------------------------------------------ // // Function: ISP_InReg32 // // Read data from register // BOOL ISP_InReg32( volatile UINT32* address, UINT32* data ) { *data = INREG32(address); return TRUE; }