/* ** For each end of frame interrupt base and ceiling is reconfigured */ static void LCDIsr(void) { unsigned int status; #ifdef _TMS320C6X IntEventClear(SYS_INT_LCDC_INT); #else IntSystemStatusClear(SYS_INT_LCDINT); #endif status = RasterIntStatus(SOC_LCDC_0_REGS,RASTER_END_OF_FRAME0_INT_STAT | RASTER_END_OF_FRAME1_INT_STAT ); status = RasterClearGetIntStatus(SOC_LCDC_0_REGS, status); /* Read the timer counter, to see how much time has elapsed */ /*if(trIndex < TIME_ELAPSED_INST) frameTransferRate[trIndex++] = TimerCounterGet(SOC_TMR_2_REGS, TMR_TIMER12);*/ if (status & RASTER_END_OF_FRAME0_INT_STAT) { flagA = 1; } if(status & RASTER_END_OF_FRAME1_INT_STAT) { flagB = 1; } /* since the frame buffers are constant no need to re-configure again.*/ }
/* ** VPIF Interrupt service routine. */ static void VPIFIsr(void) { #ifdef _TMS320C6X IntEventClear(SYS_INT_VPIF_INT); #else IntSystemStatusClear(SYS_INT_VPIF); #endif /* If previously captured frame not processed, clear this interrupt and return */ if (!processed) { VPIFInterruptStatusClear(SOC_VPIF_0_REGS, VPIF_FRAMEINT_CH0); return; } /* buffcount represents buffer to be given to capture driver and * buffcount2 represents the newly captured buffer to be processed */ processed = 0; captured = 0; buffcount++; buffcount2 = buffcount - 1; /* Currently only two buffers are being used for capture */ if (buffcount == 2) buffcount = 0; /* Invalidate the buffers before giving to capture driver*/ #ifdef _TMS320C6X CacheInv((unsigned int) buff_luma[buffcount], CAPTURE_IMAGE_WIDTH * CAPTURE_IMAGE_HEIGHT * 2); CacheInv((unsigned int) buff_chroma[buffcount], CAPTURE_IMAGE_WIDTH * CAPTURE_IMAGE_HEIGHT * 2); #else CP15ICacheFlushBuff((unsigned int) buff_luma[buffcount], CAPTURE_IMAGE_WIDTH * CAPTURE_IMAGE_HEIGHT * 2); CP15ICacheFlushBuff((unsigned int) buff_chroma[buffcount], CAPTURE_IMAGE_WIDTH * CAPTURE_IMAGE_HEIGHT * 2); #endif /* Initialize buffer addresses for a new frame*/ VPIFCaptureFBConfig(SOC_VPIF_0_REGS, VPIF_CHANNEL_0, VPIF_TOP_FIELD, VPIF_LUMA, (unsigned int) buff_luma[buffcount], CAPTURE_IMAGE_WIDTH*2); VPIFCaptureFBConfig(SOC_VPIF_0_REGS, VPIF_CHANNEL_0, VPIF_TOP_FIELD, VPIF_CHROMA, (unsigned int) buff_chroma[buffcount], CAPTURE_IMAGE_WIDTH*2); VPIFCaptureFBConfig(SOC_VPIF_0_REGS, VPIF_CHANNEL_0, VPIF_BOTTOM_FIELD, VPIF_LUMA, (unsigned int) (buff_luma[buffcount] + CAPTURE_IMAGE_WIDTH), CAPTURE_IMAGE_WIDTH*2); VPIFCaptureFBConfig(SOC_VPIF_0_REGS, VPIF_CHANNEL_0, VPIF_BOTTOM_FIELD, VPIF_CHROMA, (unsigned int) (buff_chroma[buffcount] + CAPTURE_IMAGE_WIDTH), CAPTURE_IMAGE_WIDTH*2); /* Initialize buffer addresses with the captured frame ready to be processed */ videoTopC = buff_chroma[buffcount2]; videoTopY = buff_luma[buffcount2]; captured = 1; /* clear interrupt */ VPIFInterruptStatusClear(SOC_VPIF_0_REGS, VPIF_FRAMEINT_CH0); }
/* ** Error ISR for McASP */ static void McASPErrorIsr(void) { #ifdef _TMS320C6X IntEventClear(SYS_INT_MCASP0_INT); #else IntSystemStatusClear(SYS_INT_MCASPINT); #endif ; /* Perform any error handling here.*/ }
static void PWMTZIsr(void) { #ifdef _TMS320C6X IntEventClear(SYS_INT_EHRPWM1TZ); #else IntSystemStatusClear(SYS_INT_EHRPWM1TZ); #endif EHRPWMTZFlagClear(SOC_EHRPWM_1_REGS, EHRPWM_TZ_CYCLEBYCYCLE_CLEAR); }
/* ** ISR to handler i2c interrupts */ void I2CCodecIsr(void) { unsigned int intCode = 0; unsigned int sysIntNum = 0; /* Get interrupt vector code */ intCode = I2CInterruptVectorGet(savedBase); if(SOC_I2C_0_REGS == savedBase) { #ifdef _TMS320C6X sysIntNum = SYS_INT_I2C0_INT; #else sysIntNum = SYS_INT_I2CINT0; #endif } else { intCode = 0; } while(intCode!=0) { /* Clear status of interrupt */ #ifdef _TMS320C6X IntEventClear(sysIntNum); #else IntSystemStatusClear(sysIntNum); #endif if (intCode == I2C_INTCODE_TX_READY) { I2CMasterDataPut(savedBase, slaveData[dataIdx]); dataIdx++; } if(intCode == I2C_INTCODE_RX_READY) { slaveData[dataIdx] = I2CMasterDataGet(savedBase); dataIdx++; } if (intCode == I2C_INTCODE_STOP) { /* Disable transmit data ready and receive data read interupt */ I2CMasterIntDisableEx(savedBase, I2C_INT_TRANSMIT_READY | I2C_INT_DATA_READY); txCompFlag = 0; } intCode = I2CInterruptVectorGet(savedBase); } }
/* ** For each end of frame interrupt base and ceiling is reconfigured */ static void LCDIsr(void) { unsigned int status; #ifdef _TMS320C6X IntEventClear(SYS_INT_LCDC_INT); #else IntSystemStatusClear(SYS_INT_LCDINT); #endif /* Find which interrupt occurred and clear it */ status = RasterIntStatus(SOC_LCDC_0_REGS, RASTER_END_OF_FRAME0_INT_STAT | RASTER_END_OF_FRAME1_INT_STAT); status = RasterClearGetIntStatus(SOC_LCDC_0_REGS, status); /* Display the appropriate output buffer on the appropriate raster buffer * and if a new processed buffer is available, let the DSP know that * it has configured the raster buffer to point to the new output buffer * by updating the 'updated' flag */ if (display_buff_1) { if (status & RASTER_END_OF_FRAME0_INT_STAT) { RasterDMAFBConfig(SOC_LCDC_0_REGS, (unsigned int) Rgb_buffer1, (unsigned int) (Rgb_buffer1 + DISPLAY_IMAGE_WIDTH * DISPLAY_IMAGE_HEIGHT + 15), 0); if (changed) updated = updated | 0x1; } if (status & RASTER_END_OF_FRAME1_INT_STAT) { RasterDMAFBConfig(SOC_LCDC_0_REGS, (unsigned int) Rgb_buffer1, (unsigned int) (Rgb_buffer1 + DISPLAY_IMAGE_WIDTH * DISPLAY_IMAGE_HEIGHT + 15), 1); if (changed) updated = updated | 0x2; } } else { if (status & RASTER_END_OF_FRAME0_INT_STAT) { RasterDMAFBConfig(SOC_LCDC_0_REGS, (unsigned int) Rgb_buffer2, (unsigned int) (Rgb_buffer2 + DISPLAY_IMAGE_WIDTH * DISPLAY_IMAGE_HEIGHT + 15), 0); if (changed) updated = updated | 0x1; } if (status & RASTER_END_OF_FRAME1_INT_STAT) { RasterDMAFBConfig(SOC_LCDC_0_REGS, (unsigned int) Rgb_buffer2, (unsigned int) (Rgb_buffer2 + DISPLAY_IMAGE_WIDTH * DISPLAY_IMAGE_HEIGHT + 15), 1); if (changed) updated = updated | 0x2; } } }
/* ** For each end of frame interrupt base and ceiling is reconfigured */ static void LCDIsr(void) { unsigned int status; #ifdef _TMS320C6X IntEventClear(SYS_INT_LCDC_INT); #else IntSystemStatusClear(SYS_INT_LCDINT); #endif status = RasterIntStatus(SOC_LCDC_0_REGS,RASTER_END_OF_FRAME0_INT_STAT | RASTER_END_OF_FRAME1_INT_STAT ); status = RasterClearGetIntStatus(SOC_LCDC_0_REGS, status); }
static void PWMEventIsr(void) { #ifdef _TMS320C6X IntEventClear(SYS_INT_EHRPWM1); #else IntSystemStatusClear(SYS_INT_EHRPWM1); #endif EHRPWMETIntClear(SOC_EHRPWM_1_REGS); #ifdef SYNC_EN EHRPWMTriggerSWSync(SOC_EHRPWM_1_REGS); #endif }
/* ** Timer Interrupt Service Routine */ static void TimerIsr(void) { /* Disable the timer interrupt */ TimerIntDisable(SOC_TMR_2_REGS, TMR_INT_TMR12_NON_CAPT_MODE); #ifdef _TMS320C6X /* Clear interrupt status in DSPINTC */ IntEventClear(SYS_INT_T64P2_TINTALL); #else /* Clear the interrupt status in AINTC */ IntSystemStatusClear(SYS_INT_TIMR2_ALL); #endif TimerIntStatusClear(SOC_TMR_2_REGS, TMR_INT_TMR12_NON_CAPT_MODE); /* Signal application to print a new character */ flagIsrCnt = 1; /* Enable the timer interrupt */ TimerIntEnable(SOC_TMR_2_REGS, TMR_INT_TMR12_NON_CAPT_MODE); }
/* ** EDMA transfer completion ISR */ static void EDMA3CCComplIsr(void) { #ifdef _TMS320C6X IntEventClear(SYS_INT_EDMA3_0_CC0_INT1); #else IntSystemStatusClear(SYS_INT_CCINT0); #endif /* Check if receive DMA completed */ if(EDMA3GetIntrStatus(SOC_EDMA30CC_0_REGS) & (1 << EDMA3_CHA_MCASP0_RX)) { /* Clear the interrupt status for the 0th channel */ EDMA3ClrIntr(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_RX); McASPRxDMAComplHandler(); } /* Check if transmit DMA completed */ if(EDMA3GetIntrStatus(SOC_EDMA30CC_0_REGS) & (1 << EDMA3_CHA_MCASP0_TX)) { /* Clear the interrupt status for the first channel */ EDMA3ClrIntr(SOC_EDMA30CC_0_REGS, EDMA3_CHA_MCASP0_TX); McASPTxDMAComplHandler(); } }
//***************************************************************************** // //! The USB device interrupt handler. //! //! This the main USB interrupt handler entry point for use in USB device //! applications. This top-level handler will branch the interrupt off to the //! appropriate application or stack handlers depending on the current status //! of the USB controller. //! //! Applications which operate purely as USB devices (rather than dual mode //! applications which can operate in either device or host mode at different //! times) must ensure that a pointer to this function is installed in the //! interrupt vector table entry for the USB0 interrupt. For dual mode //! operation, the vector should be set to point to \e USB0DualModeIntHandler() //! instead. //! //! \return None. // //***************************************************************************** void USB0DeviceIntHandler(void) { unsigned int ulStatus = 0; #if defined(am335x) || defined (am335x_15x15) || defined(c6a811x) || defined(am386x) || \ defined(c6741x) unsigned int epStatus = 0; // // Get the controller interrupt status. // ulStatus = HWREG(g_USBInstance[0].uiSubBaseAddr + USB_0_IRQ_STATUS_1); // // Get the EP interrupt status. // epStatus = HWREG(g_USBInstance[0].uiSubBaseAddr + USB_0_IRQ_STATUS_0); // // Clear the controller interrupt status. // HWREG(g_USBInstance[0].uiSubBaseAddr + USB_0_IRQ_STATUS_1) = ulStatus; // // Clear the EP interrupt status. // HWREG(g_USBInstance[0].uiSubBaseAddr + USB_0_IRQ_STATUS_0) = epStatus; #ifdef DMA_MODE HWREG(USBSS_BASE + USBSS_IRQ_STATUS) = HWREG(USBSS_BASE + USBSS_IRQ_STATUS); #endif // //Call the Interrupt Handler. // USBDeviceIntHandlerInternal(0, ulStatus, &epStatus); // //End of Interrupts. // HWREG(g_USBInstance[0].uiSubBaseAddr + USB_0_IRQ_EOI) = 0; #ifdef DMA_MODE HWREG(USBSS_BASE + USBSS_IRQ_EOI) = 0; #endif #else // // Get the controller interrupt status. // ulStatus = HWREG(g_USBInstance[0].uiSubBaseAddr + USB_0_INTR_SRC); // Clear the Interrupts HWREG(g_USBInstance[0].uiSubBaseAddr + USB_0_INTR_SRC_CLEAR) = ulStatus; #ifdef _TMS320C6X IntEventClear(g_USBInstance[0].uiInterruptNum); #else IntSystemStatusClear(g_USBInstance[0].uiInterruptNum); #endif // // Call the internal handler. // USBDeviceIntHandlerInternal(0, ulStatus, NULL); // End of Interrupts HWREG(g_USBInstance[0].uiSubBaseAddr + USB_0_END_OF_INTR) = 0; #endif }
void UARTIsr() { //static unsigned int length = sizeof(txArray); //static unsigned int count = 0; char rxData = 0; unsigned int int_id = 0; static char *inBufferPtr = inBuffer; static char traceBuf[2] = {'\0', '\0'}; do { /* This determines the cause of UART2 interrupt.*/ int_id = UARTIntStatus(SOC_UART_2_REGS); #ifdef _TMS320C6X // Clear UART2 system interrupt in DSPINTC IntEventClear(SYS_INT_UART2_INT); #else /* Clears the system interupt status of UART2 in AINTC. */ IntSystemStatusClear(SYS_INT_UARTINT2); #endif #if 0 /* Checked if the cause is transmitter empty condition.*/ if(UART_INTID_TX_EMPTY == int_id) { if(0 < length) { /* Write a byte into the THR if THR is free. */ UARTCharPutNonBlocking(SOC_UART_2_REGS, txArray[count]); length--; count++; } if(0 == length) { /* Disable the Transmitter interrupt in UART.*/ UARTIntDisable(SOC_UART_2_REGS, UART_INT_TX_EMPTY); } } #endif /* Check if the cause is receiver data condition.*/ if(UART_INTID_RX_DATA == int_id) { rxData = UARTCharGetNonBlocking(SOC_UART_2_REGS); if (uartNewString == 0) { if (rxData == '\r') { *inBufferPtr = '\0'; uartNewString = 1; inBufferPtr = inBuffer; /* Disable the Receiver interrupt in UART.*/ //UARTIntDisable(SOC_UART_2_REGS, UART_INT_RXDATA_CTI); } else { *inBufferPtr = rxData; inBufferPtr++; if (inBufferPtr >= (inBuffer + inBufferSize)) inBufferPtr--; else { *traceBuf = rxData; trace(traceBuf); } } } //UARTCharPutNonBlocking(SOC_UART_2_REGS, rxData); } /* Check if the cause is receiver line error condition.*/ if(UART_INTID_RX_LINE_STAT == int_id) { while(UARTRxErrorGet(SOC_UART_2_REGS)) { /* Read a byte from the RBR if RBR has data.*/ UARTCharGetNonBlocking(SOC_UART_2_REGS); } } } while (int_id); return; }
/* ** ISR to handler i2c interrupts */ static void I2C0Isr(void) { volatile unsigned int intCode = 0; /* Get interrupt vector code */ intCode = I2CInterruptVectorGet(SOC_I2C_0_REGS); while(intCode!=0) { /* Clear status of interrupt */ #ifdef _TMS320C6X IntEventClear(SYS_INT_I2C0_INT); #else IntSystemStatusClear(15); #endif if (intCode == I2C_INTCODE_TX_READY) { I2CMasterDataPut(SOC_I2C_0_REGS, slaveData[dataIdx]); dataIdx++; } if(intCode == I2C_INTCODE_RX_READY) { slaveData[dataIdx] = I2CMasterDataGet(SOC_I2C_0_REGS); dataIdx++; } if (intCode == I2C_INTCODE_STOP) { I2CMasterIntDisableEx(SOC_I2C_0_REGS, I2C_INT_TRANSMIT_READY | I2C_INT_DATA_READY | I2C_INT_NO_ACK | I2C_INT_STOP_CONDITION); txCompFlag = 0; } if (intCode == I2C_INTCODE_NACK) { I2CMasterIntDisableEx(SOC_I2C_0_REGS, I2C_INT_TRANSMIT_READY | I2C_INT_DATA_READY | I2C_INT_NO_ACK | I2C_INT_STOP_CONDITION); /* Generate a STOP */ I2CMasterStop(SOC_I2C_0_REGS); I2CStatusClear(SOC_I2C_0_REGS, I2C_CLEAR_STOP_CONDITION); /* Clear interrupt at AINTC, if we missed any, in case of error */ #ifdef _TMS320C6X IntEventClear(SYS_INT_I2C0_INT); #else IntSystemStatusClear(15); #endif txCompFlag = 0; } if (I2CMasterIntStatus(SOC_I2C_0_REGS) & I2C_ICSTR_NACKSNT) { I2CMasterIntDisableEx(SOC_I2C_0_REGS, I2C_INT_TRANSMIT_READY | I2C_INT_DATA_READY | I2C_INT_NO_ACK | I2C_INT_STOP_CONDITION); /* Generate a STOP */ I2CMasterStop(SOC_I2C_0_REGS); I2CStatusClear(SOC_I2C_0_REGS, (I2C_CLEAR_NO_ACK_SENT | I2C_CLEAR_STOP_CONDITION)); /* Clear interrupt at AINTC, if we missed any, in case of error */ #ifdef _TMS320C6X IntEventClear(SYS_INT_I2C0_INT); #else IntSystemStatusClear(15); #endif txCompFlag = 0; } intCode = I2CInterruptVectorGet(SOC_I2C_0_REGS); } }