int wifi_init(void){ uint32_t BUF_SIZE = MD_BUF_SIZE; uint8_t tmp; //dummy var for flushing UART int r; //return value from wifi_send_cmd (length of resp) char *buf; char *tx_buf; //allocate static buffers if they are not NULL if(resp_buf==NULL){ resp_buf=core_malloc(RESP_BUF_SIZE); } if(resp_complete_buf==NULL){ resp_complete_buf=core_malloc(RESP_COMPLETE_BUF_SIZE); } if(wifi_rx_buf==NULL){ wifi_rx_buf = core_malloc(WIFI_RX_BUF_SIZE); } //if we are standalone, don't do anything if(wemo_config.standalone){ printf("warning: wifi_init called in standalone mode\n"); return 0; } //initialize the memory buf = core_malloc(BUF_SIZE); tx_buf = core_malloc(BUF_SIZE); //set up the UART static usart_serial_options_t usart_options = { .baudrate = WIFI_UART_BAUDRATE, .charlength = WIFI_UART_CHAR_LENGTH, .paritytype = WIFI_UART_PARITY, .stopbits = WIFI_UART_STOP_BITS }; gpio_configure_pin(PIO_PA9_IDX, (PIO_PERIPH_A | PIO_DEFAULT)); gpio_configure_pin(PIO_PA10_IDX, (PIO_PERIPH_A | PIO_DEFAULT)); pmc_enable_periph_clk(ID_WIFI_UART); sysclk_enable_peripheral_clock(ID_WIFI_UART); usart_serial_init(WIFI_UART,&usart_options); //flush any existing data while(usart_serial_is_rx_ready(WIFI_UART)){ usart_serial_getchar(WIFI_UART,&tmp); } // Trigger from timer 0 pmc_enable_periph_clk(ID_TC0); tc_init(TC0, 0, // channel 0 TC_CMR_TCCLKS_TIMER_CLOCK5 // source clock (CLOCK5 = Slow Clock) | TC_CMR_CPCTRG // up mode with automatic reset on RC match | TC_CMR_WAVE // waveform mode | TC_CMR_ACPA_CLEAR // RA compare effect: clear | TC_CMR_ACPC_SET // RC compare effect: set ); TC0->TC_CHANNEL[0].TC_RA = 0; // doesn't matter TC0->TC_CHANNEL[0].TC_RC = 64000; // sets frequency: 32kHz/32000 = 1 Hz NVIC_ClearPendingIRQ(TC0_IRQn); NVIC_SetPriority(TC0_IRQn,1);//high priority NVIC_EnableIRQ(TC0_IRQn); tc_enable_interrupt(TC0, 0, TC_IER_CPCS); //reset the module if(wifi_send_cmd("AT+RST","ready",buf,BUF_SIZE,8)==0){ printf("Error reseting ESP8266\n"); //free memory core_free(buf); core_free(tx_buf); return -1; } //set to mode STA if(wifi_send_cmd("AT+CWMODE=1","OK",buf,BUF_SIZE,8)==0){ printf("Error setting ESP8266 mode\n"); core_free(buf); core_free(tx_buf); return 0; } //try to join the specified network snprintf(tx_buf,BUF_SIZE,"AT+CWJAP=\"%s\",\"%s\"", wemo_config.wifi_ssid,wemo_config.wifi_pwd); if((r=wifi_send_cmd(tx_buf,"OK",buf,BUF_SIZE,10))==0){ printf("no response to CWJAP\n"); //free memory core_free(buf); core_free(tx_buf); return -1; } //check for errors if( (r<1) || (strcmp(&buf[r-1],"OK")!=0)){ snprintf(tx_buf,BUF_SIZE,"failed to join network [%s]: [%s]\n",wemo_config.wifi_ssid, buf); printf(tx_buf); core_log(tx_buf); //free memory core_free(buf); core_free(tx_buf); return -1; } //see if we have an IP address wifi_send_cmd("AT+CIFSR","OK",buf,BUF_SIZE,5); if(strstr(buf,"ERROR")==buf){ printf("error getting IP address\n"); //free the memory core_free(tx_buf); core_free(buf); return -1; } //try to parse the response into an IP address //expect 4 octets but *not* 0.0.0.0 int a1,a2,a3,a4; if(!(sscanf(buf,"+CIFSR:STAIP,\"%d.%d.%d.%d\"",&a1,&a2,&a3,&a4)==4 && a1!=0)){ printf("error, bad address: %s\n",buf); //free the memory core_free(tx_buf); core_free(buf); return -1; } //save the IP to our config snprintf(buf,BUF_SIZE,"%d.%d.%d.%d",a1,a2,a3,a4); memset(wemo_config.ip_addr,0x0,MAX_CONFIG_LEN); strcpy(wemo_config.ip_addr,buf); //set the mode to multiple connection wifi_send_cmd("AT+CIPMUX=1","OK",buf,BUF_SIZE,2); //start a server on port 1336 wifi_send_cmd("AT+CIPSERVER=1,1336","OK",buf,BUF_SIZE,2); //if we know the NILM IP address, send it our IP if(strlen(wemo_config.nilm_ip_addr)!=0){ if(wifi_send_ip()==TX_ERR_MODULE_RESET){ return TX_ERR_MODULE_RESET; } } else { //get the NILM IP address from the manager //once we know the NILM address we send it ours core_get_nilm_ip_addr(); } //log the event snprintf(buf,BUF_SIZE,"Joined [%s] with IP [%s]", wemo_config.wifi_ssid,wemo_config.ip_addr); printf("\n%s\n",buf); core_log(buf); //free the memory core_free(tx_buf); core_free(buf); return 0; }
static void ser_phy_init_pendSV(void) { NVIC_SetPriority(SW_IRQn, APP_IRQ_PRIORITY_MID); NVIC_EnableIRQ(SW_IRQn); }
int gpio_init_int(gpio_t dev, gpio_pp_t pullup, gpio_flank_t flank, gpio_cb_t cb, void *arg) { int res; uint8_t pin; if (dev >= GPIO_NUMOF) { return -1; } pin = gpio_pin_map[dev]; /* configure pin as input */ res = gpio_init_in(dev, pullup); if (res < 0) { return res; } /* set interrupt priority (its the same for all EXTI interrupts) */ NVIC_SetPriority(EXTI0_1_IRQn, GPIO_IRQ_PRIO); NVIC_SetPriority(EXTI2_3_IRQn, GPIO_IRQ_PRIO); NVIC_SetPriority(EXTI4_15_IRQn, GPIO_IRQ_PRIO); /* enable clock of the SYSCFG module for EXTI configuration */ RCC->APB2ENR |= RCC_APB2ENR_SYSCFGCOMPEN; /* read pin number, set EXIT channel and enable global interrupt for EXTI channel */ switch (dev) { #ifdef GPIO_0_EN case GPIO_0: GPIO_0_EXTI_CFG(); break; #endif #ifdef GPIO_1_EN case GPIO_1: GPIO_1_EXTI_CFG(); break; #endif #ifdef GPIO_2_EN case GPIO_2: GPIO_2_EXTI_CFG(); break; #endif #ifdef GPIO_3_EN case GPIO_3: GPIO_3_EXTI_CFG(); break; #endif #ifdef GPIO_4_EN case GPIO_4: GPIO_4_EXTI_CFG(); break; #endif #ifdef GPIO_5_EN case GPIO_5: GPIO_5_EXTI_CFG(); break; #endif #ifdef GPIO_6_EN case GPIO_6: GPIO_6_EXTI_CFG(); break; #endif #ifdef GPIO_7_EN case GPIO_7: GPIO_7_EXTI_CFG(); break; #endif #ifdef GPIO_8_EN case GPIO_8: GPIO_8_EXTI_CFG(); break; #endif #ifdef GPIO_9_EN case GPIO_9: GPIO_9_EXTI_CFG(); break; #endif #ifdef GPIO_10_EN case GPIO_10: GPIO_10_EXTI_CFG(); break; #endif #ifdef GPIO_11_EN case GPIO_11: GPIO_11_EXTI_CFG(); break; #endif } NVIC_EnableIRQ(gpio_irq_map[dev]); /* set callback */ gpio_config[dev].cb = cb; gpio_config[dev].arg = arg; /* configure the event that triggers an interrupt */ switch (flank) { case GPIO_RISING: EXTI->RTSR |= (1 << pin); EXTI->FTSR &= ~(1 << pin); break; case GPIO_FALLING: EXTI->RTSR &= ~(1 << pin); EXTI->FTSR |= (1 << pin); break; case GPIO_BOTH: EXTI->RTSR |= (1 << pin); EXTI->FTSR |= (1 << pin); break; } /* clear any pending requests */ EXTI->PR = (1 << pin); /* unmask the pins interrupt channel */ EXTI->IMR |= (1 << pin); return 0; }
void vuIP_Task( void *pvParameters ) { portBASE_TYPE i; uip_ipaddr_t xIPAddr; struct timer periodic_timer, arp_timer; extern void ( vEMAC_ISR_Wrapper )( void ); vtWebServerStruct *param = (vtWebServerStruct *)pvParameters; roverStatusDev = param->roverStatusDev; lcdDev = param->lcdDev; mapDev = param->mapDev; /* Initialise the uIP stack. */ timer_set( &periodic_timer, configTICK_RATE_HZ / 2 ); timer_set( &arp_timer, configTICK_RATE_HZ * 10 ); uip_init(); uip_ipaddr( xIPAddr, configIP_ADDR0, configIP_ADDR1, configIP_ADDR2, configIP_ADDR3 ); uip_sethostaddr( xIPAddr ); uip_ipaddr( xIPAddr, configNET_MASK0, configNET_MASK1, configNET_MASK2, configNET_MASK3 ); uip_setnetmask( xIPAddr ); httpd_init(); /* Create the semaphore used to wake the uIP task. */ vSemaphoreCreateBinary( xEMACSemaphore ); /* Initialise the MAC. */ while( lEMACInit() != pdPASS ) { vTaskDelay( uipINIT_WAIT ); } portENTER_CRITICAL(); { EMAC->IntEnable = ( INT_RX_DONE | INT_TX_DONE ); /* Set the interrupt priority to the max permissible to cause some interrupt nesting. */ NVIC_SetPriority( ENET_IRQn, configEMAC_INTERRUPT_PRIORITY ); /* Enable the interrupt. */ NVIC_EnableIRQ( ENET_IRQn ); prvSetMACAddress(); } portEXIT_CRITICAL(); for( ;; ) { /* Is there received data ready to be processed? */ uip_len = ulGetEMACRxData(); if( ( uip_len > 0 ) && ( uip_buf != NULL ) ) { /* Standard uIP loop taken from the uIP manual. */ if( xHeader->type == htons( UIP_ETHTYPE_IP ) ) { uip_arp_ipin(); uip_input(); /* If the above function invocation resulted in data that should be sent out on the network, the global variable uip_len is set to a value > 0. */ if( uip_len > 0 ) { uip_arp_out(); vSendEMACTxData( uip_len ); } } else if( xHeader->type == htons( UIP_ETHTYPE_ARP ) ) { uip_arp_arpin(); /* If the above function invocation resulted in data that should be sent out on the network, the global variable uip_len is set to a value > 0. */ if( uip_len > 0 ) { vSendEMACTxData( uip_len ); } } } else { if( timer_expired( &periodic_timer ) && ( uip_buf != NULL ) ) { timer_reset( &periodic_timer ); for( i = 0; i < UIP_CONNS; i++ ) { uip_periodic( i ); /* If the above function invocation resulted in data that should be sent out on the network, the global variable uip_len is set to a value > 0. */ if( uip_len > 0 ) { uip_arp_out(); vSendEMACTxData( uip_len ); } } /* Call the ARP timer function every 10 seconds. */ if( timer_expired( &arp_timer ) ) { timer_reset( &arp_timer ); uip_arp_timer(); } } else { /* We did not receive a packet, and there was no periodic processing to perform. Block for a fixed period. If a packet is received during this period we will be woken by the ISR giving us the Semaphore. */ xSemaphoreTake( xEMACSemaphore, configTICK_RATE_HZ / 2 ); } } } }
/** * User EMAC initialization */ void Usr_Init_Emac(void) { /* EMAC configuration type */ EMAC_CFG_Type Emac_Config; /* pin configuration */ PINSEL_CFG_Type PinCfg; uint32_t i; /* * Enable P1 Ethernet Pins: * P1.0 - ENET_TXD0 * P1.1 - ENET_TXD1 * P1.4 - ENET_TX_EN * P1.8 - ENET_CRS * P1.9 - ENET_RXD0 * P1.10 - ENET_RXD1 * P1.14 - ENET_RX_ER * P1.15 - ENET_REF_CLK * P1.16 - ENET_MDC * P1.17 - ENET_MDIO */ PinCfg.Funcnum = 1; PinCfg.OpenDrain = 0; PinCfg.Pinmode = 0; PinCfg.Portnum = 1; PinCfg.Pinnum = 0; PINSEL_ConfigPin(&PinCfg); PinCfg.Pinnum = 1; PINSEL_ConfigPin(&PinCfg); PinCfg.Pinnum = 4; PINSEL_ConfigPin(&PinCfg); PinCfg.Pinnum = 8; PINSEL_ConfigPin(&PinCfg); PinCfg.Pinnum = 9; PINSEL_ConfigPin(&PinCfg); PinCfg.Pinnum = 10; PINSEL_ConfigPin(&PinCfg); PinCfg.Pinnum = 14; PINSEL_ConfigPin(&PinCfg); PinCfg.Pinnum = 15; PINSEL_ConfigPin(&PinCfg); PinCfg.Pinnum = 16; PINSEL_ConfigPin(&PinCfg); PinCfg.Pinnum = 17; PINSEL_ConfigPin(&PinCfg); _DBG_("Init EMAC module"); sprintf(db_,"MAC[1..6] addr: %X-%X-%X-%X-%X-%X \n\r", \ EMACAddr[0], EMACAddr[1], EMACAddr[2], \ EMACAddr[3], EMACAddr[4], EMACAddr[5]); DB; Emac_Config.Mode = EMAC_MODE_AUTO; Emac_Config.pbEMAC_Addr = EMACAddr; // Initialize EMAC module with given parameter while (EMAC_Init(&Emac_Config) == ERROR){ // Delay for a while then continue initializing EMAC module _DBG_("Error during initializing EMAC, restart after a while"); for (i = 0x100000; i; i--); } _DBG_("Setup callback functions"); // Setup callback functions EMAC_SetupIntCBS(EMAC_INT_RX_OVERRUN, RxOverrun_UsrCBS); EMAC_SetupIntCBS(EMAC_INT_RX_ERR, RxError_UsrCBS); EMAC_SetupIntCBS(EMAC_INT_RX_FIN, RxFinish_UsrCBS); EMAC_SetupIntCBS(EMAC_INT_RX_DONE, RxDone_UsrCBS); EMAC_SetupIntCBS(EMAC_INT_TX_UNDERRUN, TxUnderrun_UsrCBS); EMAC_SetupIntCBS(EMAC_INT_TX_ERR, TxError_UsrCBS); EMAC_SetupIntCBS(EMAC_INT_TX_FIN, TxFinish_UsrCBS); EMAC_SetupIntCBS(EMAC_INT_TX_DONE, TxDone_UsrCBS); #if ENABLE_WOL EMAC_SetupIntCBS(EMAC_INT_WAKEUP, WoL_UsrCBS); #endif // Enable all interrupt EMAC_IntCmd((EMAC_INT_RX_OVERRUN | EMAC_INT_RX_ERR | EMAC_INT_RX_FIN \ | EMAC_INT_RX_DONE | EMAC_INT_TX_UNDERRUN | EMAC_INT_TX_ERR \ | EMAC_INT_TX_FIN | EMAC_INT_TX_DONE), ENABLE); NVIC_SetPriority(ENET_IRQn, 0); NVIC_EnableIRQ(ENET_IRQn); _DBG_("Initialize EMAC complete"); }
void NVIC_set_all_irq_priorities(int priority) { int irqnum; for(irqnum = first_IRQ_number ; irqnum < last_IRQ_number + 1 ; irqnum++) NVIC_SetPriority((IRQn_Type)irqnum, priority); }
void platform_init_peripheral_irq_priorities( void ) { /* Interrupt priority setup. Called by WICED/platform/MCU/STM32F2xx/platform_init.c */ NVIC_SetPriority( RTC_WKUP_IRQn , 1 ); /* RTC Wake-up event */ NVIC_SetPriority( SDIO_IRQn , 2 ); /* WLAN SDIO */ NVIC_SetPriority( DMA2_Stream3_IRQn, 3 ); /* WLAN SDIO DMA */ //NVIC_SetPriority( DMA1_Stream3_IRQn, 3 ); /* WLAN SPI DMA */ NVIC_SetPriority( USART1_IRQn , 6 ); /* MICO_UART_1 */ NVIC_SetPriority( USART2_IRQn , 6 ); /* MICO_UART_2 */ NVIC_SetPriority( DMA1_Stream6_IRQn, 7 ); /* MICO_UART_1 TX DMA */ NVIC_SetPriority( DMA1_Stream5_IRQn, 7 ); /* MICO_UART_1 RX DMA */ NVIC_SetPriority( DMA2_Stream7_IRQn, 7 ); /* MICO_UART_2 TX DMA */ NVIC_SetPriority( DMA2_Stream2_IRQn, 7 ); /* MICO_UART_2 RX DMA */ NVIC_SetPriority( EXTI0_IRQn , 14 ); /* GPIO */ NVIC_SetPriority( EXTI1_IRQn , 14 ); /* GPIO */ NVIC_SetPriority( EXTI2_IRQn , 14 ); /* GPIO */ NVIC_SetPriority( EXTI3_IRQn , 14 ); /* GPIO */ NVIC_SetPriority( EXTI4_IRQn , 14 ); /* GPIO */ NVIC_SetPriority( EXTI9_5_IRQn , 14 ); /* GPIO */ NVIC_SetPriority( EXTI15_10_IRQn , 14 ); /* GPIO */ }
int gpio_init_int(gpio_t dev, gpio_pp_t pullup, gpio_flank_t flank, void (*cb)(void)) { int res; uint32_t pin; /* configure pin as input */ res = gpio_init_in(dev, pullup); if (res < 0) { return res; } /* set interrupt priority (its the same for all EXTI interrupts) */ NVIC_SetPriority(EXTI0_1_IRQn, GPIO_IRQ_PRIO); NVIC_SetPriority(EXTI2_3_IRQn, GPIO_IRQ_PRIO); NVIC_SetPriority(EXTI4_15_IRQn, GPIO_IRQ_PRIO); /* enable clock of the SYSCFG module for EXTI configuration */ RCC->APB2ENR |= RCC_APB2ENR_SYSCFGCOMPEN; /* read pin number, set EXIT channel and enable global interrupt for EXTI channel */ switch (dev) { #ifdef GPIO_0_EN case GPIO_0: pin = GPIO_0_PIN; GPIO_0_EXTI_CFG(); NVIC_SetPriority(GPIO_0_IRQ, GPIO_IRQ_PRIO); NVIC_EnableIRQ(GPIO_0_IRQ); break; #endif #ifdef GPIO_1_EN case GPIO_1: pin = GPIO_1_PIN; GPIO_1_EXTI_CFG(); NVIC_SetPriority(GPIO_1_IRQ, GPIO_IRQ_PRIO); NVIC_EnableIRQ(GPIO_1_IRQ); break; #endif #ifdef GPIO_2_EN case GPIO_2: pin = GPIO_2_PIN; GPIO_2_EXTI_CFG(); NVIC_SetPriority(GPIO_2_IRQ, GPIO_IRQ_PRIO); NVIC_EnableIRQ(GPIO_2_IRQ); break; #endif #ifdef GPIO_3_EN case GPIO_3: pin = GPIO_3_PIN; GPIO_3_EXTI_CFG(); NVIC_SetPriority(GPIO_3_IRQ, GPIO_IRQ_PRIO); NVIC_EnableIRQ(GPIO_3_IRQ); break; #endif #ifdef GPIO_4_EN case GPIO_4: pin = GPIO_4_PIN; GPIO_4_EXTI_CFG(); NVIC_SetPriority(GPIO_4_IRQ, GPIO_IRQ_PRIO); NVIC_EnableIRQ(GPIO_4_IRQ); break; #endif #ifdef GPIO_5_EN case GPIO_5: pin = GPIO_5_PIN; GPIO_5_EXTI_CFG(); NVIC_SetPriority(GPIO_5_IRQ, GPIO_IRQ_PRIO); NVIC_EnableIRQ(GPIO_5_IRQ); break; #endif #ifdef GPIO_6_EN case GPIO_6: pin = GPIO_6_PIN; GPIO_6_EXTI_CFG(); NVIC_SetPriority(GPIO_6_IRQ, GPIO_IRQ_PRIO); NVIC_EnableIRQ(GPIO_6_IRQ); break; #endif #ifdef GPIO_7_EN case GPIO_7: pin = GPIO_7_PIN; GPIO_7_EXTI_CFG(); NVIC_SetPriority(GPIO_7_IRQ, GPIO_IRQ_PRIO); NVIC_EnableIRQ(GPIO_7_IRQ); break; #endif #ifdef GPIO_8_EN case GPIO_8: pin = GPIO_8_PIN; GPIO_8_EXTI_CFG(); NVIC_SetPriority(GPIO_8_IRQ, GPIO_IRQ_PRIO); NVIC_EnableIRQ(GPIO_8_IRQ); break; #endif #ifdef GPIO_9_EN case GPIO_9: pin = GPIO_9_PIN; GPIO_9_EXTI_CFG(); NVIC_SetPriority(GPIO_9_IRQ, GPIO_IRQ_PRIO); NVIC_EnableIRQ(GPIO_9_IRQ); break; #endif #ifdef GPIO_10_EN case GPIO_10: pin = GPIO_10_PIN; GPIO_10_EXTI_CFG(); NVIC_SetPriority(GPIO_10_IRQ, GPIO_IRQ_PRIO); NVIC_EnableIRQ(GPIO_10_IRQ); break; #endif #ifdef GPIO_11_EN case GPIO_11: pin = GPIO_11_PIN; GPIO_11_EXTI_CFG(); NVIC_SetPriority(GPIO_11_IRQ, GPIO_IRQ_PRIO); NVIC_EnableIRQ(GPIO_11_IRQ); break; #endif case GPIO_UNDEFINED: default: return -1; } /* set callback */ config[dev].cb = cb; /* configure the event that triggers an interrupt */ switch (flank) { case GPIO_RISING: EXTI->RTSR |= (1 << pin); EXTI->FTSR &= ~(1 << pin); break; case GPIO_FALLING: EXTI->RTSR &= ~(1 << pin); EXTI->FTSR |= (1 << pin); break; case GPIO_BOTH: EXTI->RTSR |= (1 << pin); EXTI->FTSR |= (1 << pin); break; } /* unmask the pins interrupt channel */ EXTI->IMR |= (1 << pin); return 0; }
/** * @brief Initializes the Low Level portion of the Device driver. * @param pdev: Device handle * @retval USBD Status */ USBD_StatusTypeDef USBD_LL_Init (USBD_HandleTypeDef *pdev) { /* Change Systick prioity */ NVIC_SetPriority (SysTick_IRQn, 0); #ifdef USE_USB_FS /*Set LL Driver parameters */ hpcd.Instance = USB_OTG_FS; hpcd.Init.dev_endpoints = 4; hpcd.Init.use_dedicated_ep1 = 0; hpcd.Init.ep0_mps = 0x40; hpcd.Init.dma_enable = 0; hpcd.Init.low_power_enable = 0; hpcd.Init.phy_itface = PCD_PHY_EMBEDDED; hpcd.Init.Sof_enable = 0; hpcd.Init.speed = PCD_SPEED_FULL; hpcd.Init.vbus_sensing_enable = 1; /* Link The driver to the stack */ hpcd.pData = pdev; pdev->pData = &hpcd; /*Initialize LL Driver */ HAL_PCD_Init(&hpcd); HAL_PCDEx_SetRxFiFo(&hpcd, 0x80); HAL_PCDEx_SetTxFiFo(&hpcd, 0, 0x40); HAL_PCDEx_SetTxFiFo(&hpcd, 1, 0x80); #endif #ifdef USE_USB_HS /*Set LL Driver parameters */ hpcd.Instance = USB_OTG_HS; hpcd.Init.dev_endpoints = 6; hpcd.Init.use_dedicated_ep1 = 0; hpcd.Init.ep0_mps = 0x40; /* Be aware that enabling USB-DMA mode will result in data being sent only by multiple of 4 packet sizes. This is due to the fact that USB-DMA does not allow sending data from non word-aligned addresses. For this specific application, it is advised to not enable this option unless required. */ hpcd.Init.dma_enable = 0; hpcd.Init.low_power_enable = 0; hpcd.Init.phy_itface = PCD_PHY_ULPI; hpcd.Init.Sof_enable = 0; hpcd.Init.speed = PCD_SPEED_HIGH; hpcd.Init.vbus_sensing_enable = 1; /* Link The driver to the stack */ hpcd.pData = pdev; pdev->pData = &hpcd; /*Initialize LL Driver */ HAL_PCD_Init(&hpcd); HAL_PCDEx_SetRxFiFo(&hpcd, 0x200); HAL_PCDEx_SetTxFiFo(&hpcd, 0, 0x80); HAL_PCDEx_SetTxFiFo(&hpcd, 1, 0x174); #endif return USBD_OK; }
void uart3Init(uint32_t baudrate) { GPIO_InitTypeDef GPIO_InitStructure; RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1,ENABLE); // /* Configure USART1 TX (PA.09) as alternate function push-pull */ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; GPIO_Init(GPIOC, &GPIO_InitStructure); /* Configure USART1 RX (PA.10) as input floating */ GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; GPIO_Init(GPIOC, &GPIO_InitStructure); USART_DeInit(USART3); USART_InitTypeDef USART_InitStructure; /* Enable AFIO, clocks */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); /* Enable GPIO clocks */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC|RCC_APB2Periph_GPIOA |RCC_APB2Periph_GPIOB, ENABLE); /* Enable USART3, clocks */ RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); GPIO_PinRemapConfig(GPIO_PartialRemap_USART3,ENABLE); USART_InitStructure.USART_BaudRate = baudrate; USART_InitStructure.USART_WordLength = USART_WordLength_8b; USART_InitStructure.USART_StopBits = USART_StopBits_1; USART_InitStructure.USART_Parity = USART_Parity_No; USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; /* Configure USART3 */ USART_Init(USART3, &USART_InitStructure); USART_ClearFlag(USART3, USART_FLAG_CTS | USART_FLAG_LBD | USART_FLAG_TC | USART_FLAG_RXNE ); uartRxDMAConfiguration(USART3, USART3_RX_DMA, u1Fifo.rxBuf, UARTRX_FIFO_SIZE); USART_DMACmd(USART3, USART_DMAReq_Tx, ENABLE); /* Enable USART_Rx DMA Receive request */ USART_DMACmd(USART3, USART_DMAReq_Rx, ENABLE); /* Enable USART_Rx Receive interrupt */ //USART_ITConfig(USART3, USART_IT_RXNE, ENABLE); /* Configure USART3 interrupt */ NVIC_SetPriority(USART3_RX_DMA_IRQn, 0x7); NVIC_EnableIRQ(USART3_RX_DMA_IRQn); /* Enable the USART3 */ USART_Cmd(USART3, ENABLE); }
/** * In this function, the hardware should be initialized. * Called from ethernetif_init(). * * @param netif the already initialized lwip network interface structure * for this ethernetif */ static void low_level_init(struct netif *netif) { StatusType result; int data; /* set MAC hardware address length */ netif->hwaddr_len = ETHARP_HWADDR_LEN; /* set MAC hardware address */ netif->hwaddr[0] = MAC_ADDR0; netif->hwaddr[1] = MAC_ADDR1; netif->hwaddr[2] = MAC_ADDR2; netif->hwaddr[3] = MAC_ADDR3; netif->hwaddr[4] = MAC_ADDR4; netif->hwaddr[5] = MAC_ADDR5; /* maximum transfer unit */ netif->mtu = ENET_MAX_PKT_SIZE - 20; /* device capabilities */ /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */ netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP; /* enable the ENET clock */ SIM_SCGC2 |= SIM_SCGC2_ENET_MASK; /* allow concurrent access to MPU controller. Example: ENET uDMA to SRAM, otherwise bus error */ MPU_CESR = 0; init_enet_bufs(); /* create semaphores */ sem_rx = CoCreateSem(NUM_ENET_TX_BUFS, NUM_ENET_TX_BUFS, 1); sem_tx = CoCreateSem(0, NUM_ENET_RX_BUFS, 1); /* Set the Reset bit and clear the Enable bit */ ENET_ECR = ENET_ECR_RESET_MASK; /* Wait at least 8 clock cycles */ for (data = 0; data < 10; data++) { asm("NOP"); } /* start MII interface */ mii_init(50/*BUS_CLOCK*/); // enet tx interrupt NVIC_SetPriority(ENET_Transmit_IRQn, 6); NVIC_EnableIRQ(ENET_Transmit_IRQn); // enet rx interrupt NVIC_SetPriority(ENET_Receive_IRQn, 6); NVIC_EnableIRQ(ENET_Receive_IRQn); //enet error interrupt NVIC_SetPriority(ENET_Error_IRQn, 6); NVIC_EnableIRQ(ENET_Error_IRQn); /* Make sure the external interface signals are enabled */ PORTB_PCR0 = PORT_PCR_MUX(4); //RMII0_MDIO/MII0_MDIO PORTB_PCR1 = PORT_PCR_MUX(4); //RMII0_MDC/MII0_MDC #if USE_MII_MODE PORTA_PCR14 = PORT_PCR_MUX(4); //RMII0_CRS_DV/MII0_RXDV //PORTA_PCR5 = PORT_PCR_MUX(4); //RMII0_RXER/MII0_RXER PORTA_PCR12 = PORT_PCR_MUX(4); //RMII0_RXD1/MII0_RXD1 PORTA_PCR13 = PORT_PCR_MUX(4); //RMII0_RXD0/MII0_RXD0 PORTA_PCR15 = PORT_PCR_MUX(4); //RMII0_TXEN/MII0_TXEN PORTA_PCR16 = PORT_PCR_MUX(4); //RMII0_TXD0/MII0_TXD0 PORTA_PCR17 = PORT_PCR_MUX(4); //RMII0_TXD1/MII0_TXD1 PORTA_PCR11 = PORT_PCR_MUX(4); //MII0_RXCLK PORTA_PCR25 = PORT_PCR_MUX(4); //MII0_TXCLK PORTA_PCR9 = PORT_PCR_MUX(4); //MII0_RXD3 PORTA_PCR10 = PORT_PCR_MUX(4); //MII0_RXD2 PORTA_PCR28 = PORT_PCR_MUX(4); //MII0_TXER PORTA_PCR24 = PORT_PCR_MUX(4); //MII0_TXD2 PORTA_PCR26 = PORT_PCR_MUX(4); //MII0_TXD3 PORTA_PCR27 = PORT_PCR_MUX(4); //MII0_CRS PORTA_PCR29 = PORT_PCR_MUX(4); //MII0_COL #else PORTA_PCR14 = PORT_PCR_MUX(4); //RMII0_CRS_DV/MII0_RXDV // PORTA_PCR5 = PORT_PCR_MUX(4); //RMII0_RXER/MII0_RXER PORTA_PCR12 = PORT_PCR_MUX(4); //RMII0_RXD1/MII0_RXD1 PORTA_PCR13 = PORT_PCR_MUX(4); //RMII0_RXD0/MII0_RXD0 PORTA_PCR15 = PORT_PCR_MUX(4); //RMII0_TXEN/MII0_TXEN PORTA_PCR16 = PORT_PCR_MUX(4); //RMII0_TXD0/MII0_TXD0 PORTA_PCR17 = PORT_PCR_MUX(4); //RMII0_TXD1/MII0_TXD1 #endif /* USE_MII_MODE */ /* Can we talk to the PHY? */ do { CoTickDelay(PHY_LINK_DELAY); data = 0xffff; mii_read(PHY_ADDR, MII_PHYID1, (uint16_t*)&data); } while (data == 0xffff); /* Start auto negotiate. */ mii_write(PHY_ADDR, MII_BMCR, (MII_BMCR_ANRESTART | MII_BMCR_ANENABLE)); /* Wait for auto negotiate to complete. */ do { CoTickDelay(PHY_LINK_DELAY); mii_read(PHY_ADDR, MII_BMSR, (uint16_t*)&data); } while (!(data & MII_BMSR_ANEGCOMPLETE)); /* When we get here we have a link - find out what has been negotiated. */ data = 0; mii_read(PHY_ADDR, PHY_STATUS, (uint16_t*)&data); /* Set the Physical Address for the selected ENET */ ENET_PALR = (uint32_t)((netif->hwaddr[0] << 24) | (netif->hwaddr[1] << 16) | (netif->hwaddr[2] << 8) | netif->hwaddr[3]); ENET_PAUR = (uint32_t)((netif->hwaddr[4] << 24) | (netif->hwaddr[5] << 16)); /* Clear the Individual and Group Address Hash registers */ ENET_IALR = 0; ENET_IAUR = 0; ENET_GALR = 0; ENET_GAUR = 0; #if USE_MII_MODE /* various mode/status setup */ ENET_RCR = ENET_RCR_MAX_FL(ENET_MAX_PKT_SIZE) | ENET_RCR_MII_MODE_MASK | ENET_RCR_CRCFWD_MASK; #else ENET_RCR = ENET_RCR_MAX_FL(ENET_MAX_PKT_SIZE) | ENET_RCR_MII_MODE_MASK | ENET_RCR_CRCFWD_MASK | ENET_RCR_RMII_MODE_MASK; #endif /* clear rx/tx control registers */ ENET_TCR = 0; /* setup half or full duplex */ if (data & PHY_DUPLEX_STATUS) { /* full duplex */ ENET_RCR &= ~ENET_RCR_DRT_MASK; ENET_TCR |= ENET_TCR_FDEN_MASK; } else { /* half duplex */ ENET_RCR |= ENET_RCR_DRT_MASK; ENET_TCR &= ~ENET_TCR_FDEN_MASK; } /* Setup speed */ if (data & PHY_SPEED_STATUS) { /* 10Mbps */ ENET_RCR |= ENET_RCR_RMII_10T_MASK; } #if USE_PROMISCUOUS_MODE ENET_RCR |= ENET_RCR_PROM_MASK; #endif #ifdef ENHANCED_BD ENET_ECR = ENET_ECR_EN1588_MASK; #else ENET_ECR = 0; #endif #if ENET_HARDWARE_CHECKSUM /* enable discard on wrong protocol checksum and other nice features */ ENET_RACC = ENET_RACC_IPDIS_MASK | ENET_RACC_PRODIS_MASK | ENET_RACC_LINEDIS_MASK | ENET_RACC_IPDIS_MASK | ENET_RACC_PADREM_MASK; /* enable protocol checksum insertion */ ENET_TACC = ENET_TACC_IPCHK_MASK | ENET_TACC_PROCHK_MASK; #endif ENET_TFWR = ENET_TFWR_STRFWD_MASK; #if ENET_HARDWARE_SHIFT /* enable ethernet header alignment for rx */ ENET_RACC |= ENET_RACC_SHIFT16_MASK; /* enable ethernet header alignment for tx */ ENET_TACC |= ENET_TACC_SHIFT16_MASK; #endif /* set rx buffer size */ ENET_MRBR = ENET_RX_BUF_SIZE; /* point to the start of the circular rx buffer descriptor queue */ ENET_RDSR = (uint32_t)rx_bd; /* point to the start of the circular tx buffer descriptor queue */ ENET_TDSR = (uint32_t)tx_bd; /* clear all ENET interrupt events */ ENET_EIR = -1u; /* enable interrupts */ ENET_EIMR = 0 /* rx irqs */ | ENET_EIMR_RXF_MASK /* only for complete frame, not partial buffer descriptor */ /* tx irqs */ | ENET_EIMR_TXF_MASK /* only for complete frame, not partial buffer descriptor */ /* others enet irqs */ | ENET_EIMR_UN_MASK | ENET_EIMR_RL_MASK | ENET_EIMR_LC_MASK | ENET_EIMR_BABT_MASK | ENET_EIMR_BABR_MASK | ENET_EIMR_EBERR_MASK; /* create the task that handles the MAC ENET */ result = CoCreateTask((FUNCPtr)ethernetif_input, (void *)netif, TASK_ETHIF_PRIO, &stack[TASK_ETHIF_STACK_SIZE - 1], TASK_ETHIF_STACK_SIZE); if (result == E_CREATE_FAIL) { LWIP_DEBUGF(NETIF_DEBUG,("Task for ETH recive created failed !\n\r ")); }; /* Enable the MAC itself */ ENET_ECR |= ENET_ECR_ETHEREN_MASK; /* Indicate that there have been empty receive buffers produced */ ENET_RDAR = ENET_RDAR_RDAR_MASK; }
void sync_sep_setup() { quan::stm32::module_enable<video_in_hsync_first_edge_pin::port_type>(); quan::stm32::module_enable<video_in_hsync_second_edge_pin::port_type>(); quan::stm32::apply< video_in_hsync_first_edge_pin, // af for first edge #if (QUAN_OSD_BOARD_TYPE == 4) quan::stm32::gpio::mode::af9, // PB14 TIM12_CH1 #else quan::stm32::gpio::mode::af3, #endif #if (QUAN_OSD_BOARD_TYPE == 1) || (QUAN_OSD_BOARD_TYPE == 3) || (QUAN_OSD_BOARD_TYPE == 4) quan::stm32::gpio::pupd::pull_up #else #if QUAN_OSD_BOARD_TYPE == 2 quan::stm32::gpio::pupd::pull_down #else #error no board defined #endif #endif >(); quan::stm32::apply< video_in_hsync_second_edge_pin, #if (QUAN_OSD_BOARD_TYPE == 4) quan::stm32::gpio::mode::af9, // PB15 TIM12_CH2 #else quan::stm32::gpio::mode::af3, #endif #if (QUAN_OSD_BOARD_TYPE == 1) || (QUAN_OSD_BOARD_TYPE == 3)|| (QUAN_OSD_BOARD_TYPE == 4) quan::stm32::gpio::pupd::pull_up #else #if QUAN_OSD_BOARD_TYPE == 2 quan::stm32::gpio::pupd::pull_down #else #error no board defined #endif #endif >(); quan::stm32::module_enable<sync_sep_timer>(); quan::stm32::module_reset<sync_sep_timer>(); sync_sep_timer::get()->arr = 0xFFFF; // cc1 capture on first edge of hsync // cc2 capture on second edge of hsync quan::stm32::tim::ccmr1_t ccmr1 = 0; ccmr1.cc1s = 0b01;// CC1 is input mapped on TI1 ccmr1.cc2s = 0b01; // CC2 is input mapped on TI2 sync_sep_timer::get()->ccmr1.set(ccmr1.value); quan::stm32::tim::ccer_t ccer = 0; #if (QUAN_OSD_BOARD_TYPE == 1) || (QUAN_OSD_BOARD_TYPE == 3) || (QUAN_OSD_BOARD_TYPE == 4) ccer.cc1p = true; // CC1 is falling edge capture ccer.cc1np = false; ccer.cc2p = false; ccer.cc2np = false; // CC2 is rising edge capture #else #if QUAN_OSD_BOARD_TYPE == 2 ccer.cc1p = false; // CC1 is rising edge capture ccer.cc1np = false; ccer.cc2p = true; ccer.cc2np = false; // CC2 is falling edge capture #else #error no board type specified #endif #endif ccer.cc1e = true; ccer.cc2e = true; sync_sep_timer::get()->ccer.set(ccer.value); #if (QUAN_OSD_BOARD_TYPE !=4) NVIC_SetPriority(TIM1_BRK_TIM9_IRQn,interrupt_priority::video); NVIC_EnableIRQ(TIM1_BRK_TIM9_IRQn); #else NVIC_SetPriority(TIM8_BRK_TIM12_IRQn,interrupt_priority::video); NVIC_EnableIRQ(TIM8_BRK_TIM12_IRQn); #endif }
/*********************************************************************//** * @brief c_entry: Main SPI program body * @param[in] None * @return int **********************************************************************/ int c_entry(void) { uint8_t tmpchar[2] = {0, 0}; PINSEL_CFG_Type PinCfg; __IO FlagStatus exitflag; /* * Initialize SPI pin connect * P0.15 - SCK; * P0.16 - SSEL - used as GPIO * P0.17 - MISO * P0.18 - MOSI */ PinCfg.Funcnum = 3; PinCfg.OpenDrain = 0; PinCfg.Pinmode = 0; PinCfg.Portnum = 0; PinCfg.Pinnum = 15; PINSEL_ConfigPin(&PinCfg); PinCfg.Pinnum = 17; PINSEL_ConfigPin(&PinCfg); PinCfg.Pinnum = 18; PINSEL_ConfigPin(&PinCfg); PinCfg.Pinnum = 16; PinCfg.Funcnum = 0; PINSEL_ConfigPin(&PinCfg); /* Initialize debug via UART0 * – 115200bps * – 8 data bit * – No parity * – 1 stop bit * – No flow control */ debug_frmwrk_init(); // print welcome screen print_menu(); // initialize SPI configuration structure to default SPI_ConfigStructInit(&SPI_ConfigStruct); // Initialize SPI peripheral with parameter given in structure above SPI_Init(LPC_SPI, &SPI_ConfigStruct); // Initialize /CS pin to GPIO function CS_Init(); /* preemption = 1, sub-priority = 1 */ NVIC_SetPriority(SPI_IRQn, ((0x01<<3)|0x01)); /* Enable SSP0 interrupt */ NVIC_EnableIRQ(SPI_IRQn); /* First, send some command to reset SC16IS740 chip via SPI bus interface * note driver /CS pin to low state before transferring by CS_Enable() function */ complete = RESET; CS_Force(0); xferConfig.tx_data = iocon_cfg; xferConfig.rx_data = spireadbuf; xferConfig.length = sizeof (iocon_cfg); SPI_ReadWrite(LPC_SPI, &xferConfig, SPI_TRANSFER_INTERRUPT); while (complete == RESET); CS_Force(1); complete = RESET; CS_Force(0); xferConfig.tx_data = iodir_cfg; xferConfig.rx_data = spireadbuf; xferConfig.length = sizeof (iodir_cfg); SPI_ReadWrite(LPC_SPI, &xferConfig, SPI_TRANSFER_INTERRUPT); while (complete == RESET); CS_Force(1); // Reset exit flag exitflag = RESET; // Start to use SPI polling mode /* Read some data from the buffer */ while (exitflag == RESET) { while((tmpchar[0] = _DG) == 0); if (tmpchar[0] == 27){ /* ESC key, set exit flag */ _DBG_(menu2); exitflag = SET; } else if (tmpchar[0] == 'r'){ print_menu(); } else { if (tmpchar[0] == '1') { // LEDs are ON now... CS_Force(0); xferConfig.tx_data = iostate_on; xferConfig.rx_data = spireadbuf; xferConfig.length = sizeof (iostate_on); SPI_ReadWrite(LPC_SPI, &xferConfig, SPI_TRANSFER_POLLING); CS_Force(1); } else if (tmpchar[0] == '2') { // LEDs are OFF now... CS_Force(0); xferConfig.tx_data = iostate_off; xferConfig.rx_data = spireadbuf; xferConfig.length = sizeof (iostate_off); SPI_ReadWrite(LPC_SPI, &xferConfig, SPI_TRANSFER_POLLING); CS_Force(1); } /* Then Echo it back */ _DBG_(tmpchar); } } // DeInitialize UART0 peripheral SPI_DeInit(LPC_SPI); /* Loop forever */ while(1); return 1; }
int wifi_send_cmd(const char* cmd, const char* resp_complete, char* resp, uint32_t maxlen, int timeout){ resp_buf_idx = 0; uint32_t rx_start, rx_end; //clear out the response buffer memset(resp,0x0,maxlen); memset(resp_buf,0x0,RESP_BUF_SIZE); //setup the rx_complete buffer so we know when the command is finished if(strlen(resp_complete)>RESP_COMPLETE_BUF_SIZE-3){ printf("resp_complete, too long exiting\n"); return -1; } strcpy(resp_complete_buf,resp_complete); strcat(resp_complete_buf,"\r\n"); //enable RX interrupts usart_enable_interrupt(WIFI_UART, US_IER_RXRDY); NVIC_SetPriority(WIFI_UART_IRQ,2); NVIC_EnableIRQ(WIFI_UART_IRQ); //write the command rx_wait=true; //we want this data returned in resp_buf rx_complete =false; //reset the early complete flag usart_serial_write_packet(WIFI_UART,(uint8_t*)cmd,strlen(cmd)); //terminate the command usart_serial_putchar(WIFI_UART,'\r'); usart_serial_putchar(WIFI_UART,'\n'); //wait for [timeout] seconds while(timeout>0){ //start the timer tc_start(TC0, 0); //when timer expires, return what we have in the buffer rx_wait=true; //reset the wait flag while(rx_wait); tc_stop(TC0,0); if(rx_complete) //if the uart interrupt signals rx is complete break; timeout--; } //now null terminate the response resp_buf[resp_buf_idx]=0x0; //remove any ECHO if(strstr((char*)resp_buf,cmd)!=(char*)resp_buf){ printf("bad echo: %s\n",resp_buf); return 0; } rx_start = strlen(cmd); //remove leading whitespace while(resp_buf[rx_start]=='\r'|| resp_buf[rx_start]=='\n') rx_start++; //remove trailing whitespace rx_end = strlen((char*)resp_buf)-1; while(resp_buf[rx_end]=='\r'|| resp_buf[rx_end]=='\n') rx_end--; //make sure we have a response if(rx_end<=rx_start){ printf("no response by timeout\n"); return 0; } //copy the data to the response buffer if((rx_end-rx_start+1)>maxlen){ memcpy(resp,&resp_buf[rx_start],maxlen-1); resp[maxlen-1]=0x0; printf((char*)resp_buf); printf("truncated output!\n"); } else{ memcpy(resp,&resp_buf[rx_start],rx_end-rx_start+1); //null terminate the response buffer resp[rx_end-rx_start+1]=0x0; } return rx_end-rx_start; }
OSStatus platform_uart_init( platform_uart_driver_t* driver, const platform_uart_t* peripheral, const platform_uart_config_t* config, ring_buffer_t* optional_ring_buffer ) { pdc_packet_t pdc_uart_packet, pdc_uart_tx_packet; OSStatus err = kNoErr; sam_usart_opt_t settings; bool hardware_shaking = false; platform_mcu_powersave_disable(); require_action_quiet( ( driver != NULL ) && ( peripheral != NULL ) && ( config != NULL ), exit, err = kParamErr); require_action_quiet( (optional_ring_buffer->buffer != NULL ) && (optional_ring_buffer->size != 0), exit, err = kUnsupportedErr); driver->rx_size = 0; driver->tx_size = 0; driver->rx_ring_buffer = optional_ring_buffer; driver->last_transmit_result = kNoErr; driver->last_receive_result = kNoErr; driver->peripheral = (platform_uart_t*)peripheral; #ifndef NO_MICO_RTOS mico_rtos_init_semaphore( &driver->tx_complete, 1 ); mico_rtos_init_semaphore( &driver->rx_complete, 1 ); mico_rtos_init_semaphore( &driver->sem_wakeup, 1 ); mico_rtos_init_mutex ( &driver->tx_mutex ); #else driver->tx_complete = false; driver->rx_complete = false; #endif /* Set Tx and Rx pin mode to UART peripheral */ platform_gpio_peripheral_pin_init( peripheral->tx_pin, ( peripheral->tx_pin_mux_mode | IOPORT_MODE_PULLUP ) ); platform_gpio_peripheral_pin_init( peripheral->rx_pin, ( peripheral->rx_pin_mux_mode | IOPORT_MODE_PULLUP ) ); /* Init CTS and RTS pins (if available) */ if ( peripheral->cts_pin != NULL && (config->flow_control == FLOW_CONTROL_CTS || config->flow_control == FLOW_CONTROL_CTS_RTS) ) { hardware_shaking = true; platform_gpio_peripheral_pin_init( peripheral->cts_pin, ( peripheral->cts_pin_mux_mode | IOPORT_MODE_PULLUP ) ); } if ( peripheral->rts_pin != NULL && (config->flow_control == FLOW_CONTROL_CTS || config->flow_control == FLOW_CONTROL_CTS_RTS) ) { hardware_shaking = true; platform_gpio_peripheral_pin_init( peripheral->rts_pin, ( peripheral->rts_pin_mux_mode | IOPORT_MODE_PULLUP ) ); } /* Enable the clock. */ if( pmc_is_periph_clk_enabled( peripheral->peripheral_id ) == 0 ) { flexcom_enable( peripheral->flexcom_base ); } flexcom_set_opmode( peripheral->flexcom_base, FLEXCOM_USART ); /* Enable the receiver and transmitter. */ usart_reset_tx( peripheral->port ); usart_reset_rx( peripheral->port ); /* Disable all the interrupts. */ usart_disable_interrupt( peripheral->port, 0xffffffff ); switch ( config->parity ) { case NO_PARITY: settings.parity_type = US_MR_PAR_NO; break; case EVEN_PARITY: settings.parity_type = US_MR_PAR_EVEN; break; case ODD_PARITY: settings.parity_type = US_MR_PAR_ODD; break; default: err = kParamErr; goto exit; } switch ( config->data_width) { case DATA_WIDTH_5BIT: settings.char_length = US_MR_CHRL_5_BIT; break; case DATA_WIDTH_6BIT: settings.char_length = US_MR_CHRL_6_BIT; break; case DATA_WIDTH_7BIT: settings.char_length = US_MR_CHRL_7_BIT; break; case DATA_WIDTH_8BIT: settings.char_length = US_MR_CHRL_8_BIT; break; case DATA_WIDTH_9BIT: settings.char_length = US_MR_MODE9; break; default: err = kParamErr; goto exit; } settings.baudrate = config->baud_rate; settings.stop_bits = ( config->stop_bits == STOP_BITS_1 ) ? US_MR_NBSTOP_1_BIT : US_MR_NBSTOP_2_BIT; settings.channel_mode= US_MR_CHMODE_NORMAL; /* Configure USART in serial mode. */ if (!hardware_shaking) { usart_init_rs232( peripheral->port, &settings, sysclk_get_peripheral_hz()); } else { usart_init_hw_handshaking( peripheral->port, &settings, sysclk_get_peripheral_hz()); } /* Enable uart interrupt */ NVIC_SetPriority( platform_flexcom_irq_numbers[peripheral->uart_id], 0x06 ); NVIC_EnableIRQ( platform_flexcom_irq_numbers[peripheral->uart_id] ); /* Enable PDC transmit */ pdc_enable_transfer( usart_get_pdc_base( peripheral->port ), PERIPH_PTCR_TXTEN | PERIPH_PTCR_RXTEN ); pdc_disable_transfer( usart_get_pdc_base( driver->peripheral->port ), PERIPH_PTCR_TXTDIS ); pdc_uart_packet.ul_addr = (uint32_t)driver->rx_ring_buffer->buffer; pdc_uart_packet.ul_size = (uint32_t)driver->rx_ring_buffer->size; pdc_rx_init( usart_get_pdc_base( peripheral->port ), &pdc_uart_packet, &pdc_uart_packet ); pdc_uart_tx_packet.ul_addr = (uint32_t)0; pdc_uart_tx_packet.ul_size = (uint32_t)1; pdc_tx_init( usart_get_pdc_base( driver->peripheral->port ), &pdc_uart_tx_packet, NULL ); usart_enable_interrupt( peripheral->port, US_IER_ENDRX | US_IER_RXBUFF | US_IER_RXRDY | US_IER_ENDTX ); /* Enable the receiver and transmitter. */ usart_enable_tx( peripheral->port ); usart_enable_rx( peripheral->port ); exit: platform_mcu_powersave_enable( ); return err; }
error_t xmc4700EthInit(NetInterface *interface) { error_t error; //Debug message TRACE_INFO("Initializing XMC4700 Ethernet MAC...\r\n"); //Save underlying network interface nicDriverInterface = interface; //Disable parity error trap SCU_PARITY->PETE = 0; //Disable unaligned access trap PPB->CCR &= ~PPB_CCR_UNALIGN_TRP_Msk; //Enable ETH0 peripheral clock SCU_CLK->CLKSET = SCU_CLK_CLKSET_ETH0CEN_Msk; //GPIO configuration xmc4700EthInitGpio(interface); //Reset ETH0 peripheral SCU_RESET->PRSET2 = SCU_RESET_PRSET2_ETH0RS_Msk; SCU_RESET->PRCLR2 = SCU_RESET_PRCLR2_ETH0RS_Msk; //Reset DMA controller ETH0->BUS_MODE |= ETH_BUS_MODE_SWR_Msk; //Wait for the reset to complete while(ETH0->BUS_MODE & ETH_BUS_MODE_SWR_Msk); //Adjust MDC clock range depending on ETH clock frequency ETH0->GMII_ADDRESS = ETH_GMII_ADDRESS_CR_DIV62; //PHY transceiver initialization error = interface->phyDriver->init(interface); //Failed to initialize PHY transceiver? if(error) return error; //Use default MAC configuration ETH0->MAC_CONFIGURATION = ETH_MAC_CONFIGURATION_RESERVED15_Msk | ETH_MAC_CONFIGURATION_DO_Msk; //Set the MAC address ETH0->MAC_ADDRESS0_LOW = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16); ETH0->MAC_ADDRESS0_HIGH = interface->macAddr.w[2]; //Initialize hash table ETH0->HASH_TABLE_LOW = 0; ETH0->HASH_TABLE_HIGH = 0; //Configure the receive filter ETH0->MAC_FRAME_FILTER = ETH_MAC_FRAME_FILTER_HPF_Msk | ETH_MAC_FRAME_FILTER_HMC_Msk; //Disable flow control ETH0->FLOW_CONTROL = 0; //Enable store and forward mode ETH0->OPERATION_MODE = ETH_OPERATION_MODE_RSF_Msk | ETH_OPERATION_MODE_TSF_Msk; //Configure DMA bus mode ETH0->BUS_MODE = ETH_BUS_MODE_AAL_Msk | ETH_BUS_MODE_USP_Msk | ETH_BUS_MODE_RPBL_1 | ETH_BUS_MODE_PR_1_1 | ETH_BUS_MODE_PBL_1; //Initialize DMA descriptor lists xmc4700EthInitDmaDesc(interface); //Prevent interrupts from being generated when statistic counters reach //half their maximum value ETH0->MMC_TRANSMIT_INTERRUPT_MASK = 0xFFFFFFFF; ETH0->MMC_RECEIVE_INTERRUPT_MASK = 0xFFFFFFFF; ETH0->MMC_IPC_RECEIVE_INTERRUPT_MASK = 0xFFFFFFFF; //Disable MAC interrupts ETH0->INTERRUPT_MASK = ETH_INTERRUPT_MASK_TSIM_Msk | ETH_INTERRUPT_MASK_PMTIM_Msk; //Enable the desired DMA interrupts ETH0->INTERRUPT_ENABLE = ETH_INTERRUPT_ENABLE_NIE_Msk | ETH_INTERRUPT_ENABLE_RIE_Msk | ETH_INTERRUPT_ENABLE_TIE_Msk; //Set priority grouping (6 bits for pre-emption priority, no bits for subpriority) NVIC_SetPriorityGrouping(XMC4700_ETH_IRQ_PRIORITY_GROUPING); //Configure Ethernet interrupt priority NVIC_SetPriority(ETH0_0_IRQn, NVIC_EncodePriority(XMC4700_ETH_IRQ_PRIORITY_GROUPING, XMC4700_ETH_IRQ_GROUP_PRIORITY, XMC4700_ETH_IRQ_SUB_PRIORITY)); //Enable MAC transmission and reception ETH0->MAC_CONFIGURATION |= ETH_MAC_CONFIGURATION_TE_Msk | ETH_MAC_CONFIGURATION_RE_Msk; //Enable DMA transmission and reception ETH0->OPERATION_MODE |= ETH_OPERATION_MODE_ST_Msk | ETH_OPERATION_MODE_SR_Msk; //Accept any packets from the upper layer osSetEvent(&interface->nicTxEvent); //Successful initialization return NO_ERROR; }
int main(void) { if (PM->RCAUSE.reg & (PM_RCAUSE_POR | PM_RCAUSE_BOD12 | PM_RCAUSE_BOD33)) { // On powerup, force a clean reset of the MT7620 pin_low(PIN_SOC_RST); pin_out(PIN_SOC_RST); // turn off 3.3V to SoC pin_low(PIN_SOC_PWR); pin_out(PIN_SOC_PWR); // pull 1.8V low pin_low(PIN_18_V); pin_out(PIN_18_V); clock_init_crystal(GCLK_SYSTEM, GCLK_32K); timer_clock_enable(TC_BOOT); // hold everything low boot_delay_ms(50); // power off for 50ms pin_high(PIN_SOC_PWR); boot_delay_ms(2); // 2ms until 1.8 rail comes on pin_high(PIN_18_V); boot_delay_ms(50); // 50ms before soc rst comes on } else { clock_init_crystal(GCLK_SYSTEM, GCLK_32K); } pin_mux(PIN_USB_DM); pin_mux(PIN_USB_DP); usb_init(); usb_attach(); NVIC_SetPriority(USB_IRQn, 0xff); pin_in(PIN_SOC_RST); pin_high(PIN_SOC_PWR); pin_out(PIN_SOC_PWR); pin_low(PORT_A.power); pin_out(PORT_A.power); pin_low(PORT_B.power); pin_out(PORT_B.power); pin_pull_up(PIN_BRIDGE_CS); pin_pull_up(PIN_FLASH_CS); pin_pull_up(PIN_SERIAL_TX); pin_pull_up(PIN_SERIAL_RX); dma_init(); NVIC_EnableIRQ(DMAC_IRQn); NVIC_SetPriority(DMAC_IRQn, 0xff); eic_init(); NVIC_EnableIRQ(EIC_IRQn); NVIC_SetPriority(EIC_IRQn, 0xff); evsys_init(); NVIC_EnableIRQ(EVSYS_IRQn); NVIC_SetPriority(EVSYS_IRQn, 0); adc_init(GCLK_SYSTEM, ADC_REFCTRL_REFSEL_INTVCC1); dac_init(GCLK_32K); bridge_init(); port_init(&port_a, 1, &PORT_A, GCLK_PORT_A, TCC_PORT_A, DMA_PORT_A_TX, DMA_PORT_A_RX); port_init(&port_b, 2, &PORT_B, GCLK_PORT_B, TCC_PORT_B, DMA_PORT_B_TX, DMA_PORT_B_RX); __enable_irq(); SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk; init_breathing_animation(); while (1) { __WFI(); } }
uint32_t app_timer_init(uint32_t prescaler, uint8_t max_timers, uint8_t op_queues_size, void * p_buffer, app_timer_evt_schedule_func_t evt_schedule_func) { int i; // Check that buffer is correctly aligned if (!is_word_aligned(p_buffer)) { return NRF_ERROR_INVALID_PARAM; } // Check for NULL buffer if (p_buffer == NULL) { return NRF_ERROR_INVALID_PARAM; } // Stop RTC to prevent any running timers from expiring (in case of reinitialization) rtc1_stop(); m_evt_schedule_func = evt_schedule_func; // Initialize timer node array m_node_array_size = max_timers; mp_nodes = p_buffer; for (i = 0; i < max_timers; i++) { mp_nodes[i].state = STATE_FREE; mp_nodes[i].is_running = false; } // Skip timer node array p_buffer = &((uint8_t *)p_buffer)[max_timers * sizeof(timer_node_t)]; // Initialize users array m_user_array_size = APP_TIMER_INT_LEVELS; mp_users = p_buffer; // Skip user array p_buffer = &((uint8_t *)p_buffer)[APP_TIMER_INT_LEVELS * sizeof(timer_user_t)]; // Initialize operation queues for (i = 0; i < APP_TIMER_INT_LEVELS; i++) { timer_user_t * p_user = &mp_users[i]; p_user->first = 0; p_user->last = 0; p_user->user_op_queue_size = op_queues_size; p_user->p_user_op_queue = p_buffer; // Skip operation queue p_buffer = &((uint8_t *)p_buffer)[op_queues_size * sizeof(timer_user_op_t)]; } m_timer_id_head = TIMER_NULL; m_ticks_elapsed_q_read_ind = 0; m_ticks_elapsed_q_write_ind = 0; NVIC_ClearPendingIRQ(SWI_IRQn); NVIC_SetPriority(SWI_IRQn, SWI0_IRQ_PRI); NVIC_EnableIRQ(SWI_IRQn); rtc1_init(prescaler); m_ticks_latest = rtc1_counter_get(); return NRF_SUCCESS; }
/*********************************************************************//** * @brief c_entry: Main TI program body * @param[in] None * @return int **********************************************************************/ int c_entry(void) { PINSEL_CFG_Type PinCfg; /* Initialize debug via UART0 * – 115200bps * – 8 data bit * – No parity * – 1 stop bit * – No flow control */ debug_frmwrk_init(); // print welcome screen print_menu(); /* * Initialize SSP pin connect * P0.6 - SSEL1 * P0.7 - SCK1 * P0.8 - MISO1 * P0.9 - MOSI1 */ PinCfg.Funcnum = 2; PinCfg.OpenDrain = 0; PinCfg.Pinmode = 0; PinCfg.Portnum = 0; PinCfg.Pinnum = 6; PINSEL_ConfigPin(&PinCfg); PinCfg.Pinnum = 7; PINSEL_ConfigPin(&PinCfg); PinCfg.Pinnum = 8; PINSEL_ConfigPin(&PinCfg); PinCfg.Pinnum = 9; PINSEL_ConfigPin(&PinCfg); /* * Initialize SSP pin connect * P0.15 - SCK * P0.16 - SSEL * P0.17 - MISO * P0.18 - MOSI */ PinCfg.Funcnum = 2; PinCfg.OpenDrain = 0; PinCfg.Pinmode = 0; PinCfg.Portnum = 0; PinCfg.Pinnum = 15; PINSEL_ConfigPin(&PinCfg); PinCfg.Pinnum = 17; PINSEL_ConfigPin(&PinCfg); PinCfg.Pinnum = 18; PINSEL_ConfigPin(&PinCfg); PinCfg.Pinnum = 16; PINSEL_ConfigPin(&PinCfg); /* Initializing Master SSP device section ------------------------------------------- */ // initialize SSP configuration structure to default SSP_ConfigStructInit(&SSP_ConfigStruct); // Re-configure SSP to TI frame format SSP_ConfigStruct.FrameFormat = SSP_FRAME_TI; // Initialize SSP peripheral with parameter given in structure above SSP_Init(SSPDEV_M, &SSP_ConfigStruct); // Enable SSP peripheral SSP_Cmd(SSPDEV_M, ENABLE); /* Initializing Slave SSP device section ------------------------------------------- */ // initialize SSP configuration structure to default SSP_ConfigStructInit(&SSP_ConfigStruct); /* Re-configure mode for SSP device */ SSP_ConfigStruct.Mode = SSP_SLAVE_MODE; // Re-configure SSP to TI frame format SSP_ConfigStruct.FrameFormat = SSP_FRAME_TI; // Initialize SSP peripheral with parameter given in structure above SSP_Init(SSPDEV_S, &SSP_ConfigStruct); // Enable SSP peripheral SSP_Cmd(SSPDEV_S, ENABLE); /* Interrupt configuration section ------------------------------------------------- */ #if ((USEDSSPDEV_S == 0) || (USEDSSPDEV_M == 0)) /* preemption = 1, sub-priority = 1 */ NVIC_SetPriority(SSP0_IRQn, ((0x01<<3)|0x01)); /* Enable SSP0 interrupt */ NVIC_EnableIRQ(SSP0_IRQn); #endif #if ((USEDSSPDEV_S == 1) || (USEDSSPDEV_M == 1)) /* preemption = 1, sub-priority = 1 */ NVIC_SetPriority(SSP1_IRQn, ((0x01<<3)|0x01)); /* Enable SSP0 interrupt */ NVIC_EnableIRQ(SSP1_IRQn); #endif /* Initializing Buffer section ------------------------------------------------- */ Buffer_Init(); /* Start Transmit/Receive between Master and Slave ----------------------------- */ complete_S = FALSE; complete_M = FALSE; /* Slave must be ready first */ ssp_SlaveReadWrite(SSPDEV_S, Slave_Rx_Buf, Slave_Tx_Buf, BUFFER_SIZE); /* Then Master can start its transferring */ ssp_MasterReadWrite(SSPDEV_M, Master_Rx_Buf, Master_Tx_Buf, BUFFER_SIZE); /* Wait for complete */ while ((complete_S == FALSE) || (complete_M == FALSE)); /* Verify buffer */ Buffer_Verify(); _DBG_("Verify success!\n\r"); /* Loop forever */ while(1); return 1; }
uint8_t usart1_init(void) { //zmienna do zwracania statusu funkcji uint8_t usart_status; //inicjalizacja struktur od GPIO GPIO_InitTypeDef GPIO_InitStruct; usart_status = UART_INIT_ERROR; /* Enable GPIO clock */ __HAL_RCC_GPIOA_CLK_ENABLE(); // Enable clock for USART1 peripheral __HAL_RCC_USART1_CLK_ENABLE(); /* Configure USART Tx as alternate function */ GPIO_InitStruct.Pin = GPIO_PIN_9; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FAST; GPIO_InitStruct.Alternate = GPIO_AF7_USART1; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); /* Configure USART Rx as alternate function */ GPIO_InitStruct.Pin = GPIO_PIN_10; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FAST; GPIO_InitStruct.Alternate = GPIO_AF7_USART1; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); //Priorytet przerwania NVIC_SetPriority(USART1_IRQn, 2); NVIC_EnableIRQ(USART1_IRQn); //Handle USART1_HandleStruct.Instance = USART1; USART1_HandleStruct.Init.BaudRate = BAUDRATE_USART1; USART1_HandleStruct.Init.StopBits = USART_STOPBITS_1; USART1_HandleStruct.Init.Parity = USART_PARITY_NONE; USART1_HandleStruct.Init.Mode = USART_MODE_TX_RX; //Init usart_status = HAL_UART_Init(&USART1_HandleStruct); //USART2 enable __HAL_UART_ENABLE(&USART1_HandleStruct); #ifdef USART1_IT_RX_ON USART1 -> CR1 |= USART_CR1_RXNEIE; #endif return usart_status; }
/*********************************************************************//** * @brief c_entry: Main program body * @param[in] None * @return int **********************************************************************/ int c_entry(void) { uint32_t i; GPDMA_Channel_CFG_Type GPDMACfg; I2S_MODEConf_Type I2S_ClkConfig; I2S_CFG_Type I2S_ConfigStruct; I2S_DMAConf_Type I2S_DMAStruct; PINSEL_CFG_Type PinCfg; /* Initialize debug via UART0 * – 115200bps * – 8 data bit * – No parity * – 1 stop bit * – No flow control */ debug_frmwrk_init(); //print menu screen print_menu(); //Initialize buffer Buffer_Init(); _DBG_("Press '1' to initialize buffer..."); while(_DG !='1'); _DBG_("Transmit Buffer init: ..."); for(i=0;i<BUFFER_SIZE;i++) { _DBH32(I2STXBuffer[i]);_DBG_(""); } _DBG_("Receive Buffer init: ..."); for(i=0;i<BUFFER_SIZE;i++) { _DBH32(I2SRXBuffer[i]);_DBG_(""); } /* Pin configuration: * Assign: - P0.4 as I2SRX_CLK * - P0.5 as I2SRX_WS * - P0.6 as I2SRX_SDA * - P0.7 as I2STX_CLK * - P0.8 as I2STX_WS * - P0.9 as I2STX_SDA */ PinCfg.Funcnum = 1; PinCfg.OpenDrain = 0; PinCfg.Pinmode = 0; PinCfg.Pinnum = 4; PinCfg.Portnum = 0; PINSEL_ConfigPin(&PinCfg); PinCfg.Pinnum = 5; PINSEL_ConfigPin(&PinCfg); PinCfg.Pinnum = 6; PINSEL_ConfigPin(&PinCfg); PinCfg.Pinnum = 7; PINSEL_ConfigPin(&PinCfg); PinCfg.Pinnum = 8; PINSEL_ConfigPin(&PinCfg); PinCfg.Pinnum = 9; PINSEL_ConfigPin(&PinCfg); /* Initialize I2S */ I2S_Init(LPC_I2S); //Setup for I2S: RX is similar with TX /* setup: * - wordwidth: 16 bits * - stereo mode * - master mode for I2S_TX and slave for I2S_RX * - ws_halfperiod is 31 * - not use mute mode * - use reset and stop mode * - select the fractional rate divider clock output as the source, * - disable 4-pin mode * - MCLK ouput is disable * - Frequency = 44.1 kHz * Because we use mode I2STXMODE[3:0]= 0000, I2SDAO[5]=0 and * I2SRX[3:0]=0000, I2SDAI[5] = 1. So we have I2SRX_CLK = I2STX_CLK * --> I2SRXBITRATE = 1 (not divide TXCLK to produce RXCLK) */ /* Audio Config*/ I2S_ConfigStruct.wordwidth = I2S_WORDWIDTH_16; I2S_ConfigStruct.mono = I2S_STEREO; I2S_ConfigStruct.stop = I2S_STOP_ENABLE; I2S_ConfigStruct.reset = I2S_RESET_ENABLE; I2S_ConfigStruct.ws_sel = I2S_MASTER_MODE; I2S_ConfigStruct.mute = I2S_MUTE_DISABLE; I2S_Config(LPC_I2S,I2S_TX_MODE,&I2S_ConfigStruct); I2S_ConfigStruct.ws_sel = I2S_SLAVE_MODE; I2S_Config(LPC_I2S,I2S_RX_MODE,&I2S_ConfigStruct); /* Clock Mode Config*/ I2S_ClkConfig.clksel = I2S_CLKSEL_FRDCLK; I2S_ClkConfig.fpin = I2S_4PIN_DISABLE; I2S_ClkConfig.mcena = I2S_MCLK_DISABLE; I2S_ModeConfig(LPC_I2S,&I2S_ClkConfig,I2S_TX_MODE); I2S_ModeConfig(LPC_I2S,&I2S_ClkConfig,I2S_RX_MODE); /* Set up frequency and bit rate*/ I2S_FreqConfig(LPC_I2S, 44100, I2S_TX_MODE); I2S_SetBitRate(LPC_I2S, 0, I2S_RX_MODE); _DBG_("Press '2' to initialize DMA..."); while(_DG !='2'); /* GPDMA Interrupt configuration section ------------------------------------------------- */ /* Initialize GPDMA controller */ GPDMA_Init(); LPC_GPDMA->DMACConfig = 0x01; /* Setting GPDMA interrupt */ // Disable interrupt for DMA NVIC_DisableIRQ (DMA_IRQn); /* preemption = 1, sub-priority = 1 */ NVIC_SetPriority(DMA_IRQn, ((0x01<<3)|0x01)); /* * Configure GPDMA channel 0 ------------------------------------------------------------- * Used for I2S Transmit */ // Setup GPDMA channel -------------------------------- // channel 0 GPDMACfg.ChannelNum = 0; // Source memory GPDMACfg.SrcMemAddr = DMA_SRC; // Destination memory GPDMACfg.DstMemAddr = 0; // Transfer size GPDMACfg.TransferSize = BUFFER_SIZE; // Transfer width - unused GPDMACfg.TransferWidth = 0; // Transfer type GPDMACfg.TransferType = GPDMA_TRANSFERTYPE_M2P; // Source connection GPDMACfg.SrcConn = 0; // Destination connection - unused GPDMACfg.DstConn = GPDMA_CONN_I2S_Channel_0; // Linker List Item - unused GPDMACfg.DMALLI = 0; GPDMA_Setup(&GPDMACfg); _DBG_("DMA Channel 0 setting finised..."); /* Reset terminal counter */ Channel0_TC = 0; /* Reset Error counter */ Channel0_Err = 0; /* * Configure GPDMA channel 1 ------------------------------------------------------------- * Used for UART0 Receive */ // Setup GPDMA channel -------------------------------- // channel 1 GPDMACfg.ChannelNum = 1; // Source memory - unused GPDMACfg.SrcMemAddr = 0; // Destination memory GPDMACfg.DstMemAddr = DMA_DST; // Transfer size GPDMACfg.TransferSize = BUFFER_SIZE+1; // Transfer width - unused GPDMACfg.TransferWidth = 0; // Transfer type GPDMACfg.TransferType = GPDMA_TRANSFERTYPE_P2M; // Source connection - unused GPDMACfg.SrcConn = GPDMA_CONN_I2S_Channel_1; // Destination connection GPDMACfg.DstConn = 0; // Linker List Item - unused GPDMACfg.DMALLI = 0; GPDMA_Setup(&GPDMACfg); _DBG_("DMA Channel 1 setting finised..."); /* Reset terminal counter */ Channel1_TC = 0; /* Reset Error counter */ Channel1_Err = 0; // Enable GPDMA channel 0 & 1 GPDMA_ChannelCmd(0, ENABLE); GPDMA_ChannelCmd(1, ENABLE); // Enable interrupt for DMA NVIC_EnableIRQ (DMA_IRQn); _DBG_("Press '3' to start I2S transfer process..."); while(_DG !='3'); _DBG_("I2S Start..."); I2S_DMAStruct.DMAIndex = I2S_DMA_2; I2S_DMAStruct.depth = 8; I2S_DMAConfig(LPC_I2S, &I2S_DMAStruct, I2S_RX_MODE); I2S_DMAStruct.DMAIndex = I2S_DMA_1; I2S_DMAStruct.depth = 1; I2S_DMAConfig(LPC_I2S, &I2S_DMAStruct, I2S_TX_MODE); I2S_Start(LPC_I2S); I2S_DMACmd(LPC_I2S, I2S_DMA_2, I2S_RX_MODE, ENABLE); I2S_DMACmd(LPC_I2S, I2S_DMA_1, I2S_TX_MODE, ENABLE); while ((Channel0_TC == 0)||(Channel1_TC == 0) ); _DBG_("I2S Finish..."); _DBG_("Receive Buffer data: ..."); for(i=0;i<BUFFER_SIZE+1;i++) { _DBH32(I2SRXBuffer[i]); if(I2SRXBuffer[i]==0) { _DBG_(" ->Dummy data"); } else _DBG_(""); } I2S_DeInit(LPC_I2S); while(1); return 1; }
/*********************************************************************//** * @brief c_entry: Main program body * @param[in] None * @return int **********************************************************************/ int c_entry(void) { PINSEL_CFG_Type PinCfg; uint8_t idx,i; /* Initialize debug via UART0 * – 115200bps * – 8 data bit * – No parity * – 1 stop bit * – No flow control */ debug_frmwrk_init(); //print menu screen print_menu(); /* I2C block ------------------------------------------------------------------- */ /* * Init I2C pin connect */ PinCfg.OpenDrain = 0; PinCfg.Pinmode = 0; PinCfg.Funcnum = 1; PinCfg.Pinnum = 27; PinCfg.Portnum = 0; PINSEL_ConfigPin(&PinCfg);//SDA0 PinCfg.Pinnum = 28; PINSEL_ConfigPin(&PinCfg);//SCL0 // Initialize I2C peripheral I2C_Init(I2CDEV, 100000); /* Configure interrupt for I2C in NVIC of ARM core */ /* Disable I2C0 interrupt */ NVIC_DisableIRQ(I2C0_IRQn); /* preemption = 1, sub-priority = 0 */ NVIC_SetPriority(I2C0_IRQn, ((0x01<<3)|0x01)); //enable I2C interrupt I2C_IntCmd(LPC_I2C0, ENABLE); /* Enable I2C operation */ I2C_Cmd(I2CDEV, ENABLE); while(1) { idx=0;count=0; while(idx<2) { if(idx==0) { _DBG_("\n\rEnter monitor buffer size: "); } idx++; switch(_DG) { case '0': count=(count<<4)|0x00;break; case '1': count=(count<<4)|0x01;break; case '2': count=(count<<4)|0x02;break; case '3': count=(count<<4)|0x03;break; case '4': count=(count<<4)|0x04;break; case '5': count=(count<<4)|0x05;break; case '6': count=(count<<4)|0x06;break; case '7': count=(count<<4)|0x07;break; case '8': count=(count<<4)|0x08;break; case '9': count=(count<<4)|0x09;break; case 'a': count=(count<<4)|0x0A;break; case 'A': count=(count<<4)|0x0A;break; case 'b': count=(count<<4)|0x0B;break; case 'B': count=(count<<4)|0x0B;break; case 'c': count=(count<<4)|0x0C;break; case 'C': count=(count<<4)|0x0C;break; case 'd': count=(count<<4)|0x0D;break; case 'D': count=(count<<4)|0x0D;break; case 'e': count=(count<<4)|0x0E;break; case 'E': count=(count<<4)|0x0E;break; case 'f': count=(count<<4)|0x0F;break; case 'F': count=(count<<4)|0x0F;break; default: idx=0;count=0;break; } if(idx==2) { if(count>BUFFER_SIZE) { _DBG_("invalid! The size is bigger than ");_DBH(BUFFER_SIZE); idx=0;count=0; } else _DBH(count); } } //Configure I2C in monitor mode I2C_MonitorModeConfig(I2CDEV,(uint32_t)I2C_MONITOR_CFG_MATCHALL, ENABLE); I2C_MonitorModeCmd(I2CDEV, ENABLE); _DBG_("\n\rStart monitoring I2C bus..."); while(done==FALSE); done=FALSE; _DBG_("done!"); for(i=0;i<count;i++) { if((i%16)==0) _DBG_(""); _DBH(buffer[i]);_DBC(0x20); buffer[i]=0; } } return 1; }
/** * \brief usb_iad_hid_aud Application entry point. * * Starts the driver and waits for an audio input stream to forward to the DAC. */ int main(void) { volatile uint8_t usbConn = 0; volatile uint8_t audioOn = 0; int32_t numDiff = 0, prevDiff = 0; int8_t clockAdjust = 0; /* Disable watchdog */ WDT_Disable(WDT); SCB_EnableICache(); SCB_EnableDCache(); printf("-- USB HID + Audio Device Example %s --\n\r", SOFTPACK_VERSION); printf("-- %s\n\r", BOARD_NAME); printf("-- Compiled: %s %s With %s--\n\r", __DATE__, __TIME__ , COMPILER_NAME); TimeTick_Configure(); /* Interrupt priority */ NVIC_SetPriority(USBHS_IRQn, 2); /* If they are present, configure Vbus & Wake-up pins */ PIO_InitializeInterrupts(0); /* Initialize all USB power (off) */ _ConfigureUsbhs(); /* ----- HID Function Initialize */ #ifdef NO_PUSHBUTTON printf("-- : DBG key 1 2 used as buttons\n\r"); printf("-- : 1st press to push, 2nd press to release\n\r"); #else /* Initialize key statuses and configure push buttons */ PIO_Configure(pinsPushButtons, PIO_LISTSIZE(pinsPushButtons)); #endif memset(keyStatus, 1, NUM_KEYS); //LED_Configure(LED_NUMLOCK); /* Audio STREAM LED */ LED_Configure(USBD_LEDOTHER); /* Configure Audio */ _ConfigureAudioPlay(AUDDevice_SAMPLERATE, BOARD_MCK); /* Configure DMA */ _ConfigureDma(); /* USB audio driver initialization */ HIDAUDDDriver_Initialize(&hidauddDriverDescriptors); /* connect if needed */ USBD_Connect(); /* Infinite loop */ while (1) { if (USBD_GetState() < USBD_STATE_CONFIGURED) { usbConn = 0; continue; } if (audioOn) { if (isDacActive == 0) { AudioPlayEnable(0); printf("audE "); isFirstFrame = 1; audioOn = 0; } else { numDiff = numBuffersToSend - DAC_DELAY; if (prevDiff != numDiff) { prevDiff = numDiff; if (numDiff > 1 && clockAdjust != 1) { printf("+"); /* USB too fast or SSC too slow: faster clock */ clockAdjust = 1; _SyncAdjust(1); } if (numDiff < -1 && clockAdjust != -1) { printf("-"); /* USB too slow or SSC too fast: slower clock */ clockAdjust = -1; _SyncAdjust(-1); } if (numDiff == 0 && clockAdjust != 0) { clockAdjust = 0; _SyncAdjust(0); } } } } else if (isDacActive) { printf("audS "); audioOn = 1; } if (usbConn == 0) { usbConn = 1; /* Start Reading the incoming audio stream */ AUDDFunction_Read(buffers[inBufferIndex], AUDDevice_BYTESPERFRAME, (TransferCallback) FrameReceived, 0); // No optional argument } HIDDKeyboardProcessKeys(); } }
/**@brief Function for initializing the RTC1 counter. * * @param[in] prescaler Value of the RTC1 PRESCALER register. Set to 0 for no prescaling. */ static void rtc1_init(uint32_t prescaler) { NRF_RTC1->PRESCALER = prescaler; NVIC_SetPriority(RTC1_IRQn, RTC1_IRQ_PRI); }
void UARTClass::setInterruptPriority(uint32_t priority) { NVIC_SetPriority(_dwIrq, priority & 0x0F); }
int gpio_init_int(gpio_t dev, gpio_pp_t pullup, gpio_flank_t flank, gpio_cb_t cb, void *arg) { int res; Pio *port = 0; uint32_t pin = 0; /* initialize port as input */ res = gpio_init_in(dev, pullup); if (res < 0) { return res; } /* read port and enable port interrupts */ switch (dev) { #if GPIO_0_EN case GPIO_0: port = GPIO_0_DEV; pin = GPIO_0_PIN; NVIC_SetPriority(GPIO_0_IRQ, GPIO_IRQ_PRIO); NVIC_EnableIRQ(GPIO_0_IRQ); break; #endif #if GPIO_1_EN case GPIO_1: port = GPIO_1_DEV; pin = GPIO_1_PIN; NVIC_SetPriority(GPIO_1_IRQ, GPIO_IRQ_PRIO); NVIC_EnableIRQ(GPIO_1_IRQ); break; #endif #if GPIO_2_EN case GPIO_2: port = GPIO_2_DEV; pin = GPIO_2_PIN; NVIC_SetPriority(GPIO_2_IRQ, GPIO_IRQ_PRIO); NVIC_EnableIRQ(GPIO_2_IRQ); break; #endif #if GPIO_3_EN case GPIO_3: port = GPIO_3_DEV; pin = GPIO_3_PIN; NVIC_SetPriority(GPIO_3_IRQ, GPIO_IRQ_PRIO); NVIC_EnableIRQ(GPIO_3_IRQ); break; #endif #if GPIO_4_EN case GPIO_4: port = GPIO_4_DEV; pin = GPIO_4_PIN; NVIC_SetPriority(GPIO_4_IRQ, GPIO_IRQ_PRIO); NVIC_EnableIRQ(GPIO_4_IRQ); break; #endif #if GPIO_5_EN case GPIO_5: port = GPIO_5_DEV; pin = GPIO_5_PIN; NVIC_SetPriority(GPIO_5_IRQ, GPIO_IRQ_PRIO); NVIC_EnableIRQ(GPIO_5_IRQ); break; #endif #if GPIO_6_EN case GPIO_6: port = GPIO_6_DEV; pin = GPIO_6_PIN; NVIC_SetPriority(GPIO_6_IRQ, GPIO_IRQ_PRIO); NVIC_EnableIRQ(GPIO_6_IRQ); break; #endif #if GPIO_7_EN case GPIO_7: port = GPIO_7_DEV; pin = GPIO_7_PIN; NVIC_SetPriority(GPIO_7_IRQ, GPIO_IRQ_PRIO); NVIC_EnableIRQ(GPIO_7_IRQ); break; #endif #if GPIO_8_EN case GPIO_8: port = GPIO_8_DEV; pin = GPIO_8_PIN; NVIC_SetPriority(GPIO_8_IRQ, GPIO_IRQ_PRIO); NVIC_EnableIRQ(GPIO_8_IRQ); break; #endif #if GPIO_9_EN case GPIO_9: port = GPIO_9_DEV; pin = GPIO_9_PIN; NVIC_SetPriority(GPIO_9_IRQ, GPIO_IRQ_PRIO); NVIC_EnableIRQ(GPIO_9_IRQ); break; #endif #if GPIO_10_EN case GPIO_10: port = GPIO_10_DEV; pin = GPIO_10_PIN; NVIC_SetPriority(GPIO_10_IRQ, GPIO_IRQ_PRIO); NVIC_EnableIRQ(GPIO_10_IRQ); break; #endif #if GPIO_11_EN case GPIO_11: port = GPIO_11_DEV; pin = GPIO_11_PIN; NVIC_SetPriority(GPIO_11_IRQ, GPIO_IRQ_PRIO); NVIC_EnableIRQ(GPIO_11_IRQ); break; #endif #if GPIO_12_EN case GPIO_12: port = GPIO_12_DEV; pin = GPIO_12_PIN; NVIC_SetPriority(GPIO_12_IRQ, GPIO_IRQ_PRIO); NVIC_EnableIRQ(GPIO_12_IRQ); break; #endif #if GPIO_13_EN case GPIO_13: port = GPIO_13_DEV; pin = GPIO_13_PIN; NVIC_SetPriority(GPIO_13_IRQ, GPIO_IRQ_PRIO); NVIC_EnableIRQ(GPIO_13_IRQ); break; #endif #if GPIO_14_EN case GPIO_14: port = GPIO_14_DEV; pin = GPIO_14_PIN; NVIC_SetPriority(GPIO_14_IRQ, GPIO_IRQ_PRIO); NVIC_EnableIRQ(GPIO_14_IRQ); break; #endif #if GPIO_15_EN case GPIO_15: port = GPIO_15_DEV; pin = GPIO_15_PIN; NVIC_SetPriority(GPIO_15_IRQ, GPIO_IRQ_PRIO); NVIC_EnableIRQ(GPIO_15_IRQ); break; #endif } /* set callback function and parameter */ gpio_config[dev].cb = cb; gpio_config[dev].arg = arg; /* set the active flank */ switch (flank) { case GPIO_FALLING: port->PIO_AIMER = pin; port->PIO_ESR = pin; port->PIO_FELLSR = pin; break; case GPIO_RISING: port->PIO_AIMER = pin; port->PIO_ESR = pin; port->PIO_REHLSR = pin; break; case GPIO_BOTH: port->PIO_AIMDR = pin; break; } /* clean interrupt status register */ port->PIO_ISR; /* enable the interrupt for the given channel */ port->PIO_IER = pin; return 0; }
static void set_irq_priority(uint32_t priority) { NVIC_SetPriority(quan::stm32::usart::detail::get_irq_number<usart_type>::value,priority); }
int main(void) { NVIC_SetPriorityGrouping(3); /* enable GPIO */ RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN; RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN; RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN; RCC->AHB1ENR |= RCC_AHB1ENR_GPIODEN; RCC->AHB1ENR |= RCC_AHB1ENR_GPIOEEN; act::mode(GPIO_OUTPUT); stat::mode(GPIO_OUTPUT); error::mode(GPIO_OUTPUT); error::high(); estop::mode(GPIO_INPUT); /* setup ethernet */ phy_rst::mode(GPIO_OUTPUT_2MHz); phy_rst::high(); // release reset line eth_mii_crs::mode(GPIO_ALTERNATE | GPIO_AF_ETH); eth_rx_clk::mode(GPIO_ALTERNATE | GPIO_AF_ETH); eth_mdio::mode(GPIO_ALTERNATE | GPIO_AF_ETH); eth_mii_col::mode(GPIO_ALTERNATE | GPIO_AF_ETH); eth_mii_rx_dv::mode(GPIO_ALTERNATE | GPIO_AF_ETH); eth_mii_rxd2::mode(GPIO_ALTERNATE | GPIO_AF_ETH); eth_mii_rxd3::mode(GPIO_ALTERNATE | GPIO_AF_ETH); eth_mii_rx_er::mode(GPIO_ALTERNATE | GPIO_AF_ETH); eth_mii_tx_en::mode(GPIO_ALTERNATE | GPIO_AF_ETH); eth_mii_txd0::mode(GPIO_ALTERNATE | GPIO_AF_ETH); eth_mii_txd1::mode(GPIO_ALTERNATE | GPIO_AF_ETH); eth_mdc::mode(GPIO_ALTERNATE | GPIO_AF_ETH); eth_mii_txd2::mode(GPIO_ALTERNATE | GPIO_AF_ETH); eth_mii_tx_clk::mode(GPIO_ALTERNATE | GPIO_AF_ETH); eth_mii_rxd0::mode(GPIO_ALTERNATE | GPIO_AF_ETH); eth_mii_rxd1::mode(GPIO_ALTERNATE | GPIO_AF_ETH); eth_mii_txd3::mode(GPIO_ALTERNATE | GPIO_AF_ETH); /* Initialize Table */ register_table.model_number = 302; register_table.version = 0; register_table.id = 253; register_table.baud_rate = 34; // 57600???? register_table.last_packet = 0; register_table.system_time = 0; register_table.led = 0; dynamixel_init(); /* setup analog */ RCC->APB2ENR |= RCC_APB2ENR_ADC1EN | RCC_APB2ENR_ADC2EN | RCC_APB2ENR_ADC3EN; adc1.init(VOLTAGE_SENSE_ANALOG_CHANNEL, CURRENT_SENSE_ANALOG_CHANNEL); voltage_sense::mode(GPIO_INPUT_ANALOG); current_sense::mode(GPIO_INPUT_ANALOG); /* setup systick */ SysTick_Config(SystemCoreClock/1000); NVIC_SetPriority(SysTick_IRQn,2); NVIC_EnableIRQ(SysTick_IRQn); Ethernet_Init(); LwIP_Init(); if (!netapp_init()) while(1); __enable_irq(); /* done with setup, turn off err led */ error::low(); while(1) { /* check if any packet received */ if (ETH_CheckFrameReceived()) { /* process received ethernet packet */ LwIP_Pkt_Handle(); } LwIP_Periodic_Handle(register_table.system_time); } }
int timer_init(tim_t dev, unsigned int us_per_tick, void (*callback)(int)) { if (callback == 0 || us_per_tick == 0) { return -1; } switch (dev) { #ifdef TIMER_0_EN case TIMER_0: // timers[dev].base = &LPC_TMR0; LPC_SYS_CTL.PCONP.PCTIM0 = 1; LPC_SYS_CTL.PCLKSEL0.PCLK_TIMER0 = TIMER_0_CCLKSEL; LPC_TMR0.PR = TIMER_0_US_CONSTANT * us_per_tick; LPC_TMR0.CTCR.REGISTER = 0; LPC_TMR0.TCR.REGISTER = 0b10; LPC_TMR0.TCR.REGISTER = 0b01; /* configure and enable timer interrupts */ NVIC_SetPriority(TIMER0_IRQn, TIMER_IRQ_PRIO); NVIC_EnableIRQ(TIMER0_IRQn); break; #endif #ifdef TIMER_1_EN case TIMER_1: // timers[dev].base = &LPC_TMR1; LPC_SYS_CTL.PCONP.PCTIM1 = 1; LPC_SYS_CTL.PCLKSEL0.PCLK_TIMER1 = TIMER_1_CCLKSEL; LPC_TMR1.PR = TIMER_1_US_CONSTANT * us_per_tick; LPC_TMR1.CTCR.REGISTER = 0; LPC_TMR1.TCR.REGISTER = 0b10; LPC_TMR1.TCR.REGISTER = 0b01; /* configure and enable timer interrupts */ NVIC_SetPriority(TIMER1_IRQn, TIMER_IRQ_PRIO); NVIC_EnableIRQ(TIMER1_IRQn); break; #endif #ifdef TIMER_2_EN case TIMER_2: // timers[dev].base = &LPC_TMR2; LPC_SYS_CTL.PCONP.PCTIM2 = 1; LPC_SYS_CTL.PCLKSEL1.PCLK_TIMER2 = TIMER_2_CCLKSEL; LPC_TMR2.PR = TIMER_2_US_CONSTANT * us_per_tick; LPC_TMR2.CTCR.REGISTER = 0; LPC_TMR2.TCR.REGISTER = 0b10; LPC_TMR2.TCR.REGISTER = 0b01; NVIC_SetPriority(TIMER2_IRQn, TIMER_IRQ_PRIO); NVIC_EnableIRQ(TIMER2_IRQn); break; #endif #ifdef TIMER_3_EN case TIMER_3: // timers[dev].base = &LPC_TMR3; LPC_SYS_CTL.PCONP.PCTIM3 = 1; LPC_SYS_CTL.PCLKSEL1.PCLK_TIMER3 = TIMER_3_CCLKSEL; LPC_TMR3.PR = TIMER_3_US_CONSTANT * us_per_tick; LPC_TMR3.CTCR.REGISTER = 0; LPC_TMR3.TCR.REGISTER = 0b10; LPC_TMR3.TCR.REGISTER = 0b01; NVIC_SetPriority(TIMER3_IRQn, TIMER_IRQ_PRIO); NVIC_EnableIRQ(TIMER3_IRQn); break; #endif default: return -1; } timers[dev].callback = callback; return 1; }
/***************************************************************************//** * @brief * Main function. Setup ADC, FFT, clocks, PRS, DMA, Timer, * and process FFT forever. *******************************************************************************/ int main(void) { arm_status status; char buf[20]; bool redraw = false; int glibStatus; DMA_Init_TypeDef dmaInit; TIMER_Init_TypeDef timerInit = TIMER_INIT_DEFAULT; /* Initialize DVK board register access */ BSP_Init(BSP_INIT_DEFAULT); /* If first word of user data page is non-zero, enable eA Profiler trace */ BSP_TraceEtmSetup(); /* Connect audio in to ADC */ BSP_PeripheralAccess(BSP_AUDIO_IN, true); /* Wait a while in order to let signal from audio-in stabilize after */ /* enabling audio-in peripheral. */ RTCDRV_Trigger(1000, NULL); EMU_EnterEM2(true); /* Initialize the CFFT/CIFFT module */ status = arm_rfft_init_f32(&rfft_instance, &cfft_instance, GUITAR_AUDIO_BUFFER_SAMPLES, 0, /* forward transform */ 1); /* normal, not bitreversed, order */ if (status != ARM_MATH_SUCCESS) { /* Error initializing RFFT module. */ while (1) ; } dataReadyForFFT = false; processingFFT = false; /* Use the HFXO. We still only manage to process about * a third the buffers through FFT */ CMU_ClockSelectSet(cmuClock_HF, cmuSelect_HFXO); /* Setup SysTick Timer for 1 msec interrupts */ if (SysTick_Config(CMU_ClockFreqGet(cmuClock_CORE) / 1000)) { while (1) ; } /* Enable clocks required */ CMU_ClockEnable(cmuClock_HFPER, true); CMU_ClockEnable(cmuClock_ADC0, true); CMU_ClockEnable(cmuClock_PRS, true); CMU_ClockEnable(cmuClock_DMA, true); CMU_ClockEnable(cmuClock_TIMER0, true); NVIC_SetPriority(DMA_IRQn, 0); /* Highest priority */ /* Configure peripheral reflex system used by TIMER to trigger ADC/DAC */ guitarPRSConfig(GUITAR_PRS_CHANNEL); /* Configure general DMA issues */ dmaInit.hprot = 0; dmaInit.controlBlock = dmaControlBlock; DMA_Init(&dmaInit); /* Configure ADC used for audio-in */ guitarADCConfig(); /* Trigger sampling according to configured sample rate */ TIMER_TopSet(TIMER0, CMU_ClockFreqGet(cmuClock_HFPER) / GUITAR_AUDIO_SAMPLE_RATE); TIMER_Init(TIMER0, &timerInit); /* Wait until we have control over display */ while(!redraw) { redraw = TFT_AddressMappedInit(); } /* Init graphics context - abort on failure */ glibStatus = GLIB_contextInit(&gc); if (glibStatus != GLIB_OK) while (1) ; /* Clear the screen */ gc.backgroundColor = GLIB_rgbColor(0, 0, 0); GLIB_clear(&gc); while (1) { while (dataReadyForFFT) { float32_t freq; processingFFT = true; processFFT(); dataReadyForFFT = false; processingFFT = false; /* Get frequency and make string with one decimal accuracy */ freq = getFreq(); sprintf(buf, "%6.1f", freq); /* Check if we should control TFT display instead of AEM/board controller */ redraw = TFT_AddressMappedInit(); if (redraw) { gc.foregroundColor = GLIB_rgbColor(220, 220, 220); gc.backgroundColor = GLIB_rgbColor(0, 0, 0); /* Print the frequency somewhere in the middle of the screen */ GLIB_drawString(&gc, buf, strlen(buf), 100, 120, 1); } } EMU_EnterEM1(); } }