extern "C" void Reset_Handler()
{
  /* 4 bits for preemption priority */
  NVIC_SetPriorityGrouping(4);

  /* enable data/instruction cache, set wait cycles, set flash latency */
  FLASH->ACR |= FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN | FLASH_ACR_LATENCY_5WS;

  assert(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) == FLASH_ACR_LATENCY_5WS);

  /* enable FPU if needed */
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
  /* enable coprocessors CP10 and CP11 */
  SCB->CPACR |= (0x0f << 20);
#endif

  clock_init();

  /* data initialization */
  memcpy(&__data_start__, &__etext, (intptr_t)&__data_end__ - (intptr_t)&__data_start__);
  memcpy(&__data2_start__, &__etext2, (intptr_t)&__data2_end__ - (intptr_t)&__data2_start__);
  memset(&__bss_start__, 0, (intptr_t)&__bss_end__ - (intptr_t)&__bss_start__);
  memset(&__bss2_start__, 0, (intptr_t)&__bss2_end__ - (intptr_t)&__bss2_start__);

  /* set interrupt vector table offset */
  SCB->VTOR = (uint32_t)&interruptVectorTable;

  /* c++ constructors */
  __libc_init_array();

  gpio_init();
  i2s_init();

  main();
}
Exemple #2
0
int main(void)
{
  leds.initHW();

  NVIC_SetPriorityGrouping( NVIC_PriorityGroup_4 );

  leds.write( 0x0F );  delay_bad_ms( 200 );
  leds.write( 0x0A );  delay_bad_ms( 200 );
  leds.reset( 0x0F );  delay_bad_ms( 200 );

  xTaskCreate( task_leds, "leds", 2*def_stksz, 0, 1, 0 );
  xTaskCreate( task_usart2_send, "send", 2*def_stksz, 0, 1, 0 );
  xTaskCreate( task_usart2_recv, "recv", 2*def_stksz, 0, 1, 0 );
  xTaskCreate( task_string_send, "ss",     def_stksz, 0, 1, 0 );

  us2.initIRQ( configKERNEL_INTERRUPT_PRIORITY, 0 );
  us2.initHW();
  us2.init();
  us2.itConfig( USART_IT_RXNE, ENABLE );
  us2.setOnRecv( on_received_char );
  us2.enable();

  vTaskStartScheduler();
  die4led( 0xFF );

  return 0;
}
void IRQportableStartKernel()
{
    //Enable fault handlers
    SCB->SHCSR |= SCB_SHCSR_USGFAULTENA | SCB_SHCSR_BUSFAULTENA
            | SCB_SHCSR_MEMFAULTENA;
    //Enable traps for unaligned memory access and division by zero
    SCB->CCR |= SCB_CCR_DIV_0_TRP | SCB_CCR_UNALIGN_TRP;
    NVIC_SetPriorityGrouping(7);//This should disable interrupt nesting
    NVIC_SetPriority(SVCall_IRQn,3);//High priority for SVC (Max=0, min=15)
    NVIC_SetPriority(SysTick_IRQn,3);//High priority for SysTick (Max=0, min=15)
    SysTick->LOAD=SystemCoreClock/miosix::TICK_FREQ;
    //Start SysTick, set to generate interrupts
    SysTick->CTRL=SysTick_CTRL_ENABLE | SysTick_CTRL_TICKINT |
            SysTick_CTRL_CLKSOURCE;

    #ifdef SCHED_TYPE_CONTROL_BASED
    AuxiliaryTimer::IRQinit();
    #endif //SCHED_TYPE_CONTROL_BASED
    
    //create a temporary space to save current registers. This data is useless
    //since there's no way to stop the sheduler, but we need to save it anyway.
    unsigned int s_ctxsave[miosix::CTXSAVE_SIZE];
    ctxsave=s_ctxsave;//make global ctxsave point to it
    //Note, we can't use enableInterrupts() now since the call is not mathced
    //by a call to disableInterrupts()
    __enable_fault_irq();
    __enable_irq();
    miosix::Thread::yield();
    //Never reaches here
}
/**
 * \brief Configure the hardware.
 */
static void prvSetupHardware(void)
{
#ifdef EXAMPLE_LCD_SIGNALLING_ENABLE
	status_code_t status;
#endif

	/* ASF function to setup clocking. */
	sysclk_init();

	/* Ensure all priority bits are assigned as preemption priority bits. */
	NVIC_SetPriorityGrouping(__NVIC_PRIO_BITS);

	/* Atmel library function to setup for the evaluation kit being used. */
	board_init();

	/* PLC HAL service initialization */
	hal_init();
	hal_start();

#ifdef EXAMPLE_LCD_SIGNALLING_ENABLE
	/* Initialize the C42364A LCD glass component. */
	status = c42364a_init();
	if (status != STATUS_OK) {
		puts("-- LCD Initialization fails! --\r\n");
		while (1) {
		}
	}

	c42364a_set_contrast(15);
	c42364a_clear_all();
	c42364a_show_icon(C42364A_ICON_ATMEL);
	c42364a_show_icon(C42364A_ICON_WLESS);
	c42364a_show_text((const uint8_t *)"SERV  ");
#endif
}
Exemple #5
0
/**
 * This function will initial M487 board.
 */
void rt_hw_board_init(void)
{
    clock_init();

#ifdef RT_USING_HEAP
#ifdef __CC_ARM
    rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)SRAM_END);
#elif __ICCARM__
    rt_system_heap_init(__segment_end("HEAP"), (void*)SRAM_END);
#else
    /* init memory system */
    rt_system_heap_init((void*)&__bss_end, (void*)&__ram_top);
#endif
#endif /* RT_USING_HEAP */

    rt_hw_uart_init();

#ifdef RT_USING_CONSOLE
    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif

    SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
	
	NVIC_SetPriorityGrouping(7);
	
#ifdef RT_USING_COMPONENTS_INIT
    rt_components_board_init();
#endif
}
void SystemInit(void)
{
    DBG_FWsim_Log("SystemInit\n");

    /* PingPong Buffer Init */
    PPB_Init();

    /* Enable the memory management fault , Bus Fault, Usage Fault exception */
    //SCB->SHCSR |= (SCB_SHCSR_MEMFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk | SCB_SHCSR_USGFAULTENA_Msk);

    /* Ensure all priority bits are assigned as preemption priority bits. */
    NVIC_SetPriorityGrouping( 0 );

    #if (__FPU_USED == 1)
    SCB->CPACR |= ((3UL << 10*2) |                 /* set CP10 Full Access */
                   (3UL << 11*2)  );               /* set CP11 Full Access */
    #endif

    #ifdef UNALIGNED_SUPPORT_DISABLE
    SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
    #endif

    // relocate vector table to internal ram
    // updates also VTOR
    // TODO
}
Exemple #7
0
static void TIM2_CFG(  )
{
  TIM_TIMERCFG_Type TMR2_Cfg;
  TIM_MATCHCFG_Type TMR2_Match;

  /* On reset, Timer0/1 are enabled (PCTIM0/1 = 1), and Timer2/3 are disabled (PCTIM2/3 = 0).*/
  /* Initialize timer 0, prescale count time of 100uS */
  TMR2_Cfg.PrescaleOption = TIM_PRESCALE_USVAL;
  TMR2_Cfg.PrescaleValue = 10000;
  /* Use channel 0, MR0 */
  TMR2_Match.MatchChannel = 0;
  /* Enable interrupt when MR0 matches the value in TC register */
  TMR2_Match.IntOnMatch = ENABLE;
  /* Enable reset on MR0: TIMER will reset if MR0 matches it */
  TMR2_Match.ResetOnMatch = FALSE;
  /* Don't stop on MR0 if MR0 matches it*/
  TMR2_Match.StopOnMatch = TRUE;
  /* Do nothing for external output pin if match (see cmsis help, there are another options) */
  TMR2_Match.ExtMatchOutputType = TIM_EXTMATCH_NOTHING;
  /* Set Match value, count value of 2 (2 * 100uS = 200us ) */
  TMR2_Match.MatchValue = 250;
  /* Set configuration for Tim_config and Tim_MatchConfig */
  TIM_Init(LPC_TIM2, TIM_TIMER_MODE, &TMR2_Cfg);
  TIM_ConfigMatch(LPC_TIM2, &TMR2_Match);

  NVIC_SetPriorityGrouping(3);
  /* Preemption = 1, sub-priority = 1 */
  NVIC_SetPriority(TIMER2_IRQn, 2);
  /* Enable interrupt for timer 0 */
  NVIC_EnableIRQ(TIMER2_IRQn);
  /* Start timer 0 */
  TIM_Cmd(LPC_TIM2, ENABLE);
}
/**
 * @brief  Sets the priority grouping field (preemption priority and subpriority)
 *         using the required unlock sequence.
 * @param  PriorityGroup: The priority grouping bits length. 
 *         This parameter can be one of the following values:
 *         @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority
 *                                    4 bits for subpriority
 *         @arg NVIC_PRIORITYGROUP_1: 1 bits for preemption priority
 *                                    3 bits for subpriority
 *         @arg NVIC_PRIORITYGROUP_2: 2 bits for preemption priority
 *                                    2 bits for subpriority
 *         @arg NVIC_PRIORITYGROUP_3: 3 bits for preemption priority
 *                                    1 bits for subpriority
 *         @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority
 *                                    0 bits for subpriority
 * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. 
 *         The pending IRQ priority will be managed only by the subpriority. 
 * @retval None
 */
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) {
	/* Check the parameters */
	assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));

	/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
	NVIC_SetPriorityGrouping(PriorityGroup);
}
Exemple #9
0
static void prvSetupHardware( void )
{
extern void SystemCoreClockUpdate( void );
struct eic_line_config xEICLineConfiguration;

	/* Configure the external interrupt controller so button pushes can
	generate interrupts. */
	xEICLineConfiguration.eic_mode = EIC_MODE_EDGE_TRIGGERED;
	xEICLineConfiguration.eic_edge = EIC_EDGE_FALLING_EDGE;
	xEICLineConfiguration.eic_level = EIC_LEVEL_LOW_LEVEL;
	xEICLineConfiguration.eic_filter = EIC_FILTER_DISABLED;
	xEICLineConfiguration.eic_async = EIC_ASYNCH_MODE;
	eic_enable( EIC );
	eic_line_set_config( EIC, GPIO_PUSH_BUTTON_EIC_LINE, &xEICLineConfiguration );
	eic_line_set_callback( EIC, GPIO_PUSH_BUTTON_EIC_LINE, prvButtonISR, EIC_5_IRQn, 0 );
	eic_line_enable( EIC, GPIO_PUSH_BUTTON_EIC_LINE );

	/* ASF function to setup clocking. */
	sysclk_init();

	/* Ensure all priority bits are assigned as preemption priority bits. */
	NVIC_SetPriorityGrouping( 0 );

	/* Atmel library function to setup for the evaluation kit being used. */
	board_init();

	/* Initialise the sleep manager in case the low power demo is being used. */
	sleepmgr_init();
}
Exemple #10
0
void DAVE_Init(void)
{
          
    //  NVIC Priority Grouping
    NVIC_SetPriorityGrouping(1);

//****************************************************************************
// @Initialization of APPs Init Functions
//****************************************************************************
	//  MUX configurations
	DAVE_MUX_PreInit(); 
	//  Initialization of app 'CLK001'		     
	CLK001_Init();
	 
	//  Initialization of app 'SYSTM001'		     
	SYSTM001_Init();
	 
	//  Initialization of app 'I2C001'		     
	I2C001_Init();
	 
	//  Initialization of app 'NVIC002'		     
	NVIC002_Init();
	
      
	//  MUX configurations
	DAVE_MUX_Init();	
} //  End of function DAVE_Init
void platform_init_peripheral_irq_priorities( void )
{
    uint32_t i;
    uint32_t minPri = (1<<__NVIC_PRIO_BITS) - 1 - 1;
    NVIC_SetPriorityGrouping(0x00000000);

    for (i=0; i<48; i++)
    {
        // NVIC->IP[i] = 0xC0;
        NVIC_SetPriority((IRQn_Type)i, minPri);
    }
    NVIC_SetPriority(SysTick_IRQn, minPri);
    /* Interrupt priority setup. Called by WICED/platform/MCU/STM32F2xx/platform_init.c */
    NVIC_SetPriority( RTC_IRQn         ,  minPri ); /* RTC Wake-up event   */
    NVIC_SetPriority( SPI0_IRQn        ,  minPri ); /* SPI0          */
    NVIC_SetPriority( SPI1_IRQn        ,  3 ); /* WLAN SDIO           */
    NVIC_SetPriority( DMA_IRQn         ,  3 ); /* WLAN SPI DMA        */
    NVIC_SetPriority( UART0_IRQn       ,  minPri - 1); /* MICO_UART_0         */
    NVIC_SetPriority( UART1_IRQn       ,  minPri - 1); /* MICO_UART_1         */
    NVIC_SetPriority( UART2_IRQn       ,  minPri - 1); /* MICO_UART_2         */
    NVIC_SetPriority( UART3_IRQn       ,  minPri - 1); /* MICO_UART_3         */
    NVIC_SetPriority( I2C0_IRQn        ,  minPri ); /* MICO_I2C_0         */
    NVIC_SetPriority( I2C1_IRQn        ,  minPri ); /* MICO_I2C_1         */
    NVIC_SetPriority( I2C2_IRQn        ,  minPri ); /* MICO_I2C_2         */

    NVIC_SetPriority( PIN_INT0_IRQn    , minPri ); /* GPIO                */
    NVIC_SetPriority( PIN_INT1_IRQn    , minPri ); /* GPIO                */
    NVIC_SetPriority( PIN_INT2_IRQn    , minPri ); /* GPIO                */
    NVIC_SetPriority( PIN_INT3_IRQn    , minPri ); /* GPIO                */
    NVIC_SetPriority( PIN_INT4_IRQn    , minPri ); /* GPIO                */
    NVIC_SetPriority( PIN_INT5_IRQn    , minPri ); /* GPIO                */
    NVIC_SetPriority( PIN_INT6_IRQn    , minPri ); /* GPIO                */
    NVIC_SetPriority( PIN_INT7_IRQn    , minPri ); /* GPIO                */
}
Exemple #12
0
int main(void)
{
    DelayInit();
    GPIO_QuickInit(HW_GPIOE, 6, kGPIO_Mode_OPP);
    UART_QuickInit(UART0_RX_PD06_TX_PD07, 115200);
    
    /* 设置PORTE PORTA 中断 */
    GPIO_QuickInit(HW_GPIOE,26, kGPIO_Mode_IPU);
    GPIO_QuickInit(HW_GPIOA, 4, kGPIO_Mode_IPU);
    GPIO_CallbackInstall(HW_GPIOE, PORTE_ISR);
    GPIO_CallbackInstall(HW_GPIOA, PORTA_ISR);
    GPIO_ITDMAConfig(HW_GPIOE, 26, kGPIO_IT_RisingEdge, true);
    GPIO_ITDMAConfig(HW_GPIOA, 4,  kGPIO_IT_RisingEdge, true);
    
    printf("NVIC test connect E26&A04\r\n");
    /* 将系统 中断优先级分组 可以配置 16个 抢占优先级 和16个 子优先级 */
    NVIC_SetPriorityGrouping(NVIC_PriorityGroup_2);  //中断优先级分成2组
    NVIC_SetPriority(PORTE_IRQn, NVIC_EncodePriority(NVIC_PriorityGroup_2, 2, 2)); //设置PTE端口的抢占优先级的子优先级
    NVIC_SetPriority(PORTA_IRQn, NVIC_EncodePriority(NVIC_PriorityGroup_2, 2, 2));
    
    while(1)
    {
        GPIO_ToggleBit(HW_GPIOE, 6);
        DelayMs(500);
    }
}
Exemple #13
0
int main (void)
{
	/* Initialize the SAM system */
	sysclk_init();
	
	/* Initialize mcu's peripheral.*/
	board_init();
	
	/* Initialize the console uart */
	configure_console();
	
	/* Output demo information. */
	RS232printf("\n\r-- FreeRTOS Example --\n\r");
	
	/* Initialize the SPI0. */
//	spi_set_clock_configuration(0);
	
	/* Ensure all priority bits are assigned as preemption priority bits. */
	NVIC_SetPriorityGrouping( 0 );
		
	/* Create freeRTOS START task.*/
	xTaskCreate(task_start, (signed char *)"START", TASK_START_STACKSIZE, NULL,
				TASK_START_PRIORITY, NULL);
	
	/* Start the scheduler. */
	vTaskStartScheduler();
	
	/* Will only get here if there was insufficient memory to create the idle task. */
	return 0;
}
// The kernel is the central point in Smoothie : it stores modules, and handles event calls
Kernel::Kernel(){
    instance= this; // setup the Singleton instance of the kernel

    // serial first at fixed baud rate (DEFAULT_SERIAL_BAUD_RATE) so config can report errors to serial
    // Set to UART0, this will be changed to use the same UART as MRI if it's enabled
    this->serial = new SerialConsole(USBTX, USBRX, DEFAULT_SERIAL_BAUD_RATE);

    // Config next, but does not load cache yet
    // loads config from in memory source for test framework must be loaded by test
    this->config = nullptr;

    this->streams = new StreamOutputPool();
    this->streams->append_stream(this->serial);

    this->current_path   = "/";

    this->slow_ticker = new SlowTicker();

    // dummies (would be nice to refactor to not have to create a conveyor)
    this->conveyor= new Conveyor();

    // Configure UART depending on MRI config
    // Match up the SerialConsole to MRI UART. This makes it easy to use only one UART for both debug and actual commands.
    NVIC_SetPriorityGrouping(0);
    NVIC_SetPriority(UART0_IRQn, 5);
}
void HW_NVIC_init(void)
{

    // There are 3 bits of priority implemented in MDR32F9Qx device
    // Setting all bits to pre-emption, see link below
    // http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0552a/BABHGEAJ.html
    NVIC_SetPriorityGrouping( 3 );

    pr[0] = NVIC_GetPriority(SVCall_IRQn);
    pr[1] = NVIC_GetPriority(PendSV_IRQn);
    pr[2] = NVIC_GetPriority(SysTick_IRQn);
    pr[3] = NVIC_GetPriority(DMA_IRQn);
    pr[4] = NVIC_GetPriority(Timer2_IRQn);

    NVIC_SetPriority(DMA_IRQn,6);
    NVIC_SetPriority(Timer2_IRQn,6);

    pr[0] = NVIC_GetPriority(SVCall_IRQn);
    pr[1] = NVIC_GetPriority(PendSV_IRQn);
    pr[2] = NVIC_GetPriority(SysTick_IRQn);
    pr[3] = NVIC_GetPriority(DMA_IRQn);
    pr[4] = NVIC_GetPriority(Timer2_IRQn);


}
Exemple #16
0
/*..........................................................................*/
void QF_onStartup(void) {
    NVIC_InitTypeDef nvic_init;

    /* assing all priority bits for preemption-prio. and none to sub-prio. */
    NVIC_SetPriorityGrouping(0U);

    /* Set up and enable the SysTick timer.  It will be used as a reference
    * for delay loops in the interrupt handlers.  The SysTick timer period
    * will be set up for BSP_TICKS_PER_SEC.
    */
    SysTick_Config(SystemCoreClock / BSP_TICKS_PER_SEC);

//    /* Enable the EXTI0 Interrupt used for testing preemptions */
//    nvic_init.NVIC_IRQChannel                   = EXTI0_IRQn;
//    nvic_init.NVIC_IRQChannelPreemptionPriority = 0;
//    nvic_init.NVIC_IRQChannelSubPriority        = 0;
//    nvic_init.NVIC_IRQChannelCmd                = ENABLE;
//    NVIC_Init(&nvic_init);/* enables the device and sets interrupt priority */
//
//    nvic_eth_init.NVIC_IRQChannel                   = ETH_IRQn;
//    nvic_eth_init.NVIC_IRQChannelPreemptionPriority = 2;
//    nvic_eth_init.NVIC_IRQChannelSubPriority        = 0;
//    nvic_eth_init.NVIC_IRQChannelCmd                = ENABLE;
//    NVIC_Init(&nvic_eth_init);/* enables the device and sets interrupt priority */
//

    /* set priorities of all interrupts in the system... */
    NVIC_SetPriority(SysTick_IRQn, 	SYSTICK_PRIO);
    NVIC_SetPriority(EXTI0_IRQn,   	EXTI0_PRIO);
//    NVIC_SetPriority(ETH_IRQn,   	ETH_PRIO);
    /* ... */
}
static void prvSetupHardware( void )
{
	configCONFIGURE_LED();

	/* Ensure all priority bits are assigned as preemption priority bits. */
	NVIC_SetPriorityGrouping( 0 );
}
Exemple #18
0
void init_Priority(void){

	uint32_t priority, PG = 5, PP, SP; // priority grouping, pre-empt priority, subpriority
	NVIC_SetPriorityGrouping(5);

	PP = 0, SP = 0;
	priority = NVIC_EncodePriority(PG,PP,SP);
	NVIC_SetPriority(SysTick_IRQn, priority);
	PP = 1, SP = 0;
	priority = NVIC_EncodePriority(PG,PP,SP);
	NVIC_SetPriority(EINT3_IRQn, priority); // light sensor and SW3
	// interrupt with smallest time interval is given higher priority
	PP = 2, SP = 0;
	priority = NVIC_EncodePriority(PG,PP,SP);
	NVIC_SetPriority(TIMER1_IRQn, priority); // pca9532 led (250ms)
	PP = 2, SP = 1;
	priority = NVIC_EncodePriority(PG,PP,SP);
	NVIC_SetPriority(TIMER2_IRQn, priority); // rgb (1s)
	PP = 2, SP = 2;
	priority = NVIC_EncodePriority(PG,PP,SP);
	NVIC_SetPriority(TIMER3_IRQn, priority); // sampling (2s)
	// clear pending status before enabling
	NVIC_ClearPendingIRQ(EINT3_IRQn);
	NVIC_ClearPendingIRQ(TIMER1_IRQn);
	NVIC_ClearPendingIRQ(TIMER2_IRQn);
	NVIC_ClearPendingIRQ(TIMER3_IRQn);

	NVIC_EnableIRQ(EINT3_IRQn);
	NVIC_EnableIRQ(TIMER1_IRQn);
	NVIC_EnableIRQ(TIMER2_IRQn);
	NVIC_EnableIRQ(TIMER3_IRQn);
}
Exemple #19
0
int main( void )
{
	/* The examples assume that all priority bits are assigned as preemption
	priority bits. */
	NVIC_SetPriorityGrouping( 0UL );

	/* Start the timers that demonstrate FreeRTOS software timers and basic
	GPIO functionality. */
	vGPIOSoftwareTimersStart();

	/* Start the tasks that implements the command console on the UART, as
	described above. */
	vUARTCommandConsoleStart();

	/* Start the task that demonstrates the SSP port being used in SPI mode to
	write to the 7 segment display. */
	vSPIWriteTaskStart();

	/* Start the task that uses an I2C peripheral to communicate with the
	OLED and the EEPROM. */
	vI2CTaskStart();

	/* Register two command line commands to show task stats and run time stats
	respectively. */
	vRegisterCLICommands();

	/* Start the FreeRTOS scheduler. */
	vTaskStartScheduler();

	/* The following line should never execute.  If it does, it means there was
	insufficient FreeRTOS heap memory available to create the Idle and/or timer
	tasks.  See the memory management section on the http://www.FreeRTOS.org web
	site for more information. */
	for( ;; );
}
Exemple #20
0
void sio_init(void)
{
	//LPC_USART_3
	PINSEL_CFG_Type PinSelCfg;
	UART_CFG_Type UartCFG_Struct;
	UART_FIFO_CFG_Type UART_FIFO_CFG_Struct;


	// P4_28
	PinSelCfg.Portnum = PINSEL_PORT_4;
	PinSelCfg.Pinnum = PINSEL_PIN_28;
	PinSelCfg.Funcnum = PINSEL_FUNC_3;
	PinSelCfg.OpenDrain = PINSEL_PINMODE_NORMAL;
	PinSelCfg.Pinmode = PINSEL_PINMODE_PULLUP;
	PINSEL_ConfigPin(&PinSelCfg);
	// P4_29
	PinSelCfg.Pinnum = PINSEL_PIN_29;
	PINSEL_ConfigPin(&PinSelCfg);

	uartDataToSend.currPtr = 0;
	uartDataToSend.lastPtr = 0;
	/* Initialize UART Configuration parameter structure to default state:
	 * Baudrate = 9600bps
	 * 8 data bit
	 * 1 Stop bit
	 * None parity
	*/
	UART_ConfigStructInit(&UartCFG_Struct);

	/* Set Baudrate to 115200 */
	UartCFG_Struct.Baud_rate = 115200;

	/* Initialize UART3 peripheral with given to corresponding parameter */
	UART_Init(SERIAL_USART, &UartCFG_Struct);

	/* Initialize FIFOConfigStruct to default state:
	 * 				- FIFO_DMAMode = DISABLE
	 * 				- FIFO_Level = UART_FIFO_TRGLEV0
	 * 				- FIFO_ResetRxBuf = ENABLE
	 * 				- FIFO_ResetTxBuf = ENABLE
	 * 				- FIFO_State = ENABLE
	 */
	UART_FIFOConfigStructInit(&UART_FIFO_CFG_Struct);

	/* Initialize FIFO for UART3 peripheral */
	UART_FIFOConfig(SERIAL_USART, &UART_FIFO_CFG_Struct);

	/*  Enable UART Transmit */
	UART_TxCmd(SERIAL_USART, ENABLE);

	UART_IntConfig(SERIAL_USART, UART_INTCFG_THRE, ENABLE);

	NVIC_SetPriorityGrouping(UART3_PriorGrup);
	NVIC_SetPriority(UART3_IRQn, UART3_Prior);

	NVIC_EnableIRQ(UART3_IRQn);


}
Exemple #21
0
//------------------------------------------------------------------------------
// Global Functions
void initBasics(void)
{
    /* Enable data and instruction cache and prefetch buffer, set wait states
     * for Flash memory access.
     */
    FLASH->ACR |= FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_PRFTEN
        | FLASH_ACR_LATENCY_1WS;

    /* Set 4 bits for group (equal to preemption) priority and 0 bits for
     * subpriority. Arbitrary choice. Project dependent.
     * Note: use this function provided by core_cm4.h instead of
     * NVIC_PriorityGroupConfig() implemented in misc.c of the SPL because
     * it's safer: the latter only sets the bits using bitwise OR, the former
     * clears the bits first before setting them.
     */
    NVIC_SetPriorityGrouping(NVIC_PriorityGroup_4);

    /* Select HSI as main oscillator. The HSE oscillator isn't populated on
     * the Nucleo board.
     */
    RCC->CR |= ((uint32_t)RCC_CR_HSION); // Enable HSI
    while ((RCC->CR & RCC_CR_HSIRDY) == 0); // Wait until HSI ready

    RCC->CFGR = RCC_CFGR_SW_HSI; // Set HSI as system clock
    while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI);
    // Wait for HSI used as system clock

    /* Configure the HCLK, APB1 and APB2 clock frequency. */
    RCC->CFGR |= RCC_CFGR_HPRE_DIV1; // HCLK = SYSCLK
    RCC->CFGR |= RCC_CFGR_PPRE1_DIV1; // APB1 = HCLK/1
    RCC->CFGR |= RCC_CFGR_PPRE2_DIV1; // APB2 = HCLK/1

    /* Configure and enable the PLL. */
    RCC->CR &= ~RCC_CR_PLLON; // Disable the PLL

    /* PLL configuration: run the CPU at 32MHz;
     * f_VCO = f_HSI*(N/M), f_PLL_out = f_VCO/P
     */
    RCC->PLLCFGR =
        ( 16ul                   | // PLL_M =  16
        (192ul <<  6)            | // PLL_N = 192
        (  2ul << 16)            | // PLL_P =   6
        (RCC_PLLCFGR_PLLSRC_HSI) | // PLL_SRC = HSI
        (  4ul << 24)             ); // PLL_Q = 4

    RCC->CR |= RCC_CR_PLLON; // Enable the PLL
    while((RCC->CR & RCC_CR_PLLRDY) == 0) __NOP(); // Wait until PLL ready

    /* Select the PLL as system clock source. */
    RCC->CFGR &= ~RCC_CFGR_SW;
    RCC->CFGR |= RCC_CFGR_SW_PLL;
    while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL);
    // Wait until PLL is system clock source

    /* Update the global SystemCoreClock variable that stores the core
     * clock frequency in Hertz.
     */
    SystemCoreClockUpdate();
}
Exemple #22
0
// Main Program
int main (void)
{
	PINSEL_CFG_Type PinCfg;

	//  Set Vector table offset value
#if (__RAM_MODE__==1)
	NVIC_SetVTOR(0x10000000);
#else
	NVIC_SetVTOR(0x00000000);
#endif

	//p1.31	, P1.29	and P1.28 are outputs
	FIO_ByteSetDir(1, 3, LED1_MASK, 1);
	FIO_ByteSetDir(2, 0, LED2_MASK, 1);
	// Turn off all LEDs
	FIO_ByteClearValue(1, 3, LED1_MASK);
	FIO_ByteClearValue(2, 0, LED2_MASK);


	//Initialize EXT registers
	LPC_SC->EXTINT = 0x0;
	LPC_SC->EXTMODE = 0x0;
	LPC_SC->EXTPOLAR = 0x0;

	/* edge sensitive */
	LPC_SC->EXTMODE = 0xF;
	/* falling-edge sensitive */
	LPC_SC->EXTPOLAR = 0x0;
	/* External Interrupt Flag cleared*/
	LPC_SC->EXTINT = 0xF;

	/* P2.10 as /EINT0 */
	PinCfg.Funcnum = 1;
	PinCfg.OpenDrain = 0;
	PinCfg.Pinmode = 0;
	PinCfg.Pinnum = 10;
	PinCfg.Portnum = 2;
	PINSEL_ConfigPin(&PinCfg);

	// Enable GPIO interrupt  P0.25/AD0.2
	LPC_GPIOINT->IO0IntEnF	= 0x02000000;

	NVIC_SetPriorityGrouping(4);  //sets PRIGROUP to 3:2 (XXX:YY)
	NVIC_SetPriority(EINT0_IRQn, 0);   //000:00 (bit 7:3) assign eint0 to group 0, sub-priority 0 within group 0
	NVIC_SetPriority(EINT3_IRQn, 4);   //001:00 (bit 7:3) assign GPIO int to group 1, sub-priority 0 within group 1


	NVIC_EnableIRQ(EINT0_IRQn);
	NVIC_EnableIRQ(EINT3_IRQn);

	while (1)
	{
		FIO_ByteSetValue(1, 3, POLL_LED);
		delay();
		FIO_ByteClearValue(1, 3, POLL_LED);
		delay();
	}
}
Exemple #23
0
static void prvSetupHardware( void )
{
	/* Ensure all priority bits are assigned as preemption priority bits.
	http://www.freertos.org/RTOS-Cortex-M3-M4.html */
	NVIC_SetPriorityGrouping( 0 );

	/* TODO: Setup the clocks, etc. here, if they were not configured before
	main() was called. */
}
Exemple #24
0
void DAVE_Init(void)
{
          
    //  NVIC Priority Grouping
    NVIC_SetPriorityGrouping(1);

//****************************************************************************
// @Initialization of APPs Init Functions
//****************************************************************************
	//  MUX configurations
	DAVE_MUX_PreInit(); 
	//  Initialization of app 'CLK001'		     
	CLK001_Init();
	 
	//  Initialization of app 'NVIC_SCU001'		     
	NVIC_SCU001_Init();
	 
	//  Initialization of app 'RTC001'		     
	RTC001_Init();
	 
	//  Initialization of app 'GMM001'		     
	GMM001_Init();
	 
	//  Initialization of app 'SYSTM001'		     
	SYSTM001_Init();
	 
	//  Initialization of app 'USBCORE001'		     
	USBCORE001_Init();
	 
	//  Initialization of app 'UART001'		     
	UART001_Init();
	 
	//  Initialization of app 'CCU4GLOBAL'		     
	CCU4GLOBAL_Init();
	 
	//  Initialization of app 'PWMSP001'		     
	PWMSP001_Init();
	 
	//  Initialization of app 'NVIC002'		     
	NVIC002_Init();
	 
	//  Initialization of app 'I2C001'		     
	I2C001_Init();
	 
	//  Initialization of app 'ERU001'		     
	ERU001_Init();
	 
	//  Initialization of app 'ERU002'		     
	ERU002_Init();
	 
	//  Initialization of app 'IO002'		     
	IO002_Init();
	
      
	//  MUX configurations
	DAVE_MUX_Init();	
} //  End of function DAVE_Init
Exemple #25
0
void init_HW(void)
{
	// RCC system reset(for debug purpose)
	// Set HSION bit
	RCC->CR |= RCC_CR_HSION;
	// Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], ADCPRE[1:0] and MCO[2:0] bits
#ifndef STM32F10X_CL
	RCC->CFGR &= (uint32_t)0xF8FF0000;
#else
	RCC->CFGR &= (uint32_t)0xF0FF0000;
#endif
	// Reset HSEON, CSSON and PLLON bits
	RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
	// Reset HSEBYP bit
	RCC->CR &= ~RCC_CR_HSEBYP;
	// Reset PLLSRC, PLLXTPRE, PLLMUL[3:0] and USBPRE bits
	RCC->CFGR &= (uint32_t)0xFF80FFFF;

#ifdef STM32F10X_CL
	// Reset PLL2ON and PLL3ON bits
	RCC->CR &= (uint32_t)0xEBFFFFFF;

	// Disable all interrupts and clear pending bits
	RCC->CIR = 0x00FF0000;

	// Reset CFGR2 register
	RCC->CFGR2 = 0x00000000;
#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) 
	// Disable all interrupts and clear pending bits
	RCC->CIR = 0x009F0000;

	// Reset CFGR2 register
	RCC->CFGR2 = 0x00000000;      
#else
	// Disable all interrupts and clear pending bits
	RCC->CIR = 0x009F0000;
#endif

	init_clocks();

	// enable IOPx periph
	RCC->APB2ENR |=
			RCC_APB2ENR_IOPAEN |
			RCC_APB2ENR_IOPBEN |
			RCC_APB2ENR_IOPCEN |
			RCC_APB2ENR_IOPDEN |
#ifdef RCC_APB2ENR_IOPEEN
			RCC_APB2ENR_IOPEEN |
#endif
			RCC_APB2ENR_AFIOEN;

//	NVIC_SetPriorityGrouping(7);	// no preemption, 4 bit of subprio
	NVIC_SetPriorityGrouping(6);	// 1 bit preemption, 3 bit of subprio
//	NVIC_SetPriorityGrouping(5);	// 2 bit preemption, 2 bit of subprio
//	NVIC_SetPriorityGrouping(4);	// 3 bit preemption, 1 bit of subprio
//	NVIC_SetPriorityGrouping(3);	// 4 bit preemption, 0 bit of subprio
}
Exemple #26
0
Fichier : arch.c Projet : nqbit/lk
void arch_early_init(void)
{

    arch_disable_ints();

#if     (__CORTEX_M >= 0x03) || (CORTEX_SC >= 300)
    uint i;
    /* set the vector table base */
    SCB->VTOR = (uint32_t)&vectab;

#if ARM_CM_DYNAMIC_PRIORITY_SIZE
    /* number of priorities */
    for (i=0; i < 7; i++) {
        __set_BASEPRI(1 << i);
        if (__get_BASEPRI() != 0)
            break;
    }
    arm_cm_num_irq_pri_bits = 8 - i;
    arm_cm_irq_pri_mask = ~((1 << i) - 1) & 0xff;
#endif

    /* clear any pending interrupts and set all the vectors to medium priority */
    uint groups = (SCnSCB->ICTR & 0xf) + 1;
    for (i = 0; i < groups; i++) {
        NVIC->ICER[i] = 0xffffffff;
        NVIC->ICPR[i] = 0xffffffff;
        for (uint j = 0; j < 32; j++) {
            NVIC_SetPriority(i*32 + j, arm_cm_medium_priority());
        }
    }

    /* leave BASEPRI at 0 */
    __set_BASEPRI(0);

    /* set priority grouping to 0 */
    NVIC_SetPriorityGrouping(0);

    /* enable certain faults */
    SCB->SHCSR |= (SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk);

    /* set the svc and pendsv priority level to pretty low */
#endif
    NVIC_SetPriority(SVCall_IRQn, arm_cm_lowest_priority());
    NVIC_SetPriority(PendSV_IRQn, arm_cm_lowest_priority());

    /* set systick and debugmonitor to medium priority */
    NVIC_SetPriority(SysTick_IRQn, arm_cm_medium_priority());

#if (__CORTEX_M >= 0x03)
    NVIC_SetPriority(DebugMonitor_IRQn, arm_cm_medium_priority());
#endif

#if ARM_WITH_CACHE
    arch_enable_cache(UCACHE);
#endif
}
Exemple #27
0
/**
 * Initialize the system
 *
 * @param  none
 * @return none
 *
 * @brief  Setup the microcontroller system.
 *         Initialize the System.
 */
void SystemInit (void)
{
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
    SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
    SCB->VTOR  = RDA_CODE_BASE;                       /* vector table in flash      */
    NVIC_SetPriorityGrouping(0x06);                   /* 1 bit for pre-emption pri  */

    __enable_irq();
}
Exemple #28
0
void setup_TIM8_DAC_PWM(void) {
    //    	GPIO_InitTypeDef gpio;

    RCC->APB1ENR |= RCC_APB1ENR_DACEN /*| RCC_AHB1ENR_GPIOAEN*/;    // takt fuer dac einschalten
    RCC->APB2ENR |= RCC_APB2ENR_TIM8EN /*| RCC_AHB1ENR_GPIOAEN*/;                         // Takt fuer Timer 8 einschalten
    RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOIEN;  // takt fuer gpiob und gpioi einschalten

//    GPIOI->MODER |= (GPIO_Mode_IN << (2*4)) | (GPIO_Mode_IN << (2*5));
//    GPIOI->OSPEEDR |= (GPIO_High_Speed << (2*4)) | (GPIO_High_Speed << (2*5));
//    GPIOI->OTYPER |= (GPIO_OType_PP << (2*4)) | (GPIO_OType_PP << (2*5));
//	GPIOI->PUPDR |= (GPIO_PuPd_UP << (2*4)) | (GPIO_PuPd_UP << (2*5));

    GPIOB->MODER   |= (GPIO_Mode_AF << (2*0))    | (GPIO_Mode_AF << (2*1));
    GPIOB->OSPEEDR |= (GPIO_High_Speed << (2*0)) | (GPIO_High_Speed << (2*1));
    GPIOB->OTYPER |= (GPIO_OType_PP << (2*0)) | (GPIO_OType_PP << (2*1));
    GPIOB->PUPDR |= (GPIO_PuPd_UP << (2*0)) | (GPIO_PuPd_UP << (2*1));

    GPIOB->AFR[0] |= 0x03 << 0;             // alternate-funtion 3 fuer pin 0
    GPIOB->AFR[0] |= 0x03 << 1*4;           // alternate-funtion 3 fuer pin 1

    // timer enable
    TIM8->CR1 = 0;	                        // Timer disabled
    TIM8->CR2 = 0;	                        // Timer disabled
    TIM8->PSC = 0;                          // Prescaler
    TIM8->ARR = N_ARR;                      // Auto reload register
    TIM8->DIER = TIM_DIER_UIE;              // Interrupt einschalten
    TIM8->CR1 = TIM_CR1_CEN | TIM_CR1_ARPE; // Enable Timer(Counter Enable) , enable preload

    //Enable PWM
    TIM8->CCMR1 |= TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2PE; //Channel 2
    TIM8->CCMR2 |= TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3PE; //Channel 3
    TIM8->CCER |= TIM_CCER_CC3NE | TIM_CCER_CC2NE;
    TIM8->BDTR = TIM_BDTR_MOE;
    //TIM8->CR1 = TIM_CR1_CEN | TIM_CR1_ARPE; // Enable Timer, enable preload

    NVIC_SetPriorityGrouping(2);
    NVIC_SetPriority(TIM8_UP_TIM13_IRQn, 8);
    NVIC_EnableIRQ(TIM8_UP_TIM13_IRQn);

    TIM8->CCR2 = 0;                         // default value
    TIM8->CCR3 = 0;	                        // default value



//    GPIOA->MODER = (GPIOA->MODER & ~(3u << (4 * 2))) | (GPIO_Mode_AIN << (4 * 2));
//    GPIOA->MODER = (GPIOA->MODER & ~(3u << (5 * 2))) | (GPIO_Mode_AIN << (5 * 2));
//    GPIOA->OSPEEDR |= (GPIO_High_Speed << (2*4)) | (GPIO_High_Speed << (2*5));
//    GPIOA->OTYPER |= (GPIO_OType_PP << (2*4)) | (GPIO_OType_PP << (2*5));
//	GPIOA->PUPDR |= (GPIO_PuPd_UP << (2*4)) | (GPIO_PuPd_UP << (2*5));

    //DAC_START
    DAC->CR = 0;
    DAC->CR = DAC_CR_EN1 | DAC_CR_EN2;
}
Exemple #29
0
void initScmRTOS(void)
{
#if defined (STM32F40_41xxx) || defined (STM32F427_437xx) || defined (STM32F429_439xx) || defined (STM32F401xx) || defined (STM32F411xE)

	// enable GPIOx peripherals
	RCC->AHB1ENR |=
			0
			| RCC_AHB1ENR_GPIOAEN
			| RCC_AHB1ENR_GPIOBEN
			| RCC_AHB1ENR_GPIOCEN
			| RCC_AHB1ENR_GPIODEN
			| RCC_AHB1ENR_GPIOEEN
			| RCC_AHB1ENR_GPIOFEN
			| RCC_AHB1ENR_GPIOGEN
			| RCC_AHB1ENR_GPIOHEN
			| RCC_AHB1ENR_GPIOIEN
			;
#else
  // enable IOPx periph
  RCC->APB2ENR |=
    RCC_APB2ENR_IOPAEN |
    RCC_APB2ENR_IOPBEN |
    RCC_APB2ENR_IOPCEN |
    RCC_APB2ENR_IOPDEN |
#ifdef RCC_APB2ENR_IOPEEN
    RCC_APB2ENR_IOPEEN |
#endif
    RCC_APB2ENR_AFIOEN;

#endif

  // Настраиваем приоритеты прерываний.
  // 15- самый низкий приоритет.
  // 0 - самый высокий приоритет.
  //
  // PRIGROUP
  // 0x7 - оброботчик прерывания может быть прерван любым более приоритетным прерыванием.
  // 0x6 - оброботчик прерывания может быть прерван другим прерыванием, более приоритетным из
  //          другой группы. (0-7 первая группа, 8-16 вторая группа)
  // 0x3 - каждый обработчик прерывания может быть прерван другим, более приоритетным, прерыванием.
  //
  //    PRIGROUP      группы (с вытеснением)      подгруппы
  //       0x3                 16                  0
  //       0x4                  8                  2
  //       0x5                  4                  4
  //       0x6                  2                  8
  //       0x7                  0                 16

  //	NVIC_SetPriorityGrouping(7);	// no preemption, 4 bit of subprio
  // NVIC_SetPriorityGrouping(6);	// 1 bit preemption, 3 bit of subprio
  NVIC_SetPriorityGrouping(5);	// 2 bit preemption, 2 bit of subprio
  //	NVIC_SetPriorityGrouping(4);	// 3 bit preemption, 1 bit of subprio
  //	NVIC_SetPriorityGrouping(3);	// 4 bit preemption, 0 bit of subprio
}
/**
 * \brief Configure the hardware.
 */
static void prvSetupHardware(void)
{
	/* ASF function to setup clocking. */
	sysclk_init();

	/* Ensure all priority bits are assigned as preemption priority bits. */
	NVIC_SetPriorityGrouping(__NVIC_PRIO_BITS);

	/* Atmel library function to setup for the evaluation kit being used. */
	board_init();
}