Exemple #1
0
/* Set bit in Function Disble register to hide this device */
static void pch_hide_devfn(unsigned devfn)
{
	switch (devfn) {
	case PCI_DEVFN(22, 0): /* MEI #1 */
		RCBA32_OR(FD2, PCH_DISABLE_MEI1);
		break;
	case PCI_DEVFN(22, 1): /* MEI #2 */
		RCBA32_OR(FD2, PCH_DISABLE_MEI2);
		break;
	case PCI_DEVFN(22, 2): /* IDE-R */
		RCBA32_OR(FD2, PCH_DISABLE_IDER);
		break;
	case PCI_DEVFN(22, 3): /* KT */
		RCBA32_OR(FD2, PCH_DISABLE_KT);
		break;
	case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */
	case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */
	case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */
	case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */
		RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(devfn)));
		break;
	case PCI_DEVFN(29, 0): /* EHCI #1 */
		RCBA32_OR(FD, PCH_DISABLE_EHCI1);
		break;
	case PCI_DEVFN(31, 0): /* LPC */
		RCBA32_OR(FD, PCH_DISABLE_LPC);
		break;
	case PCI_DEVFN(31, 2): /* SATA #1 */
		RCBA32_OR(FD, PCH_DISABLE_SATA1);
		break;
	case PCI_DEVFN(31, 3): /* SMBUS */
		RCBA32_OR(FD, PCH_DISABLE_SMBUS);
		break;
	case PCI_DEVFN(31, 5): /* SATA #2 */
		RCBA32_OR(FD, PCH_DISABLE_SATA2);
		break;
	case PCI_DEVFN(31, 6): /* Thermal Subsystem */
		RCBA32_OR(FD, PCH_DISABLE_THERMAL);
		break;
	case PCI_DEVFN(31, 7): /* Watch Dog*/
		/* No disable defined in datasheet */
		break;
	}
}
Exemple #2
0
/* Set bit in Function Disble register to hide this device */
void pch_disable_devfn(device_t dev)
{
    switch (dev->path.pci.devfn) {
    case PCI_DEVFN(19, 0): /* Audio DSP */
        RCBA32_OR(FD, PCH_DISABLE_ADSPD);
        break;
    case PCI_DEVFN(20, 0): /* XHCI */
        RCBA32_OR(FD, PCH_DISABLE_XHCI);
        break;
    case PCI_DEVFN(21, 0): /* DMA */
        pch_enable_d3hot(dev);
        pch_iobp_update(SIO_IOBP_FUNCDIS0, ~0UL, SIO_IOBP_FUNCDIS_DIS);
        break;
    case PCI_DEVFN(21, 1): /* I2C0 */
        pch_enable_d3hot(dev);
        pch_iobp_update(SIO_IOBP_FUNCDIS1, ~0UL, SIO_IOBP_FUNCDIS_DIS);
        break;
    case PCI_DEVFN(21, 2): /* I2C1 */
        pch_enable_d3hot(dev);
        pch_iobp_update(SIO_IOBP_FUNCDIS2, ~0UL, SIO_IOBP_FUNCDIS_DIS);
        break;
    case PCI_DEVFN(21, 3): /* SPI0 */
        pch_enable_d3hot(dev);
        pch_iobp_update(SIO_IOBP_FUNCDIS3, ~0UL, SIO_IOBP_FUNCDIS_DIS);
        break;
    case PCI_DEVFN(21, 4): /* SPI1 */
        pch_enable_d3hot(dev);
        pch_iobp_update(SIO_IOBP_FUNCDIS4, ~0UL, SIO_IOBP_FUNCDIS_DIS);
        break;
    case PCI_DEVFN(21, 5): /* UART0 */
        pch_enable_d3hot(dev);
        pch_iobp_update(SIO_IOBP_FUNCDIS5, ~0UL, SIO_IOBP_FUNCDIS_DIS);
        break;
    case PCI_DEVFN(21, 6): /* UART1 */
        pch_enable_d3hot(dev);
        pch_iobp_update(SIO_IOBP_FUNCDIS6, ~0UL, SIO_IOBP_FUNCDIS_DIS);
        break;
    case PCI_DEVFN(22, 0): /* MEI #1 */
        RCBA32_OR(FD2, PCH_DISABLE_MEI1);
        break;
    case PCI_DEVFN(22, 1): /* MEI #2 */
        RCBA32_OR(FD2, PCH_DISABLE_MEI2);
        break;
    case PCI_DEVFN(22, 2): /* IDE-R */
        RCBA32_OR(FD2, PCH_DISABLE_IDER);
        break;
    case PCI_DEVFN(22, 3): /* KT */
        RCBA32_OR(FD2, PCH_DISABLE_KT);
        break;
    case PCI_DEVFN(23, 0): /* SDIO */
        pch_enable_d3hot(dev);
        pch_iobp_update(SIO_IOBP_FUNCDIS7, ~0UL, SIO_IOBP_FUNCDIS_DIS);
        break;
    case PCI_DEVFN(25, 0): /* Gigabit Ethernet */
        RCBA32_OR(BUC, PCH_DISABLE_GBE);
        break;
    case PCI_DEVFN(26, 0): /* EHCI #2 */
        RCBA32_OR(FD, PCH_DISABLE_EHCI2);
        break;
    case PCI_DEVFN(27, 0): /* HD Audio Controller */
        RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO);
        break;
    case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */
    case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */
    case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */
    case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */
    case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */
    case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */
    case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */
    case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */
        RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(dev->path.pci.devfn)));
        break;
    case PCI_DEVFN(29, 0): /* EHCI #1 */
        RCBA32_OR(FD, PCH_DISABLE_EHCI1);
        break;
    case PCI_DEVFN(31, 0): /* LPC */
        RCBA32_OR(FD, PCH_DISABLE_LPC);
        break;
    case PCI_DEVFN(31, 2): /* SATA #1 */
        RCBA32_OR(FD, PCH_DISABLE_SATA1);
        break;
    case PCI_DEVFN(31, 3): /* SMBUS */
        RCBA32_OR(FD, PCH_DISABLE_SMBUS);
        break;
    case PCI_DEVFN(31, 5): /* SATA #2 */
        RCBA32_OR(FD, PCH_DISABLE_SATA2);
        break;
    case PCI_DEVFN(31, 6): /* Thermal Subsystem */
        RCBA32_OR(FD, PCH_DISABLE_THERMAL);
        break;
    }
}
Exemple #3
0
/* Set bit in Function Disable register to hide this device */
void pch_disable_devfn(device_t dev)
{
	switch (dev->path.pci.devfn) {
	case PCH_DEVFN_ADSP: /* Audio DSP */
		rcba_function_disable(FD, PCH_DISABLE_ADSPD);
		break;
	case PCH_DEVFN_XHCI: /* XHCI */
		rcba_function_disable(FD, PCH_DISABLE_XHCI);
		break;
	case PCH_DEVFN_SDMA: /* DMA */
		pch_enable_d3hot(dev);
		pch_iobp_update(SIO_IOBP_FUNCDIS0, ~0UL, SIO_IOBP_FUNCDIS_DIS);
		break;
	case PCH_DEVFN_I2C0: /* I2C0 */
		pch_enable_d3hot(dev);
		pch_iobp_update(SIO_IOBP_FUNCDIS1, ~0UL, SIO_IOBP_FUNCDIS_DIS);
		break;
	case PCH_DEVFN_I2C1: /* I2C1 */
		pch_enable_d3hot(dev);
		pch_iobp_update(SIO_IOBP_FUNCDIS2, ~0UL, SIO_IOBP_FUNCDIS_DIS);
		break;
	case PCH_DEVFN_SPI0: /* SPI0 */
		pch_enable_d3hot(dev);
		pch_iobp_update(SIO_IOBP_FUNCDIS3, ~0UL, SIO_IOBP_FUNCDIS_DIS);
		break;
	case PCH_DEVFN_SPI1: /* SPI1 */
		pch_enable_d3hot(dev);
		pch_iobp_update(SIO_IOBP_FUNCDIS4, ~0UL, SIO_IOBP_FUNCDIS_DIS);
		break;
	case PCH_DEVFN_UART0: /* UART0 */
		pch_enable_d3hot(dev);
		pch_iobp_update(SIO_IOBP_FUNCDIS5, ~0UL, SIO_IOBP_FUNCDIS_DIS);
		break;
	case PCH_DEVFN_UART1: /* UART1 */
		pch_enable_d3hot(dev);
		pch_iobp_update(SIO_IOBP_FUNCDIS6, ~0UL, SIO_IOBP_FUNCDIS_DIS);
		break;
	case PCH_DEVFN_ME: /* MEI #1 */
		rcba_function_disable(FD2, PCH_DISABLE_MEI1);
		break;
	case PCH_DEVFN_ME_2: /* MEI #2 */
		rcba_function_disable(FD2, PCH_DISABLE_MEI2);
		break;
	case PCH_DEVFN_ME_IDER: /* IDE-R */
		rcba_function_disable(FD2, PCH_DISABLE_IDER);
		break;
	case PCH_DEVFN_ME_KT: /* KT */
		rcba_function_disable(FD2, PCH_DISABLE_KT);
		break;
	case PCH_DEVFN_SDIO: /* SDIO */
		pch_enable_d3hot(dev);
		pch_iobp_update(SIO_IOBP_FUNCDIS7, ~0UL, SIO_IOBP_FUNCDIS_DIS);
		break;
	case PCH_DEVFN_GBE: /* Gigabit Ethernet */
		rcba_function_disable(BUC, PCH_DISABLE_GBE);
		break;
	case PCH_DEVFN_HDA: /* HD Audio Controller */
		rcba_function_disable(FD, PCH_DISABLE_HD_AUDIO);
		break;
	case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 0): /* PCI Express Root Port 1 */
	case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 1): /* PCI Express Root Port 2 */
	case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 2): /* PCI Express Root Port 3 */
	case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 3): /* PCI Express Root Port 4 */
	case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 4): /* PCI Express Root Port 5 */
	case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 5): /* PCI Express Root Port 6 */
	case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 6): /* PCI Express Root Port 7 */
	case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 7): /* PCI Express Root Port 8 */
		rcba_function_disable(FD,
			PCH_DISABLE_PCIE(PCI_FUNC(dev->path.pci.devfn)));
		break;
	case PCH_DEVFN_EHCI: /* EHCI #1 */
		rcba_function_disable(FD, PCH_DISABLE_EHCI1);
		break;
	case PCH_DEVFN_LPC: /* LPC */
		rcba_function_disable(FD, PCH_DISABLE_LPC);
		break;
	case PCH_DEVFN_SATA: /* SATA #1 */
		rcba_function_disable(FD, PCH_DISABLE_SATA1);
		break;
	case PCH_DEVFN_SMBUS: /* SMBUS */
		rcba_function_disable(FD, PCH_DISABLE_SMBUS);
		break;
	case PCH_DEVFN_SATA2: /* SATA #2 */
		rcba_function_disable(FD, PCH_DISABLE_SATA2);
		break;
	case PCH_DEVFN_THERMAL: /* Thermal Subsystem */
		rcba_function_disable(FD, PCH_DISABLE_THERMAL);
		break;
	}
}