int _i8259_init(struct device *unused)
{
ARG_UNUSED(unused);
sys_out8(PIC_DISABLE, PIC_PORT2(PIC_SLAVE_BASE_ADRS));
sys_out8(PIC_DISABLE, PIC_PORT2(PIC_MASTER_BASE_ADRS));
return 0;
}
void _i8259_init(void)
{
/*
* Initialize the Master PIC device.
*
* Whenever a command is issued with A0=0 and D4=1, this is interpreted
* as Initialization Command Word 1 (ICW1).
* D0 = 1 (ICW4 required)
* D1 = 0 (Cascaded PIC configuration)
* D2 = X (ADI: only used in MCS-80/85 mode)
* D3 = 0 (level triggered interrupt mode: edge triggered)
* D4 = 1 (initiates initialization sequence: see above)
* D5 -> D7 = X (only used in MCS-80/85 mode)
*/
PLB_BYTE_REG_WRITE(0x11, PIC_PORT1(PIC_MASTER_BASE_ADRS));
/*
* ICW2 = upper 5 bits of vector presented by 8259 during /INTA cycle
*/
PLB_BYTE_REG_WRITE(INT_VEC_IRQ0, PIC_PORT2(PIC_MASTER_BASE_ADRS));
/*
* ICW3 (Master): indicate which IRQ has slave connection. On PC
* systems
* the slave PIC is connect to IRQ2.
*/
PLB_BYTE_REG_WRITE(0x04, PIC_PORT2(PIC_MASTER_BASE_ADRS));
/*
* ICW4
* D0 = 1 (Mode: 0=8085, 1=8086)
* D1 = 0 (AEOI: 1=Auto End of Interrupt, 0=Normal)
* D2 = X (Master/Slave in buffered mode: 1=Master, 0=Slave)
* D3 = 0 (Buffer mode: 0 = non-buffered mode)
* D4 = 0 (SFNM: 1= Special fully nested mode)
*/
PLB_BYTE_REG_WRITE(0x01, PIC_PORT2(PIC_MASTER_BASE_ADRS));
/*
* Initialize the Slave PIC device.
*/
PLB_BYTE_REG_WRITE(0x11, PIC_PORT1(PIC_SLAVE_BASE_ADRS)); /* ICW1 */
PLB_BYTE_REG_WRITE(INT_VEC_IRQ0 + 8, PIC_PORT2(PIC_SLAVE_BASE_ADRS));
PLB_BYTE_REG_WRITE(0x02, PIC_PORT2(PIC_SLAVE_BASE_ADRS)); /* ICW3 */
PLB_BYTE_REG_WRITE(0x01, PIC_PORT2(PIC_SLAVE_BASE_ADRS)); /* ICW4 */
/* disable interrupts */
PLB_BYTE_REG_WRITE(0xfb, PIC_IMASK(PIC_MASTER_BASE_ADRS));
PLB_BYTE_REG_WRITE(0xff, PIC_IMASK(PIC_SLAVE_BASE_ADRS));
}