static INT rtmp_bbp_set_mmps(struct _RTMP_ADAPTER *pAd, BOOLEAN ReduceCorePower) { UCHAR bbp_val, org_val; RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &org_val); bbp_val = org_val; if (ReduceCorePower) bbp_val |= 0x04; else bbp_val &= ~0x04; if (bbp_val != org_val) RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, bbp_val); #ifdef RT6352 if (IS_RT6352(pAd)) { RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R95, &org_val); bbp_val = org_val; if (ReduceCorePower) { bbp_val &= ~(0x80); /* bit 7 */ } else { if (pAd->Antenna.field.RxPath > 1) bbp_val |= 0x80; } if (bbp_val != org_val) RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R95, bbp_val); } #endif /* RT6352*/ return TRUE; }
static INT rtmp_bbp_init(RTMP_ADAPTER *pAd) { INT Index = 0; /* Read BBP register, make sure BBP is up and running before write new data*/ if (rtmp_bbp_is_ready(pAd)== FALSE) return FALSE; Index = 0; /* Initialize BBP register to default value*/ for (Index = 0; Index < NUM_BBP_REG_PARMS; Index++) { #ifdef MICROWAVE_OVEN_SUPPORT #endif /* MICROWAVE_OVEN_SUPPORT */ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBPRegTable[Index].Register, BBPRegTable[Index].Value); } /* re-config specific BBP registers for individual chip */ if (pAd->chipCap.pBBPRegTable) { REG_PAIR *reg_list = pAd->chipCap.pBBPRegTable; for (Index = 0; Index < pAd->chipCap.bbpRegTbSize; Index++) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, reg_list[Index].Register, reg_list[Index].Value); DBGPRINT(RT_DEBUG_TRACE, ("BBP_R%d=0x%x\n", reg_list[Index].Register, reg_list[Index].Value)); } } if (pAd->chipOps.AsicBbpInit != NULL) pAd->chipOps.AsicBbpInit(pAd); /* For rt2860E and after, init BBP_R84 with 0x19. This is for extension channel overlapping IOT. RT3090 should not program BBP R84 to 0x19, otherwise TX will block. 3070/71/72,3090,3090A( are included in RT30xx),3572,3390 */ if (((pAd->MACVersion & 0xffff) != 0x0101) && !(IS_RT30xx(pAd)|| IS_RT3572(pAd) || IS_RT5390(pAd) || IS_RT5392(pAd) || IS_RT3290(pAd) || IS_MT7601(pAd) || IS_RT6352(pAd) || IS_MT76x2(pAd))) RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R84, 0x19); if (pAd->MACVersion == 0x28600100) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x16); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x12); } return TRUE; }
/* Sometimes frequency will be shift we need to adjust it when the frequencey shift. */ VOID InitFrequencyCalibrationMode(PRTMP_ADAPTER pAd, UINT8 Mode) { BBP_R179_STRUC BbpR179 = { {0} }; BBP_R180_STRUC BbpR180 = { {0} }; BBP_R182_STRUC BbpR182 = { {0} }; // TODO: shiang-6590, fix me, I don't know which MODE0 yet for RT85592 if (Mode == FREQ_CAL_INIT_MODE0) { /* Initialize the RX_END_STATUS (1, 5) for "Rx OFDM/CCK frequency offset report" */ BbpR179.field.DataIndex1 = 1; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R179, BbpR179.byte); BbpR180.field.DataIndex2 = 5; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R180, BbpR180.byte); BbpR182.field.DataArray = BBP_R57; /* Rx OFDM/CCK frequency offset report */ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R182, BbpR182.byte); } else if (Mode == FREQ_CAL_INIT_MODE1) { /* Initialize the RX_END_STATUS (1, 3) for "Rx OFDM/CCK frequency offset report" */ BbpR179.field.DataIndex1 = 1; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R179, BbpR179.byte); BbpR180.field.DataIndex2 = 3; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R180, BbpR180.byte); BbpR182.field.DataArray = BBP_R57; /* Rx OFDM/CCK frequency offset report */ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R182, BbpR182.byte); } else if (Mode == FREQ_CAL_INIT_MODE2) { /* Initialize the RX_END_STATUS (1) for "Rx OFDM/CCK frequency offset report" */ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R142, 1); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R143, BBP_R57); /* Rx OFDM/CCK frequency offset report */ } else DBGPRINT(RT_DEBUG_ERROR, ("%s:Unknow mode = %d\n", __FUNCTION__, Mode)); }
VOID RT35xx_NICInitAsicFromEEPROM( IN PRTMP_ADAPTER pAd) { UCHAR bbpreg = 0; UCHAR RFValue = 0; if (IS_RT3572(pAd)) { /* enable DC filter*/ if ((pAd->MACVersion & 0xffff) >= 0x0201) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R103, 0xc0); } /* improve power consumption */ RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R138, &bbpreg); if (pAd->Antenna.field.TxPath == 1) { /* turn off tx DAC_1 */ bbpreg = (bbpreg | 0x20); } if (pAd->Antenna.field.RxPath == 1) { /* turn off tx ADC_1*/ bbpreg &= (~0x2); } RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R138, bbpreg); if ((pAd->MACVersion & 0xffff) >= 0x0211) { RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R31, &bbpreg); bbpreg &= (~0x3); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R31, bbpreg); } /* TX_LO1_en*/ RT30xxReadRFRegister(pAd, RF_R16, &RFValue); /* set RF_R16_bit[2:0] equal to EEPROM setting at 0x48h and the value should start from 2.*/ /*if (pAd->TxMixerGain24G >= 2)*/ { RFValue &= (~0x7); /* clean bit [2:0]*/ RFValue |= pAd->TxMixerGain24G; } RT30xxWriteRFRegister(pAd, RF_R16, RFValue); } }
static INT rtmp_bbp_set_ctrlch(struct _RTMP_ADAPTER *pAd, UINT8 ext_ch) { UCHAR val, old_val = 0; RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &old_val); val = old_val; switch (ext_ch) { case EXTCHA_BELOW: val |= (0x20); break; case EXTCHA_ABOVE: case EXTCHA_NONE: val &= (~0x20); break; } if (val != old_val) RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, val); #ifdef CONFIG_STA_SUPPORT #ifdef RTMP_MAC_PCI IF_DEV_CONFIG_OPMODE_ON_STA(pAd) { pAd->StaCfg.BBPR3 = val; } #endif /* RTMP_MAC_PCI */ #endif /* CONFIG_STA_SUPPORT */ return TRUE; }
static INT rtmp_bbp_set_txdac(struct _RTMP_ADAPTER *pAd, INT tx_dac) { UCHAR val, old_val = 0; RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R1, &old_val); val = old_val & (~0x18); switch (tx_dac) { case 2: val |= 0x10; break; case 1: val |= 0x08; break; case 0: default: break; } if (val != old_val) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R1, val); } return TRUE; }
VOID BeaconTimeout( IN PVOID SystemSpecific1, IN PVOID FunctionContext, IN PVOID SystemSpecific2, IN PVOID SystemSpecific3) { RTMP_ADAPTER *pAd = (RTMP_ADAPTER *)FunctionContext; DBGPRINT(RT_DEBUG_TRACE,("SYNC - BeaconTimeout\n")); if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS)) return; #ifdef DOT11_N_SUPPORT if ((pAd->CommonCfg.BBPCurrentBW == BW_40) ) { UCHAR BBPValue = 0; AsicSwitchChannel(pAd, pAd->CommonCfg.CentralChannel, FALSE); AsicLockChannel(pAd, pAd->CommonCfg.CentralChannel); RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue); BBPValue &= (~0x18); BBPValue |= 0x10; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue); DBGPRINT(RT_DEBUG_TRACE, ("SYNC - End of SCAN, restore to 40MHz channel %d, Total BSS[%02d]\n",pAd->CommonCfg.CentralChannel, pAd->ScanTab.BssNr)); } #endif MlmeEnqueue(pAd, SYNC_STATE_MACHINE, MT2_BEACON_TIMEOUT, 0, NULL); RTMP_MLME_HANDLER(pAd); }
INT rtmp_bbp_set_ctrlch(struct _RTMP_ADAPTER *pAd, INT ext_ch) { UCHAR val, old_val = 0; RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &old_val); val = old_val; switch (ext_ch) { case EXTCHA_BELOW: val |= (0x20); break; case EXTCHA_ABOVE: case EXTCHA_NONE: val &= (~0x20); break; } if (val != old_val) RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, val); #ifdef CONFIG_STA_SUPPORT #endif /* CONFIG_STA_SUPPORT */ return TRUE; }
/* ======================================================================== Routine Description: Periodic evaluate antenna link status Arguments: pAd - Adapter pointer Return Value: None ======================================================================== */ VOID APAsicEvaluateRxAnt( IN PRTMP_ADAPTER pAd) { UCHAR BBPR3 = 0; ULONG TxTotalCnt; #ifdef RALINK_ATE if (ATE_ON(pAd)) return; #endif /* RALINK_ATE */ #ifdef CARRIER_DETECTION_SUPPORT if(pAd->CommonCfg.CarrierDetect.CD_State == CD_SILENCE) return; #endif /* CARRIER_DETECTION_SUPPORT */ RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BBPR3); BBPR3 &= (~0x18); if((pAd->Antenna.field.RxPath == 3) #ifdef DOT11_N_SUPPORT #ifdef GREENAP_SUPPORT && (pAd->ApCfg.bGreenAPActive == FALSE) #endif /* GREENAP_SUPPORT */ #endif /* DOT11_N_SUPPORT */ ) { BBPR3 |= (0x10); } else if((pAd->Antenna.field.RxPath == 2) #ifdef DOT11_N_SUPPORT #ifdef GREENAP_SUPPORT && (pAd->ApCfg.bGreenAPActive == FALSE) #endif /* GREENAP_SUPPORT */ #endif /* DOT11_N_SUPPORT */ ) { BBPR3 |= (0x8); } else if(pAd->Antenna.field.RxPath == 1) { BBPR3 |= (0x0); } RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BBPR3); TxTotalCnt = pAd->RalinkCounters.OneSecTxNoRetryOkCount + pAd->RalinkCounters.OneSecTxRetryOkCount + pAd->RalinkCounters.OneSecTxFailCount; if (TxTotalCnt > 50) { RTMPSetTimer(&pAd->Mlme.RxAntEvalTimer, 20); pAd->Mlme.bLowThroughput = FALSE; } else { RTMPSetTimer(&pAd->Mlme.RxAntEvalTimer, 300); pAd->Mlme.bLowThroughput = TRUE; } }
static INT rtmp_bbp_set_rxpath(struct _RTMP_ADAPTER *pAd, INT rxpath) { UCHAR val = 0; RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &val); val &= (~0x18); if(rxpath == 3) val |= (0x10); else if(rxpath == 2) val |= (0x8); else if(rxpath == 1) val |= (0x0); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, val); #ifdef CONFIG_STA_SUPPORT #ifdef RTMP_MAC_PCI IF_DEV_CONFIG_OPMODE_ON_STA(pAd) { pAd->StaCfg.BBPR3 = val; } #endif /* RTMP_MAC_PCI */ #endif /* CONFIG_STA_SUPPORT */ return TRUE; }
/* add by johnli, RF power sequence setup ========================================================================== Description: Load RF normal operation-mode setup ========================================================================== */ VOID RT30xxLoadRFNormalModeSetup( IN PRTMP_ADAPTER pAd) { UCHAR RFValue, bbpreg = 0; { /* improve power consumption */ RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R138, &bbpreg); if (pAd->Antenna.field.TxPath == 1) { /* turn off tx DAC_1*/ bbpreg = (bbpreg | 0x20); } if (pAd->Antenna.field.RxPath == 1) { /* turn off tx ADC_1*/ bbpreg &= (~0x2); } RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R138, bbpreg); } /*RX0_PD & TX0_PD, RF R1 register Bit 2 & Bit 3 to 0 and RF_BLOCK_en,RX1_PD & TX1_PD, Bit0, Bit 4 & Bit5 to 1*/ RT30xxReadRFRegister(pAd, RF_R01, &RFValue); RFValue = (RFValue & (~0x0C)) | 0x31; RT30xxWriteRFRegister(pAd, RF_R01, RFValue); /* TX_LO2_en, RF R15 register Bit 3 to 0*/ RT30xxReadRFRegister(pAd, RF_R15, &RFValue); RFValue &= (~0x08); RT30xxWriteRFRegister(pAd, RF_R15, RFValue); /* TX_LO1_en, RF R17 register Bit 3 to 0*/ RT30xxReadRFRegister(pAd, RF_R17, &RFValue); RFValue &= (~0x08); /* to fix rx long range issue*/ if (((pAd->MACVersion & 0xffff) >= 0x0211) && (pAd->NicConfig2.field.ExternalLNAForG == 0)) { RFValue |= 0x20; } /* set RF_R17_bit[2:0] equal to EEPROM setting at 0x48h*/ if (pAd->TxMixerGain24G >= 2) { RFValue &= (~0x7); /* clean bit [2:0]*/ RFValue |= pAd->TxMixerGain24G; } RT30xxWriteRFRegister(pAd, RF_R17, RFValue); /* RX_LO1_en, RF R20 register Bit 3 to 0*/ RT30xxReadRFRegister(pAd, RF_R20, &RFValue); RFValue &= (~0x08); RT30xxWriteRFRegister(pAd, RF_R20, RFValue); /* RX_LO2_en, RF R21 register Bit 3 to 0*/ RT30xxReadRFRegister(pAd, RF_R21, &RFValue); RFValue &= (~0x08); RT30xxWriteRFRegister(pAd, RF_R21, RFValue); }
static INT rtmp_bbp_set_bw(struct _RTMP_ADAPTER *pAd, UINT8 bw) { UCHAR val, old_val = 0; BOOLEAN bstop = FALSE; UINT32 Data, MTxCycle, macStatus; if (bw != pAd->CommonCfg.BBPCurrentBW) bstop = TRUE; if (bstop) { /* Disable MAC Tx/Rx */ RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Data); Data &= (~0x0C); RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Data); /* Check MAC Tx/Rx idle */ for (MTxCycle = 0; MTxCycle < 10000; MTxCycle++) { RTMP_IO_READ32(pAd, MAC_STATUS_CFG, &macStatus); if (macStatus & 0x3) RtmpusecDelay(50); else break; } } RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &old_val); val = (old_val & (~0x18)); switch (bw) { case BW_20: val &= (~0x18); break; case BW_40: val |= (0x10); break; case BW_10: val |= 0x08; break; } if (val != old_val) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, val); } if (bstop) { /* Enable MAC Tx/Rx */ RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Data); Data |= 0x0C; RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Data); } pAd->CommonCfg.BBPCurrentBW = bw; return TRUE; }
VOID InitFrequencyCalibration( IN PRTMP_ADAPTER pAd) { BBP_R179_STRUC BbpR179 = {{0}}; BBP_R180_STRUC BbpR180 = {{0}}; BBP_R182_STRUC BbpR182 = {{0}}; if (pAd->FreqCalibrationCtrl.bEnableFrequencyCalibration == TRUE) { DBGPRINT(RT_DEBUG_TRACE, ("---> %s\n", __FUNCTION__)); /* Initialize the RX_END_STATUS (1) for "Rx OFDM/CCK frequency offset report"*/ if (IS_RT5390(pAd)) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R142, 1); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R143, BBP_R57); /* Rx OFDM/CCK frequency offset report*/ } else if (IS_RT3390(pAd)) { /* Initialize the RX_END_STATUS (1, 5) for "Rx OFDM/CCK frequency offset report"*/ BbpR179.field.DataIndex1 = 1; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R179, BbpR179.byte); BbpR180.field.DataIndex2 = 5; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R180, BbpR180.byte); BbpR182.field.DataArray = BBP_R57; /* Rx OFDM/CCK frequency offset report*/ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R182, BbpR182.byte); } else { DBGPRINT(RT_DEBUG_ERROR, ("%s: Not support IC type (MACVersion = 0x%X)\n", __FUNCTION__, pAd->MACVersion)); } StopFrequencyCalibration(pAd); DBGPRINT(RT_DEBUG_TRACE, ("%s: frequency offset in the EEPROM = %ld\n", __FUNCTION__, pAd->RfFreqOffset)); DBGPRINT(RT_DEBUG_TRACE, ("<--- %s\n", __FUNCTION__)); } }
static VOID P2PDiscListenAction( IN PRTMP_ADAPTER pAd, IN MLME_QUEUE_ELEM *Elem) { P2P_DISC_STATE *pCurrState = &(pAd->P2pCfg.DiscCurrentState); PRT_P2P_CONFIG pP2PCtrl = &pAd->P2pCfg; if (pP2PCtrl->P2pCounter.bStartScan == TRUE) pP2PCtrl->P2pCounter.ListenInterval = (RandomByte(pAd) % 3) + pP2PCtrl->P2pCounter.ListenIntervalBias; /* 1~3 */ else pP2PCtrl->P2pCounter.ListenInterval = 5; /* ExtListenInterval is in ms. So /100 */ if (IS_P2P_SUPPORT_EXT_LISTEN(pAd)) pP2PCtrl->P2pCounter.ListenInterval = pP2PCtrl->ExtListenPeriod/100; if (pAd->LatchRfRegs.Channel != pP2PCtrl->ListenChannel) { UINT32 Data = 0, macStatus; UINT32 MTxCycle, MRxCycle; UCHAR BBPValue = 0; /* Disable MAC Tx/Rx */ RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Data); Data &= (~0x0C); RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Data); /* Check MAC Tx/Rx idle */ for (MTxCycle = 0; MTxCycle < 10000; MTxCycle++) { RTMP_IO_READ32(pAd, MAC_STATUS_CFG, &macStatus); if (macStatus & 0x3) RTMPusecDelay(50); else break; } AsicSwitchChannel(pAd, pP2PCtrl->ListenChannel, FALSE); AsicLockChannel(pAd, pP2PCtrl->ListenChannel); /* Let BBP register at 20MHz */ RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue); BBPValue &= (~0x18); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue); /* Enable MAC Tx/Rx */ RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Data); Data |= 0x0C; RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Data); } DBGPRINT(RT_DEBUG_TRACE, ("%s:: Listen interval - %d\n", __FUNCTION__, pP2PCtrl->P2pCounter.ListenInterval)); pP2PCtrl->P2pCounter.bListen = TRUE; *pCurrState = P2P_DISC_LISTEN; }
static NDIS_STATUS AsicBBPWriteWithRxChain( IN RTMP_ADAPTER *pAd, IN UCHAR bbpId, IN CHAR bbpVal, IN RX_CHAIN_IDX rx_ch_idx) { UCHAR idx = 0, val = 0; if (((pAd->MACVersion & 0xffff0000) <= 0x30900000) || (pAd->Antenna.field.RxPath == 1)) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, bbpId, bbpVal); return NDIS_STATUS_SUCCESS; } while (rx_ch_idx != 0) { if (idx >= pAd->Antenna.field.RxPath) break; if (rx_ch_idx & 0x01) { RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R27, &val); val = (val & (~0x60)) | (idx << 5); #ifdef RTMP_MAC_PCI if (IS_PCI_INF(pAd) || IS_RBUS_INF(pAd)) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R27, val); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, bbpId, bbpVal); } #endif /* RTMP_MAC_PCI */ DBGPRINT(RT_DEBUG_INFO, ("%s(Idx):Write(R%d,val:0x%x) to Chain(0x%x, idx:%d)\n", __FUNCTION__, bbpId, bbpVal, rx_ch_idx, idx)); } rx_ch_idx >>= 1; idx++; } return NDIS_STATUS_SUCCESS; }
static VOID ChipBBPAdjust(RTMP_ADAPTER *pAd) { UCHAR bbp_val; UINT8 rf_bw, ext_ch; #ifdef DOT11_N_SUPPORT if (get_ht_cent_ch(pAd, &rf_bw, &ext_ch) == FALSE) #endif /* DOT11_N_SUPPORT */ { rf_bw = BW_20; ext_ch = EXTCHA_NONE; pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel; } bbp_set_bw(pAd, rf_bw); /* TX/RX : control channel setting */ AsicSetCtrlCh(pAd, ext_ch); bbp_set_ctrlch(pAd, ext_ch); /* request by Gary 20070208 for middle and long range G Band*/ #ifdef DOT11_N_SUPPORT if (rf_bw == BW_40) bbp_val = (pAd->CommonCfg.Channel > 14) ? 0x48 : 0x38; else #endif /* DOT11_N_SUPPORT */ bbp_val = (pAd->CommonCfg.Channel > 14) ? 0x40 : 0x38; bbp_set_agc(pAd, bbp_val, RX_CHAIN_ALL); if (pAd->MACVersion == 0x28600100) { #ifdef RT28xx RT28xx_ch_tunning(pAd, BW_40); #endif /* RT28xx */ } else { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x12); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0A); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x10); } MTWF_LOG(DBG_CAT_ALL, DBG_SUBCAT_ALL, DBG_LVL_TRACE, ("%s(): BW_%s, ChannelWidth=%d, Channel=%d, ExtChanOffset=%d(%d) \n", __FUNCTION__, (rf_bw == BW_40 ? "40" : "20"), pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth, pAd->CommonCfg.Channel, pAd->CommonCfg.RegTransmitSetting.field.EXTCHA, pAd->CommonCfg.AddHTInfo.AddHtInfo.ExtChanOffset)); /* request by Gary 20070208 for middle and long range A Band*/ if (pAd->CommonCfg.Channel > 14) bbp_val = 0x1D; else bbp_val = 0x2D; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, bbp_val); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, bbp_val); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, bbp_val); /*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, bbp_val);*/ }
/* ======================================================================== Routine Description: Bbp Radar detection routine Arguments: pAd Pointer to our adapter Return Value: ======================================================================== */ VOID BbpRadarDetectionStart( IN PRTMP_ADAPTER pAd) { UINT8 RadarPeriod; if (pAd->CommonCfg.dfs_func >= HARDWARE_DFS_V1) { return; } RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, 114, 0x02); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, 121, 0x20); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, 122, 0x00); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, 123, 0x08/*0x80*/); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, 124, 0x28); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, 125, 0xff); RadarPeriod = ((UINT)RdIdleTimeTable[pAd->CommonCfg.RadarDetect.RDDurRegion][0] + (UINT)pAd->CommonCfg.RadarDetect.DfsSessionTime) < 250 ? (RdIdleTimeTable[pAd->CommonCfg.RadarDetect.RDDurRegion][0] + pAd->CommonCfg.RadarDetect.DfsSessionTime) : 250; RTMP_IO_WRITE8(pAd, 0x7020, 0x1d); RTMP_IO_WRITE8(pAd, 0x7021, 0x40); RadarDetectionStart(pAd, 0, RadarPeriod); return; }
/* ======================================================================== Routine Description: 3572/3592 R66 writing must select BBP_R27 Arguments: Return Value: IRQL = Note: ======================================================================== */ NTSTATUS RT3572WriteBBPR66( IN PRTMP_ADAPTER pAd, IN UCHAR Value) { NTSTATUS NStatus = STATUS_UNSUCCESSFUL; UCHAR bbpData = 0; if (!IS_RT3572(pAd) && !IS_RT3593(pAd)) { DBGPRINT(RT_DEBUG_ERROR, ("%s: Incorrect MAC version, pAd->MACVersion = 0x%X\n", __FUNCTION__, pAd->MACVersion)); return NStatus; } RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R27, &bbpData); /* R66 controls the gain of Rx0*/ bbpData &= ~(0x60); /*clear bit 5,6*/ #ifdef RTMP_MAC_USB if (RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R27, bbpData) == STATUS_SUCCESS) #endif /* RTMP_MAC_USB */ { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, Value); } /* R66 controls the gain of Rx1*/ bbpData |= 0x20; /* set bit 5*/ #ifdef RTMP_MAC_USB if (RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R27, bbpData) == STATUS_SUCCESS) #endif /* RTMP_MAC_USB */ { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, Value); NStatus = STATUS_SUCCESS; } return NStatus; }
/* ======================================================================== Routine Description: Bbp Radar detection routine Arguments: pAd Pointer to our adapter Return Value: ======================================================================== */ VOID BbpRadarDetectionStart( IN PRTMP_ADAPTER pAd) { UINT8 RadarPeriod; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, 114, 0x02); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, 121, 0x20); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, 122, 0x00); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, 123, 0x08/*0x80*/); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, 124, 0x28); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, 125, 0xff); #ifdef MERGE_ARCH_TEAM if ((pAd->CommonCfg.RadarDetect.RDDurRegion == JAP) || (pAd->CommonCfg.RadarDetect.RDDurRegion == JAP_W53) || (pAd->CommonCfg.RadarDetect.RDDurRegion == JAP_W56)) { pAd->CommonCfg.RadarDetect.RDDurRegion = JAP; pAd->CommonCfg.RadarDetect.RDDurRegion = JapRadarType(pAd); if (pAd->CommonCfg.RadarDetect.RDDurRegion == JAP_W56) { pAd->CommonCfg.RadarDetect.DfsSessionTime = 13; } else if (pAd->CommonCfg.RadarDetect.RDDurRegion == JAP_W53) { pAd->CommonCfg.RadarDetect.DfsSessionTime = 15; } #ifdef CARRIER_DETECTION_SUPPORT pAd->CommonCfg.CarrierDetect.Enable = 1; #endif // CARRIER_DETECTION_SUPPORT // } #endif // MERGE_ARCH_TEAM // #if 0 // toggle Rx enable bit for radar detection. // it's Andy's recommand. { UINT32 Value; RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value); Value |= (0x1 << 3); RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value); Value &= ~(0x1 << 3); RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value); } #endif RadarPeriod = ((UINT)RdIdleTimeTable[pAd->CommonCfg.RadarDetect.RDDurRegion][0] + (UINT)pAd->CommonCfg.RadarDetect.DfsSessionTime) < 250 ? (RdIdleTimeTable[pAd->CommonCfg.RadarDetect.RDDurRegion][0] + pAd->CommonCfg.RadarDetect.DfsSessionTime) : 250; #ifdef MERGE_ARCH_TEAM #else // Original RT28xx source code. RTMP_IO_WRITE8(pAd, 0x7020, 0x1d); RTMP_IO_WRITE8(pAd, 0x7021, 0x40); #endif // MERGE_ARCH_TEAM // RadarDetectionStart(pAd, 0, RadarPeriod); return; }
INT rtmp_bbp_set_mmps(struct _RTMP_ADAPTER *pAd, BOOLEAN ReduceCorePower) { UCHAR bbp_val, org_val; RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &org_val); bbp_val = org_val; if (ReduceCorePower) bbp_val |= 0x04; else bbp_val &= ~0x04; if (bbp_val != org_val) RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, bbp_val); return TRUE; }
/* ======================================================================== Routine Description: Bbp Radar detection routine Arguments: pAd Pointer to our adapter Return Value: ======================================================================== */ VOID BbpRadarDetectionStart( IN PRTMP_ADAPTER pAd) { UINT8 RadarPeriod; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, 114, 0x02); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, 121, 0x20); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, 122, 0x00); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, 123, 0x08/*0x80*/); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, 124, 0x28); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, 125, 0xff); #ifdef MERGE_ARCH_TEAM if ((pAd->CommonCfg.RadarDetect.RDDurRegion == JAP) || (pAd->CommonCfg.RadarDetect.RDDurRegion == JAP_W53) || (pAd->CommonCfg.RadarDetect.RDDurRegion == JAP_W56)) { pAd->CommonCfg.RadarDetect.RDDurRegion = JAP; pAd->CommonCfg.RadarDetect.RDDurRegion = JapRadarType(pAd); if (pAd->CommonCfg.RadarDetect.RDDurRegion == JAP_W56) { pAd->CommonCfg.RadarDetect.DfsSessionTime = 13; } else if (pAd->CommonCfg.RadarDetect.RDDurRegion == JAP_W53) { pAd->CommonCfg.RadarDetect.DfsSessionTime = 15; } #ifdef CARRIER_DETECTION_SUPPORT pAd->CommonCfg.CarrierDetect.Enable = 1; #endif // CARRIER_DETECTION_SUPPORT // } #endif // MERGE_ARCH_TEAM // RadarPeriod = ((UINT)RdIdleTimeTable[pAd->CommonCfg.RadarDetect.RDDurRegion][0] + (UINT)pAd->CommonCfg.RadarDetect.DfsSessionTime) < 250 ? (RdIdleTimeTable[pAd->CommonCfg.RadarDetect.RDDurRegion][0] + pAd->CommonCfg.RadarDetect.DfsSessionTime) : 250; #ifdef MERGE_ARCH_TEAM #ifdef CONFIG_AP_SUPPORT #ifdef CARRIER_DETECTION_SUPPORT if (pAd->CommonCfg.CarrierDetect.Enable == TRUE) { // make sure CarrierDetect wont send CTS CARRIER_DETECT_STOP(pAd); } #endif // CARRIER_DETECTION_SUPPORT // #endif // CONFIG_AP_SUPPORT // #else // Original RT28xx source code. RTMP_IO_WRITE8(pAd, 0x7020, 0x1d); RTMP_IO_WRITE8(pAd, 0x7021, 0x40); #endif // MERGE_ARCH_TEAM // RadarDetectionStart(pAd, 0, RadarPeriod); return; }
/* ========================================================================== Description: Load RF normal operation-mode setup ========================================================================== */ static VOID RT3593LoadRFNormalModeSetup( IN PRTMP_ADAPTER pAd) { UCHAR RfReg; CHAR bbpreg = 0; // TX_LO2_en RT30xxReadRFRegister(pAd, RF_R50, (PUCHAR)&RfReg); RfReg = ((RfReg & ~0x10) | 0x00); // tx_lo2_en (both bands, 0: LO2 follows TR switch) RT30xxWriteRFRegister(pAd, RF_R50, (UCHAR)RfReg); // TX_LO1_en, RX_MX2_GC RT30xxReadRFRegister(pAd, RF_R51, (PUCHAR)&RfReg); RfReg = ((RfReg & ~0x1C) | ((pAd->TxMixerGain24G & 0x07) << 2)); // tx_mx1_cc (RF mixer output tank tuning, both bands) RT30xxWriteRFRegister(pAd, RF_R51, (UCHAR)RfReg); // RX_LO1_en RT30xxReadRFRegister(pAd, RF_R38, (PUCHAR)&RfReg); RfReg = ((RfReg & ~0x20) | 0x00); // rx_lo1_en (enable RX LO1, 0: LO1 follows TR switch) RT30xxWriteRFRegister(pAd, RF_R38, (UCHAR)RfReg); // RX_LO2_en RT30xxReadRFRegister(pAd, RF_R39, (PUCHAR)&RfReg); RfReg = ((RfReg & ~0x80) | 0x00); // rx_lo2_en (enable RX LO2, 0: LO2 follows TR switch) RT30xxWriteRFRegister(pAd, RF_R39, (UCHAR)RfReg); // // Avoid data lost and CRC error // RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &bbpreg); bbpreg = ((bbpreg & ~0x40) | 0x40); // MAC interface control (MAC_IF_80M, 1: 80 MHz) RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, bbpreg); RT30xxReadRFRegister(pAd, RF_R32, (PUCHAR)&RfReg); RfReg = ((RfReg & ~0x07) | 0x07); // BB_rx_out_en (enable DAC output or baseband input) //RT30xxWriteRFRegister(pAd, RF_R32, (UCHAR)RfReg); RT30xxReadRFRegister(pAd, RF_R01, (PUCHAR)&RfReg); RfReg = ((RfReg & ~0x03) | 0x03); // rf_block_en and pll_en RT30xxWriteRFRegister(pAd, RF_R01, (UCHAR)RfReg); RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RfReg); RfReg = ((RfReg & ~0x18) | 0x10); // rxvcm (Rx BB filter VCM) RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg); } /* End of RT3593LoadRFNormalModeSetup */
static INT rtmp_bbp_set_rxpath(struct _RTMP_ADAPTER *pAd, INT rxpath) { UCHAR val = 0; RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &val); val &= (~0x18); if(rxpath == 3) val |= (0x10); else if(rxpath == 2) val |= (0x8); else if(rxpath == 1) val |= (0x0); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, val); return TRUE; }
INT rtmp_bbp_set_rxpath(struct _RTMP_ADAPTER *pAd, INT rxpath) { UCHAR val = 0; RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &val); val &= (~0x18); if(rxpath == 3) val |= (0x10); else if(rxpath == 2) val |= (0x8); else if(rxpath == 1) val |= (0x0); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, val); #ifdef CONFIG_STA_SUPPORT #endif /* CONFIG_STA_SUPPORT */ return TRUE; }
INT rtmp_bbp_tx_comp_init(RTMP_ADAPTER *pAd, INT adc_insel, INT tssi_mode) { UCHAR bbp_val, rf_val; /* Set BBP_R47 */ RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R47, &bbp_val); bbp_val &= 0xe7; bbp_val |= ((tssi_mode << 3) & 0x18); bbp_val |= 0x80; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R47, bbp_val); /* Set RF_R27 */ RT30xxReadRFRegister(pAd, RF_R27, &rf_val); rf_val &= 0x3f; rf_val |= ((adc_insel << 6) & 0xc0); RT30xxWriteRFRegister(pAd, RF_R27, rf_val); DBGPRINT(RT_DEBUG_TRACE, ("[temp. compensation] Set RF_R27 to 0x%x\n", rf_val)); }
static NDIS_STATUS AsicBBPReadWithRxChain( IN RTMP_ADAPTER *pAd, IN UCHAR bbpId, IN CHAR *pBbpVal, IN RX_CHAIN_IDX rx_ch_idx) { UCHAR idx, val; if (((pAd->MACVersion & 0xffff0000) <= 0x30900000) || (pAd->Antenna.field.RxPath == 1)) { RTMP_BBP_IO_READ8_BY_REG_ID(pAd, bbpId, pBbpVal); return NDIS_STATUS_SUCCESS; } idx = 0; while(rx_ch_idx != 0) { if (idx >= pAd->Antenna.field.RxPath) break; if (rx_ch_idx & 0x01) { val = 0; RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R27, &val); val = (val & (~0x60)) | (idx << 5); #ifdef RTMP_MAC_PCI if (IS_PCI_INF(pAd) || IS_RBUS_INF(pAd)) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R27, val); RTMP_BBP_IO_READ8_BY_REG_ID(pAd, bbpId, pBbpVal); } #endif /* RTMP_MAC_PCI */ break; } rx_ch_idx >>= 1; idx++; } return NDIS_STATUS_SUCCESS; }
static INT rtmp_bbp_set_filter_coefficient_ctrl(RTMP_ADAPTER *pAd, UCHAR Channel) { UCHAR bbp_val = 0, org_val = 0; if (Channel == 14) { /* when Channel==14 && Mode==CCK && BandWidth==20M, BBP R4 bit5=1 */ RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &org_val); bbp_val = org_val; if (WMODE_EQUAL(pAd->CommonCfg.PhyMode, WMODE_B)) bbp_val |= 0x20; else bbp_val &= (~0x20); if (bbp_val != org_val) RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, bbp_val); } return TRUE; }
VOID RT30xx_RTMPSetAGCInitValue( IN PRTMP_ADAPTER pAd, IN UCHAR BandWidth) { UCHAR R66 = 0x30; if (pAd->LatchRfRegs.Channel <= 14) { /* BG band*/ /* Gary was verified Amazon AP and find that RT307x has BBP_R66 invalid default value */ if (IS_RT3070(pAd)||IS_RT3090(pAd) || IS_RT3390(pAd) || IS_RT3593(pAd)) { R66 = 0x1C + 2*GET_LNA_GAIN(pAd); { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, R66); } } } }
VOID RT30xx_ChipBBPAdjust( IN RTMP_ADAPTER *pAd) { UINT32 Value; UCHAR byteValue = 0; { // pAd->CommonCfg.BBPCurrentBW = BW_20; // pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel; /* TX : control channel at lower */ RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value); Value &= (~0x1); RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value); RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &byteValue); byteValue &= (~0x18); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, byteValue); /* 20 MHz bandwidth*/ /* request by Gary 20070208*/ /*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, 0x30);*/ /* request by Brian 20070306*/ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, 0x38); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x12); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0a); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x10); } /* request by Gary 20070208 for middle and long range G band*/ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, 0x2D); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, 0x2D); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, 0x2D); /*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0x2D);*/ }
static INT rtmp_bbp_set_ctrlch(struct _RTMP_ADAPTER *pAd, UINT8 ext_ch) { UCHAR val, old_val = 0; RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &old_val); val = old_val; switch (ext_ch) { case EXTCHA_BELOW: val |= (0x20); break; case EXTCHA_ABOVE: case EXTCHA_NONE: val &= (~0x20); break; } if (val != old_val) RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, val); return TRUE; }