static inline VOID EWDS( IN PRTMP_ADAPTER pAd) { UINT32 x; // reset bits and set EECS RTMP_IO_READ32(pAd, E2PROM_CSR, &x); x &= ~(EEDI | EEDO | EESK); x |= EECS; RTMP_IO_WRITE32(pAd, E2PROM_CSR, x); // kick a pulse RaiseClock(pAd, &x); LowerClock(pAd, &x); // output the read_opcode and six pulse in that order ShiftOutBits(pAd, EEPROM_EWDS_OPCODE, 5); ShiftOutBits(pAd, 0, 6); EEpromCleanup(pAd); }
static inline VOID EWDS( IN PRTMP_ADAPTER pAd) { UINT32 x; RTMP_IO_READ32(pAd, E2PROM_CSR, &x); x &= ~(EEDI | EEDO | EESK); x |= EECS; RTMP_IO_WRITE32(pAd, E2PROM_CSR, x); RaiseClock(pAd, &x); LowerClock(pAd, &x); ShiftOutBits(pAd, EEPROM_EWDS_OPCODE, 5); ShiftOutBits(pAd, 0, 6); EEpromCleanup(pAd); }
BOOLEAN WaitForAsicReady(RTMP_ADAPTER *pAd) { UINT32 mac_val = 0, reg = MAC_CSR0; int idx = 0; do { if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)) return FALSE; RTMP_IO_READ32(pAd, reg, &mac_val); if ((mac_val != 0x00) && (mac_val != 0xFFFFFFFF)) return TRUE; RtmpOsMsDelay(5); } while (idx++ < 500); DBGPRINT(RT_DEBUG_ERROR, ("%s(0x%x):AsicNotReady!\n", __FUNCTION__, mac_val)); return FALSE; }
/* ======================================================================== Routine Description: Process MGMT ring DMA done interrupt, running in DPC level Arguments: pAd Pointer to our adapter Return Value: None IRQL = DISPATCH_LEVEL Note: ======================================================================== */ void RTMPHandleMgmtRingDmaDoneInterrupt(struct rt_rtmp_adapter *pAd) { struct rt_txd * pTxD; void *pPacket; /* int i; */ u8 FREE = 0; struct rt_rtmp_mgmt_ring *pMgmtRing = &pAd->MgmtRing; NdisAcquireSpinLock(&pAd->MgmtRingLock); RTMP_IO_READ32(pAd, TX_MGMTDTX_IDX, &pMgmtRing->TxDmaIdx); while (pMgmtRing->TxSwFreeIdx != pMgmtRing->TxDmaIdx) { FREE++; pTxD = (struct rt_txd *) (pMgmtRing->Cell[pAd->MgmtRing.TxSwFreeIdx]. AllocVa); pTxD->DMADONE = 0; pPacket = pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNdisPacket; if (pPacket) { PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr0, pTxD->SDLen0, PCI_DMA_TODEVICE); RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS); } pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNdisPacket = NULL; pPacket = pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNextNdisPacket; if (pPacket) { PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, pTxD->SDLen1, PCI_DMA_TODEVICE); RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS); } pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNextNdisPacket = NULL; INC_RING_INDEX(pMgmtRing->TxSwFreeIdx, MGMT_RING_SIZE); } NdisReleaseSpinLock(&pAd->MgmtRingLock); }
INT Show_LedCfg_Proc( IN PRTMP_ADAPTER pAd, IN PSTRING arg) { LED_CFG_T macLedCfg; ULED_PARAMETER *pLedParameter; pLedParameter = &pAd->LedCntl.SWMCULedCntl.LedParameter; printk("LedAMode_RadioOnLinkA=%d\n", pLedParameter->LedAgCfg.field.LedAMode_RadioOnLinkA); printk("LedGMode_RadioOnLinkA=%d\n", pLedParameter->LedAgCfg.field.LedGMode_RadioOnLinkA); printk("LedAMode_RadioOnLinkG=%d\n", pLedParameter->LedAgCfg.field.LedAMode_RadioOnLinkG); printk("LedGMode_RadioOnLinkG=%d\n", pLedParameter->LedAgCfg.field.LedGMode_RadioOnLinkG); printk("LedAMode_RadioOnLinkDown=%d\n", pLedParameter->LedAgCfg.field.LedAMode_RadioOnLinkDown); printk("LedGMode_RadioOnLinkDown=%d\n", pLedParameter->LedAgCfg.field.LedGMode_RadioOnLinkDown); printk("LedAMode_RadioOff=%d\n", pLedParameter->LedAgCfg.field.LedAMode_RadioOff); printk("LedGMode_RadioOff=%d\n", pLedParameter->LedAgCfg.field.LedGMode_RadioOff); printk("LedActModeNoTx_RadioOnLinkA=%d\n", pLedParameter->LedActCfg.field.LedActModeNoTx_RadioOnLinkA); printk("LedActMode_RadioOnLinkA=%d\n", pLedParameter->LedActCfg.field.LedActMode_RadioOnLinkA); printk("LedActModeNoTx_RadioOnLinkG=%d\n", pLedParameter->LedActCfg.field.LedActModeNoTx_RadioOnLinkG); printk("LedActMode_RadioOnLinkG=%d\n", pLedParameter->LedActCfg.field.LedActMode_RadioOnLinkG); printk("LedActModeNoTx_RadioOnLinkDown=%d\n", pLedParameter->LedActCfg.field.LedActModeNoTx_RadioOnLinkDown); printk("LedActMode_RadioOnLinkDown=%d\n", pLedParameter->LedActCfg.field.LedActMode_RadioOnLinkDown); printk("LedActModeNoTx_RadioOff=%d\n", pLedParameter->LedActCfg.field.LedActModeNoTx_RadioOff); printk("LedActMode_RadioOff=%d\n", pLedParameter->LedActCfg.field.LedActMode_RadioOff); RTMP_IO_READ32(pAd, MAC_LED_CFG, &macLedCfg.word); printk("LED_CFG = %x\n\n", macLedCfg.word); printk("LED_ON_TIME = %d\n", macLedCfg.field.LED_ON_TIME); printk("LED_OFF_TIME = %d\n", macLedCfg.field.LED_OFF_TIME); printk("SLOW_BLK_TIME = %d\n", macLedCfg.field.SLOW_BLK_TIME); printk("R_LED_MODE (A) = %d\n", macLedCfg.field.R_LED_MODE); printk("G_LED_MODE (ACT) = %d\n", macLedCfg.field.G_LED_MODE); printk("Y_LED_MODE (A) = %d\n", macLedCfg.field.Y_LED_MODE); printk("LED_POL = %d\n", macLedCfg.field.LED_POL); return TRUE; }
static VOID mt7628_init_mac_cr(RTMP_ADAPTER *pAd) { MTWF_LOG(DBG_CAT_ALL, DBG_SUBCAT_ALL, DBG_LVL_OFF, ("%s()-->\n", __FUNCTION__)); // enable MAC2MAC mode #ifdef MT7628_FPGA UINT32 mac_val; RTMP_IO_READ32(pAd, RMAC_MISC, &mac_val); mac_val |= BIT18; RTMP_IO_WRITE32(pAd, RMAC_MISC, mac_val); mac_val = 0x00d700d7; RTMP_IO_WRITE32(pAd, TMAC_CDTR, mac_val); mac_val = 0x00d700d7; RTMP_IO_WRITE32(pAd, TMAC_ODTR, mac_val); #endif /* MT7628_FPGA */ /* TxS Setting */ InitTxSTypeTable(pAd); MtAsicSetTxSClassifyFilter(pAd, TXS2HOST, TXS2H_QID1, TXS2HOST_AGGNUMS, 0x00); MtAsicSetTxSClassifyFilter(pAd, TXS2MCU, TXS2M_QID0, TXS2MCU_AGGNUMS, 0x00); }
/* ======================================================================== Routine Description: Write RT30xx RF register through MAC Arguments: Return Value: IRQL = Note: ======================================================================== */ NDIS_STATUS RT30xxWriteRFRegister( IN PRTMP_ADAPTER pAd, IN UCHAR regID, IN UCHAR value) { RF_CSR_CFG_STRUC rfcsr = { { 0 } }; UINT i = 0; { ASSERT((regID <= pAd->chipCap.MaxNumOfRfId)); /* R0~R31 or R63*/ do { RTMP_IO_READ32(pAd, RF_CSR_CFG, &rfcsr.word); if (!rfcsr.field.RF_CSR_KICK) break; i++; } while ((i < RETRY_LIMIT) && (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))); if ((i == RETRY_LIMIT) || (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))) { DBGPRINT_RAW(RT_DEBUG_ERROR, ("Retry count exhausted or device removed!!!\n")); return STATUS_UNSUCCESSFUL; } rfcsr.field.RF_CSR_WR = 1; rfcsr.field.RF_CSR_KICK = 1; rfcsr.field.TESTCSR_RFACC_REGNUM = regID; /* R0~R31*/ rfcsr.field.RF_CSR_DATA = value; RTMP_IO_WRITE32(pAd, RF_CSR_CFG, rfcsr.word); } return NDIS_STATUS_SUCCESS; }
static inline BOOLEAN rf_csr_poll_idle(RTMP_ADAPTER *pAd, UINT32 *rfcsr) { RF_CSR_CFG_STRUC *csr_val; BOOLEAN idle = BUSY; INT i = 0; do { if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)) break; RTMP_IO_READ32(pAd, RF_CSR_CFG, rfcsr); csr_val = (RF_CSR_CFG_STRUC *)rfcsr; #ifdef RT6352 if (IS_RT6352(pAd)) idle = csr_val->bank_6352.RF_CSR_KICK; else #endif /* RT6352 */ #ifdef RT65xx if (IS_RT65XX(pAd)) idle = csr_val->bank_65xx.RF_CSR_KICK; else #endif /* RT65xx */ idle = csr_val->non_bank.RF_CSR_KICK; if (idle == IDLE) break; i++; } while (i < MAX_BUSY_COUNT); if ((i == MAX_BUSY_COUNT) || (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))) { DBGPRINT_RAW(RT_DEBUG_ERROR, ("Retry count exhausted or device removed(cnt=%d)!\n", i)); } return idle; }
VOID CheckSkipTX( RTMP_ADAPTER *pAd, MAC_TABLE_ENTRY *pEntry) { struct wtbl_entry tb_entry; union WTBL_1_DW3 *dw3 = (union WTBL_1_DW3 *)&tb_entry.wtbl_1.wtbl_1_d3.word; STA_TR_ENTRY *tr_entry; CHAR isChange = FALSE; NdisZeroMemory(&tb_entry, sizeof(tb_entry)); if (mt_wtbl_get_entry234(pAd, pEntry->wcid, &tb_entry) == FALSE) { DBGPRINT(RT_DEBUG_INFO | DBG_FUNC_PS, ("%s():Cannot found WTBL2/3/4\n",__FUNCTION__)); return; } tr_entry = &pAd->MacTab.tr_entry[pEntry->wcid]; RTMP_IO_READ32(pAd, tb_entry.wtbl_addr[0]+12, &dw3->word); if ((tr_entry->ps_state != APPS_RETRIEVE_START_PS) && (dw3->field.skip_tx == 1)) { dw3->field.skip_tx = 0; isChange = TRUE; } if ((tr_entry->ps_state < APPS_RETRIEVE_DONE) && (dw3->field.du_i_psm == 1)) { dw3->field.du_i_psm = 0; dw3->field.i_psm = 0; /* also sync pEntry flag*/ pEntry->i_psm = 0 ; isChange = TRUE; } if (isChange == TRUE) { pAd->SkipTxRCount++; RTMP_IO_WRITE32(pAd, tb_entry.wtbl_addr[0]+12, dw3->word); } return; }
static VOID RTMPInitPCIeDevice( IN struct pci_dev *pci_dev, IN PRTMP_ADAPTER pAd) { USHORT device_id; POS_COOKIE pObj; pObj = (POS_COOKIE) pAd->OS_Cookie; pci_read_config_word(pci_dev, PCI_DEVICE_ID, &device_id); device_id = le2cpu16(device_id); pObj->DeviceID = device_id; if ( #ifdef RT3090 (device_id == NIC3090_PCIe_DEVICE_ID) || (device_id == NIC3091_PCIe_DEVICE_ID) || (device_id == NIC3092_PCIe_DEVICE_ID) || #endif 0) { UINT32 MacCsr0 = 0, Index= 0; do { RTMP_IO_READ32(pAd, MAC_CSR0, &MacCsr0); if ((MacCsr0 != 0x00) && (MacCsr0 != 0xFFFFFFFF)) break; RTMPusecDelay(10); } while (Index++ < 100); if ((MacCsr0&0xffff0000) != 0x28600000) { OPSTATUS_SET_FLAG(pAd, fOP_STATUS_PCIE_DEVICE); } } }
/*************************************************************************** * * PCIe device initialization related procedures. * ***************************************************************************/ static void RTMPInitPCIeDevice(struct pci_dev *pci_dev, struct rt_rtmp_adapter *pAd) { u16 device_id; struct os_cookie *pObj; pObj = (struct os_cookie *)pAd->OS_Cookie; pci_read_config_word(pci_dev, PCI_DEVICE_ID, &device_id); device_id = le2cpu16(device_id); pObj->DeviceID = device_id; if ( #ifdef RT2860 (device_id == NIC2860_PCIe_DEVICE_ID) || (device_id == NIC2790_PCIe_DEVICE_ID) || (device_id == VEN_AWT_PCIe_DEVICE_ID) || #endif #ifdef RT3090 (device_id == NIC3090_PCIe_DEVICE_ID) || (device_id == NIC3091_PCIe_DEVICE_ID) || (device_id == NIC3092_PCIe_DEVICE_ID) || #endif /* RT3090 // */ 0) { u32 MacCsr0 = 0, Index = 0; do { RTMP_IO_READ32(pAd, MAC_CSR0, &MacCsr0); if ((MacCsr0 != 0x00) && (MacCsr0 != 0xFFFFFFFF)) break; RTMPusecDelay(10); } while (Index++ < 100); /* Support advanced power save after 2892/2790. */ /* MAC version at offset 0x1000 is 0x2872XXXX/0x2870XXXX(PCIe, USB, SDIO). */ if ((MacCsr0 & 0xffff0000) != 0x28600000) { OPSTATUS_SET_FLAG(pAd, fOP_STATUS_PCIE_DEVICE); } } }
INT bbp_set_bw(struct _RTMP_ADAPTER *pAd, UINT8 bw) { INT result = FALSE; if (pAd->phy_op && pAd->phy_op->bbp_set_bw) result = pAd->phy_op->bbp_set_bw(pAd, bw); if (result == TRUE) { DBGPRINT(RT_DEBUG_TRACE, ("%s(): Set PhyBW as %sHz.l\n", __FUNCTION__, get_bw_str(bw))); } // TODO: shiang-7603, revise following code #ifdef MT_MAC if (pAd->chipCap.hif_type == HIF_MT) { UINT32 val; RTMP_IO_READ32(pAd, AGG_BWCR, &val); val &= (~0x0c); switch (bw) { case BW_20: val |= (0); break; case BW_40: val |= (0x1 << 2); break; case BW_80: val |= (0x2 << 2); break; } RTMP_IO_WRITE32(pAd, AGG_BWCR, val); } #endif /* MT_MAC */ return result; }
VOID RTMPHandleRxCoherentInterrupt( IN PRTMP_ADAPTER pAd) { WPDMA_GLO_CFG_STRUC GloCfg; if (pAd == NULL) { DBGPRINT(RT_DEBUG_TRACE, ("====> pAd is NULL, return.\n")); return; } DBGPRINT(RT_DEBUG_TRACE, ("==> RTMPHandleRxCoherentInterrupt \n")); RTMP_IO_READ32(pAd, WPDMA_GLO_CFG , &GloCfg.word); GloCfg.field.EnTXWriteBackDDONE = 0; GloCfg.field.EnableRxDMA = 0; GloCfg.field.EnableTxDMA = 0; RTMP_IO_WRITE32(pAd, WPDMA_GLO_CFG, GloCfg.word); DBGPRINT_TX_RING(pAd, QID_AC_BE); DBGPRINT_TX_RING(pAd, QID_AC_BK); DBGPRINT_TX_RING(pAd, QID_AC_VI); DBGPRINT_TX_RING(pAd, QID_AC_VO); DBGPRINT_TX_RING(pAd, QID_MGMT); RTMPRingCleanUp(pAd, QID_AC_BE); RTMPRingCleanUp(pAd, QID_AC_BK); RTMPRingCleanUp(pAd, QID_AC_VI); RTMPRingCleanUp(pAd, QID_AC_VO); RTMPRingCleanUp(pAd, QID_HCCA); RTMPRingCleanUp(pAd, QID_MGMT); RTMPRingCleanUp(pAd, QID_RX); RTMPEnableRxTx(pAd); DBGPRINT(RT_DEBUG_TRACE, ("<== RTMPHandleRxCoherentInterrupt \n")); }
/*************************************************************************** * * PCIe device initialization related procedures. * ***************************************************************************/ static VOID RTMPInitPCIeDevice( IN struct pci_dev *pci_dev, IN PRTMP_ADAPTER pAd) { USHORT device_id; POS_COOKIE pObj; pObj = (POS_COOKIE) pAd->OS_Cookie; pci_read_config_word(pci_dev, PCI_DEVICE_ID, &device_id); device_id = le2cpu16(device_id); pObj->DeviceID = device_id; if ( #ifdef RT3090 (device_id == NIC3090_PCIe_DEVICE_ID) || (device_id == NIC3091_PCIe_DEVICE_ID) || (device_id == NIC3092_PCIe_DEVICE_ID) || #endif // RT3090 // 0) { UINT32 MacCsr0 = 0, Index= 0; do { RTMP_IO_READ32(pAd, MAC_CSR0, &MacCsr0); if ((MacCsr0 != 0x00) && (MacCsr0 != 0xFFFFFFFF)) break; RTMPusecDelay(10); } while (Index++ < 100); // Support advanced power save after 2892/2790. // MAC version at offset 0x1000 is 0x2872XXXX/0x2870XXXX(PCIe, USB, SDIO). if ((MacCsr0&0xffff0000) != 0x28600000) { OPSTATUS_SET_FLAG(pAd, fOP_STATUS_PCIE_DEVICE); } } }
// IRQL = PASSIVE_LEVEL int rtmp_ee_prom_read16( IN PRTMP_ADAPTER pAd, IN USHORT Offset, OUT USHORT *pValue) { UINT32 x; USHORT data; Offset /= 2; // reset bits and set EECS RTMP_IO_READ32(pAd, E2PROM_CSR, &x); x &= ~(EEDI | EEDO | EESK); x |= EECS; RTMP_IO_WRITE32(pAd, E2PROM_CSR, x); // patch can not access e-Fuse issue if (!(IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd) || IS_RT3593(pAd))) { // kick a pulse RaiseClock(pAd, &x); LowerClock(pAd, &x); } // output the read_opcode and register number in that order ShiftOutBits(pAd, EEPROM_READ_OPCODE, 3); ShiftOutBits(pAd, Offset, pAd->EEPROMAddressNum); // Now read the data (16 bits) in from the selected EEPROM word data = ShiftInBits(pAd); EEpromCleanup(pAd); *pValue = data; return NDIS_STATUS_SUCCESS; }
int rtmp_mac_set_band(RTMP_ADAPTER *pAd, int band) { UINT32 val, band_cfg; RTMP_IO_READ32(pAd, TX_BAND_CFG, &band_cfg); val = band_cfg & (~0x6); switch (band) { case BAND_5G: val |= 0x02; break; case BAND_24G: default: val |= 0x4; break; } if (val != band_cfg) RTMP_IO_WRITE32(pAd, TX_BAND_CFG, val); return TRUE; }
INT AsicGetMacVersion( IN RTMP_ADAPTER *pAd) { UINT32 reg = MAC_CSR0; #ifdef RT3290 if (IS_RT3290(pAd)) reg = 0x0; #endif /* RT3290 */ if (WaitForAsicReady(pAd) == TRUE) { RTMP_IO_READ32(pAd, reg, &pAd->MACVersion); DBGPRINT(RT_DEBUG_OFF, ("MACVersion[Ver:Rev]=0x%08x\n", pAd->MACVersion)); return TRUE; } else { DBGPRINT(RT_DEBUG_ERROR, ("%s() failed!\n", __FUNCTION__)); return FALSE; } }
static VOID CFG80211DRV_DisableApInterface( VOID *pAdOrg) { UINT32 Value; PRTMP_ADAPTER pAd = (PRTMP_ADAPTER)pAdOrg; pAd->ApCfg.MBSSID[MAIN_MBSSID].bBcnSntReq = FALSE; /* Disable pre-tbtt interrupt */ RTMP_IO_READ32(pAd, INT_TIMER_EN, &Value); Value &=0xe; RTMP_IO_WRITE32(pAd, INT_TIMER_EN, Value); if (!INFRA_ON(pAd)) { /* Disable piggyback */ RTMPSetPiggyBack(pAd, FALSE); AsicUpdateProtect(pAd, 0, (ALLN_SETPROTECT|CCKSETPROTECT|OFDMSETPROTECT), TRUE, FALSE); } if (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)) { /*RTMP_ASIC_INTERRUPT_DISABLE(pAd); */ AsicDisableSync(pAd); #ifdef LED_CONTROL_SUPPORT /* Set LED */ RTMPSetLED(pAd, LED_LINK_DOWN); #endif /* LED_CONTROL_SUPPORT */ } #ifdef RTMP_MAC_USB /* For RT2870, we need to clear the beacon sync buffer. */ RTUSBBssBeaconExit(pAd); #endif /* RTMP_MAC_USB */ }
static void rtmp_ac0_dma_done_tasklet(unsigned long data) { UINT32 irqsave; UINT32 irqMask; PRTMP_ADAPTER pAdapter = (PRTMP_ADAPTER) data; INT_SOURCE_CSR_STRUC IntSource; /* device had been closed */ if (RTMP_TEST_FLAG(pAdapter, fRTMP_ADAPTER_REMOVE_IN_PROGRESS)) { return; } IntSource.word = 0; IntSource.field.Ac0DmaDone = 1; RTMPHandleTxRingDmaDoneInterrupt(pAdapter, IntSource); RTMP_IRQ_LOCK(irqsave); /* * double check to avoid rotting packet */ if (pAdapter->Rtmp_Masked_Int & RTMP_MASK_INT_AC0_DMA_DONE) { pAdapter->Rtmp_Masked_Int &= ~RTMP_MASK_INT_AC0_DMA_DONE; tasklet_hi_schedule(&pAdapter->ac0_dma_done_task); } else { /* enable ac0 interrupt */ RTMP_IO_READ32(pAdapter, INT_MASK_CSR, &irqMask); RTMP_IO_WRITE32(pAdapter, INT_MASK_CSR, irqMask & ~RTMP_MASK_INT_AC0_DMA_DONE); pAdapter->ac0_dma_done_running = FALSE; } RTMP_IRQ_UNLOCK(irqsave); }
VOID RT30xx_ChipBBPAdjust( IN RTMP_ADAPTER *pAd) { UINT32 Value; UCHAR byteValue = 0; { // pAd->CommonCfg.BBPCurrentBW = BW_20; // pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel; /* TX : control channel at lower */ RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value); Value &= (~0x1); RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value); RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &byteValue); byteValue &= (~0x18); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, byteValue); /* 20 MHz bandwidth*/ /* request by Gary 20070208*/ /*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, 0x30);*/ /* request by Brian 20070306*/ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, 0x38); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x12); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0a); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x10); } /* request by Gary 20070208 for middle and long range G band*/ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, 0x2D); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, 0x2D); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, 0x2D); /*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0x2D);*/ }
INT rtmp_mac_set_ctrlch(RTMP_ADAPTER *pAd, UINT8 extch) { UINT32 val, band_cfg; RTMP_IO_READ32(pAd, TX_BAND_CFG, &band_cfg); val = band_cfg & (~0x1); switch (extch) { case EXTCHA_ABOVE: val &= (~0x1); break; case EXTCHA_BELOW: val |= (0x1); break; case EXTCHA_NONE: val &= (~0x1); break; } if (val != band_cfg) RTMP_IO_WRITE32(pAd, TX_BAND_CFG, val); return TRUE; }
VOID RT35xx_ChipSwitchChannel( IN PRTMP_ADAPTER pAd, IN UCHAR Channel, IN BOOLEAN bScan) { CHAR TxPwer = 0, TxPwer2 = DEFAULT_RF_TX_POWER; /*Bbp94 = BBPR94_DEFAULT, TxPwer2 = DEFAULT_RF_TX_POWER;*/ UCHAR index; UINT32 Value = 0; /*BbpReg, Value;*/ UCHAR RFValue; UINT32 i = 0; i = i; /* avoid compile warning */ RFValue = 0; /* Search Tx power value*/ /* We can't use ChannelList to search channel, since some central channl's txpowr doesn't list in ChannelList, so use TxPower array instead. */ for (index = 0; index < MAX_NUM_OF_CHANNELS; index++) { if (Channel == pAd->TxPower[index].Channel) { TxPwer = pAd->TxPower[index].Power; TxPwer2 = pAd->TxPower[index].Power2; break; } } if (index == MAX_NUM_OF_CHANNELS) { DBGPRINT(RT_DEBUG_ERROR, ("AsicSwitchChannel: Can't find the Channel#%d \n", Channel)); } #ifdef RT35xx /* 3562:RFIC_3052/ 3062:RFIC_3022 */ if (IS_RT3572(pAd) /*&& (pAd->RfIcType == RFIC_3052)*/) { for (index = 0; index < NUM_OF_3572_CHNL; index++) { if (Channel == FreqItems3572[index].Channel) { /* for 2.4G, restore BBP25, BBP26*/ if (Channel <= 14) { BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R25, pAd->Bbp25); BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R26, pAd->Bbp26); } /* hard code for 5GGhz, Gary 2008-12-10*/ else { /* Enable IQ Phase Correction*/ BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R25, 0x09); /* IQ Phase correction value*/ BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R26, 0xFF); } /* Programming channel parameters*/ RT30xxWriteRFRegister(pAd, RF_R02, FreqItems3572[index].N); RT30xxWriteRFRegister(pAd, RF_R03, FreqItems3572[index].K); RT30xxReadRFRegister(pAd, RF_R06, &RFValue); if (Channel <= 14) RFValue = (RFValue & 0xF0) | FreqItems3572[index].R | 0x8; else RFValue = (RFValue & 0xF0) | FreqItems3572[index].R | 0x4; RT30xxWriteRFRegister(pAd, RF_R06, RFValue); /* Pll mode for 2.4G or 5G*/ RT30xxReadRFRegister(pAd, RF_R05, &RFValue); if (Channel <= 14) RFValue = (RFValue & 0xF3) | 0x4; else RFValue = (RFValue & 0xF3) | 0x8; RT30xxWriteRFRegister(pAd, RF_R05, RFValue); /* Set Tx0 Power*/ RT30xxReadRFRegister(pAd, RF_R12, (PUCHAR)&RFValue); if (Channel <= 14) RFValue = 0x60 | TxPwer; else RFValue = 0xE0 | (TxPwer & 0x3) | ((TxPwer & 0xC) << 1); RT30xxWriteRFRegister(pAd, RF_R12, RFValue); /* Set Tx1 Power*/ RT30xxReadRFRegister(pAd, RF_R13, (PUCHAR)&RFValue); if (Channel <= 14) RFValue = 0x60 | TxPwer2; else RFValue = 0xE0 | (TxPwer2 & 0x3) | ((TxPwer2 & 0xC) << 1); RT30xxWriteRFRegister(pAd, RF_R13, RFValue); /* Tx/Rx Stream setting*/ RT30xxReadRFRegister(pAd, RF_R01, (PUCHAR)&RFValue); RFValue &= 0x03; /*clear bit[7~2]*/ if (pAd->Antenna.field.TxPath == 1) RFValue |= 0xA0; else if (pAd->Antenna.field.TxPath == 2) RFValue |= 0x80; if (pAd->Antenna.field.RxPath == 1) RFValue |= 0x50; else if (pAd->Antenna.field.RxPath == 2) RFValue |= 0x40; RT30xxWriteRFRegister(pAd, RF_R01, (UCHAR)RFValue); /* Set RF offset*/ RT30xxReadRFRegister(pAd, RF_R23, (PUCHAR)&RFValue); RFValue = (RFValue & 0x80) | pAd->RfFreqOffset; RT30xxWriteRFRegister(pAd, RF_R23, (UCHAR)RFValue); /* Set BW*/ if (!bScan && (pAd->CommonCfg.BBPCurrentBW == BW_40)) { RFValue = pAd->Mlme.CaliBW40RfR24; /*DISABLE_11N_CHECK(pAd);*/ } else { RFValue = pAd->Mlme.CaliBW20RfR24; } /* R24, R31, one is for tx, the other is for rx*/ RT30xxWriteRFRegister(pAd, RF_R24, (UCHAR)RFValue); RT30xxWriteRFRegister(pAd, RF_R31, (UCHAR)RFValue); /* Enable RF tuning*/ RT30xxReadRFRegister(pAd, RF_R07, (PUCHAR)&RFValue); if (Channel <= 14) /*RFValue = (RFValue & 0x37) | 0xCC;*/ RFValue = 0xd8; /*?? to check 3572?? hardcode*/ else RFValue = (RFValue & 0x37) | 0x14; RT30xxWriteRFRegister(pAd, RF_R07, (UCHAR)RFValue); /* TSSI_BS*/ RT30xxReadRFRegister(pAd, RF_R09, (PUCHAR)&RFValue); if (Channel <= 14) RFValue = 0xC3; /*RFValue = (RFValue & 0xBF) | 0x40;*/ else RFValue = 0xC0; /*RFValue = (RFValue & 0xBF) | 0x40;*/ RT30xxWriteRFRegister(pAd, RF_R09, (UCHAR)RFValue); /* Loop filter 1*/ RT30xxWriteRFRegister(pAd, RF_R10, (UCHAR)0xF1); /* Loop filter 2*/ if (Channel <= 14) RT30xxWriteRFRegister(pAd, RF_R11, (UCHAR)0xB9); else RT30xxWriteRFRegister(pAd, RF_R11, (UCHAR)0x00); /* tx_mx2_ic*/ if (Channel <= 14) RT30xxWriteRFRegister(pAd, RF_R15, (UCHAR)0x53); else RT30xxWriteRFRegister(pAd, RF_R15, (UCHAR)0x43); /* tx_mx1_ic*/ /*RT30xxReadRFRegister(pAd, RF_R16, (PUCHAR)&RFValue);*/ if (Channel <= 14) { RFValue = 0x4c; RFValue &= (~0x7); /* clean bit [2:0]*/ RFValue |= pAd->TxMixerGain24G; } else { RFValue = 0x7a; RFValue &= (~0x7); /* clean bit [2:0]*/ RFValue |= pAd->TxMixerGain5G; } RT30xxWriteRFRegister(pAd, RF_R16, (UCHAR)RFValue); /* tx_lo1*/ RT30xxWriteRFRegister(pAd, RF_R17, (UCHAR)0x23); /* tx_lo2*/ RFValue = ((Channel <= 14) ? (0x93) : ((Channel <= 64) ? (0xb7) : ((Channel <= 128) ? (0x74) : (0x72)))); RT30xxWriteRFRegister(pAd, RF_R19, (UCHAR)RFValue); /* rx_l01*/ RFValue = ((Channel <= 14) ? (0xB3) : ((Channel <= 64) ? (0xF6) : ((Channel <= 128) ? (0xF4) : (0xF3)))); RT30xxWriteRFRegister(pAd, RF_R20, (UCHAR)RFValue); /* pfd_delay*/ RFValue = ((Channel <= 14) ? (0x15) : ((Channel <= 64) ? (0x3d) : ((Channel <= 128) ? (0x01) : (0x01)))); RT30xxWriteRFRegister(pAd, RF_R25, (UCHAR)RFValue); /* rx_lo2*/ if (Channel <= 14) RT30xxWriteRFRegister(pAd, RF_R26, (UCHAR)0x85); else RT30xxWriteRFRegister(pAd, RF_R26, (UCHAR)0x87); /* ldo_rf_vc*/ if (Channel <= 14) RT30xxWriteRFRegister(pAd, RF_R27, (UCHAR)0x00); else RT30xxWriteRFRegister(pAd, RF_R27, (UCHAR)0x01); /* drv_cc*/ if (Channel <= 14) RT30xxWriteRFRegister(pAd, RF_R29, (UCHAR)0x9B); else RT30xxWriteRFRegister(pAd, RF_R29, (UCHAR)0x9F); RTMP_IO_READ32(pAd, GPIO_CTRL_CFG, &Value); if (Channel <= 14) Value = ((Value & 0xFFFF7FFF) | 0x00000080); else Value = (Value & 0xFFFF7F7F); RTMP_IO_WRITE32(pAd, GPIO_CTRL_CFG, Value); /* Enable RF tuning, this must be in the last*/ RT30xxReadRFRegister(pAd, RF_R07, (PUCHAR)&RFValue); RFValue = RFValue | 0x1; RT30xxWriteRFRegister(pAd, RF_R07, (UCHAR)RFValue); RTMPusecDelay(2000); /* latch channel for future usage.*/ pAd->LatchRfRegs.Channel = Channel; DBGPRINT(RT_DEBUG_TRACE, ("RT35xx: SwitchChannel#%d(RF=%d, Pwr0=%d, Pwr1=%d, %dT), N=0x%02X, K=0x%02X, R=0x%02X\n", Channel, pAd->RfIcType, TxPwer, TxPwer2, pAd->Antenna.field.TxPath, FreqItems3572[index].N, FreqItems3572[index].K, FreqItems3572[index].R)); break; } } } else #endif /* RT35xx */ { switch (pAd->RfIcType) { default: DBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d : unknown RFIC=%d\n", Channel, pAd->RfIcType)); break; } } /* Change BBP setting during siwtch from a->g, g->a*/ if (Channel <= 14) { ULONG TxPinCfg = 0x00050F0A;/*Gary 2007/08/09 0x050A0A*/ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd))); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd))); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd))); /* Rx High power VGA offset for LNA select*/ { if (pAd->NicConfig2.field.ExternalLNAForG) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x62); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46); } else { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x84); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50); } } /* 5G band selection PIN, bit1 and bit2 are complement*/ RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value); Value &= (~0x6); Value |= (0x04); RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value); #ifdef RT35xx if (IS_RT3572(pAd)) RT30xxWriteRFRegister(pAd, RF_R08, (UCHAR)0x00); #endif /* RT35xx */ { /* Turn off unused PA or LNA when only 1T or 1R*/ if (pAd->Antenna.field.TxPath == 1) { TxPinCfg &= 0xFFFFFFF3; } if (pAd->Antenna.field.RxPath == 1) { TxPinCfg &= 0xFFFFF3FF; } } RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg); #ifdef RT35xx if (IS_RT3572(pAd)) RT30xxWriteRFRegister(pAd, RF_R08, (UCHAR)0x80); #endif /* RT35xx */ } else { ULONG TxPinCfg = 0x00050F05;/*Gary 2007/8/9 0x050505*/ UINT8 bbpValue; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd))); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd))); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd))); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);/*(0x44 - GET_LNA_GAIN(pAd))); According the Rory's suggestion to solve the middle range issue. */ /* Set the BBP_R82 value here */ bbpValue = 0xF2; #ifdef RT35xx if (IS_RT3572(pAd)) { /* TODO: check if the BBP_R82 value is the same in both of following cases!!!*/ /* Rx High power VGA offset for LNA select*/ bbpValue = 0x94; } #endif /* RT35xx */ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, bbpValue); /* Rx High power VGA offset for LNA select*/ if (pAd->NicConfig2.field.ExternalLNAForA) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46); } else { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50); } /* 5G band selection PIN, bit1 and bit2 are complement*/ RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value); Value &= (~0x6); Value |= (0x02); RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value); /* Turn off unused PA or LNA when only 1T or 1R*/ #ifdef RT35xx if (IS_RT3572(pAd)) RT30xxWriteRFRegister(pAd, RF_R08, (UCHAR)0x00); #endif /* RT35xx */ { /* Turn off unused PA or LNA when only 1T or 1R*/ if (pAd->Antenna.field.TxPath == 1) { TxPinCfg &= 0xFFFFFFF3; } if (pAd->Antenna.field.RxPath == 1) { TxPinCfg &= 0xFFFFF3FF; } } RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg); #ifdef RT35xx if (IS_RT3572(pAd)) RT30xxWriteRFRegister(pAd, RF_R08, (UCHAR)0x80); #endif /* RT35xx */ } /* R66 should be set according to Channel and use 20MHz when scanning*/ /*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, (0x2E + GET_LNA_GAIN(pAd)));*/ if (bScan) RTMPSetAGCInitValue(pAd, BW_20); else RTMPSetAGCInitValue(pAd, pAd->CommonCfg.BBPCurrentBW); /* On 11A, We should delay and wait RF/BBP to be stable*/ /* and the appropriate time should be 1000 micro seconds */ /* 2005/06/05 - On 11G, We also need this delay time. Otherwise it's difficult to pass the WHQL.*/ RTMPusecDelay(1000); }
VOID RT35xx_ChipBBPAdjust( IN RTMP_ADAPTER *pAd) { UINT32 Value; UCHAR byteValue = 0; #ifdef DOT11_N_SUPPORT if ((pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth == BW_40) && (pAd->CommonCfg.RegTransmitSetting.field.EXTCHA == EXTCHA_ABOVE)) { pAd->CommonCfg.BBPCurrentBW = BW_40; pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel + 2; /* TX : control channel at lower */ RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value); Value &= (~0x1); RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value); /* RX : control channel at lower */ RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &byteValue); byteValue &= (~0x20); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, byteValue); RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &byteValue); byteValue &= (~0x18); byteValue |= 0x10; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, byteValue); if (pAd->CommonCfg.Channel > 14) { /* request by Gary 20070208 for middle and long range A Band*/ if (IS_RT3572(pAd) || IS_RT3593(pAd)) RT3572WriteBBPR66(pAd, 0x48); } else { /* request by Gary 20070208 for middle and long range G Band*/ if (IS_RT3572(pAd) || IS_RT3593(pAd)) RT3572WriteBBPR66(pAd, 0x38); } /* */ if (pAd->MACVersion == 0x28600100) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x1A); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0A); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x16); } else { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x12); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0A); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x10); } DBGPRINT(RT_DEBUG_TRACE, ("ApStartUp : ExtAbove, ChannelWidth=%d, Channel=%d, ExtChanOffset=%d(%d) \n", pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth, pAd->CommonCfg.Channel, pAd->CommonCfg.RegTransmitSetting.field.EXTCHA, pAd->CommonCfg.AddHTInfo.AddHtInfo.ExtChanOffset)); } else if ((pAd->CommonCfg.Channel > 2) && (pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth == BW_40) && (pAd->CommonCfg.RegTransmitSetting.field.EXTCHA == EXTCHA_BELOW)) { pAd->CommonCfg.BBPCurrentBW = BW_40; if (pAd->CommonCfg.Channel == 14) pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel - 1; else pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel - 2; /* TX : control channel at upper */ RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value); Value |= (0x1); RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value); /* RX : control channel at upper */ RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &byteValue); byteValue |= (0x20); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, byteValue); RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &byteValue); byteValue &= (~0x18); byteValue |= 0x10; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, byteValue); if (pAd->CommonCfg.Channel > 14) { /* request by Gary 20070208 for middle and long range A Band*/ if (IS_RT3572(pAd) || IS_RT3593(pAd)) RT3572WriteBBPR66(pAd, 0x48); } else { /* request by Gary 20070208 for middle and long range G band*/ if (IS_RT3572(pAd) || IS_RT3593(pAd)) RT3572WriteBBPR66(pAd, 0x38); } if (pAd->MACVersion == 0x28600100) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x1A); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0A); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x16); } else { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x12); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0A); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x10); } DBGPRINT(RT_DEBUG_TRACE, ("ApStartUp : ExtBlow, ChannelWidth=%d, Channel=%d, ExtChanOffset=%d(%d) \n", pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth, pAd->CommonCfg.Channel, pAd->CommonCfg.RegTransmitSetting.field.EXTCHA, pAd->CommonCfg.AddHTInfo.AddHtInfo.ExtChanOffset)); } else #endif /* DOT11_N_SUPPORT */ { pAd->CommonCfg.BBPCurrentBW = BW_20; pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel; /* TX : control channel at lower */ RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value); Value &= (~0x1); RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value); RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &byteValue); byteValue &= (~0x18); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, byteValue); /* 20 MHz bandwidth*/ if (pAd->CommonCfg.Channel > 14) { /* request by Gary 20070208*/ if (IS_RT3572(pAd) || IS_RT3593(pAd)) RT3572WriteBBPR66(pAd, 0x40); } else { /* request by Gary 20070208*/ /*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, 0x30);*/ /* request by Brian 20070306*/ if (IS_RT3572(pAd) || IS_RT3593(pAd)) RT3572WriteBBPR66(pAd, 0x38); } if (pAd->MACVersion == 0x28600100) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x16); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x08); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x11); } else { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x12); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0a); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x10); } #ifdef DOT11_N_SUPPORT DBGPRINT(RT_DEBUG_TRACE, ("ApStartUp : 20MHz, ChannelWidth=%d, Channel=%d, ExtChanOffset=%d(%d) \n", pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth, pAd->CommonCfg.Channel, pAd->CommonCfg.RegTransmitSetting.field.EXTCHA, pAd->CommonCfg.AddHTInfo.AddHtInfo.ExtChanOffset)); #endif /* DOT11_N_SUPPORT */ } if (pAd->CommonCfg.Channel > 14) { /* request by Gary 20070208 for middle and long range A Band*/ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, 0x1D); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, 0x1D); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, 0x1D); /*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0x1D);*/ } else { /* request by Gary 20070208 for middle and long range G band*/ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, 0x2D); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, 0x2D); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, 0x2D); /*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0x2D);*/ } }
VOID RT28xxUsbMlmeRadioOFF( IN PRTMP_ADAPTER pAd) { WPDMA_GLO_CFG_STRUC GloCfg; UINT32 Value, i; DBGPRINT(RT_DEBUG_TRACE,("RT28xxUsbMlmeRadioOFF()\n")); if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF)) return; RTMPSetLED(pAd, LED_RADIO_OFF); RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF); { if (INFRA_ON(pAd) || ADHOC_ON(pAd)) LinkDown(pAd, FALSE); RTMPusecDelay(10000); BssTableInit(&pAd->ScanTab); } if (pAd->CommonCfg.BBPCurrentBW == BW_40) { AsicTurnOffRFClk(pAd, pAd->CommonCfg.CentralChannel); } else { AsicTurnOffRFClk(pAd, pAd->CommonCfg.Channel); } RTUSBReadMACRegister(pAd, WPDMA_GLO_CFG, &GloCfg.word); GloCfg.field.EnableTxDMA = 0; GloCfg.field.EnableRxDMA = 0; RTUSBWriteMACRegister(pAd, WPDMA_GLO_CFG, GloCfg.word); i = 0; do { RTMP_IO_READ32(pAd, WPDMA_GLO_CFG, &GloCfg.word); if ((GloCfg.field.TxDMABusy == 0) && (GloCfg.field.RxDMABusy == 0)) break; RTMPusecDelay(1000); }while (i++ < 100); RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value); Value &= (0xfffffff3); RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value); AsicSendCommandToMcu(pAd, 0x30, 0xff, 0xff, 0x02); }
VOID NICInitRT3572RFRegisters(IN PRTMP_ADAPTER pAd) { INT i; UINT8 RfReg = 0; UINT32 data; /* Driver must read EEPROM to get RfIcType before initial RF registers Initialize RF register to default value Init RF calibration Driver should toggle RF R30 bit7 before init RF registers */ RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RfReg); RfReg |= 0x80; RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg); RTMPusecDelay(1000); RfReg &= 0x7F; RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg); /* Initialize RF register to default value */ for (i = 0; i < NUM_RF_3572REG_PARMS; i++) { RT30xxWriteRFRegister(pAd, RF3572_RFRegTable[i].Register, RF3572_RFRegTable[i].Value); } /* Driver should set RF R6 bit6 on before init RF registers */ RT30xxReadRFRegister(pAd, RF_R06, (PUCHAR)&RfReg); RfReg |= 0x40; RT30xxWriteRFRegister(pAd, RF_R06, (UCHAR)RfReg); /* init R31 */ /*RT30xxWriteRFRegister(pAd, RF_R31, 0x14);*/ if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211)) { /* patch tx EVM issue temporarily */ RTMP_IO_READ32(pAd, LDO_CFG0, &data); data = ((data & 0xF0FFFFFF) | 0x0D000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, data); } else { /* Patch for SRAM, increase voltage to 1.35V on core voltage and down to 1.2V after 1 msec*/ RTMP_IO_READ32(pAd, LDO_CFG0, &data); data = ((data & 0xE0FFFFFF) | 0x0D000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, data); RTMPusecDelay(1000); data = ((data & 0xE0FFFFFF) | 0x01000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, data); } /* patch LNA_PE_G1 (toggle GPIO_SWITCH) is not necessary for 3572 */ /* RTMP_IO_READ32(pAd, GPIO_SWITCH, &data); data &= ~(0x20); RTMP_IO_WRITE32(pAd, GPIO_SWITCH, data); */ /* For RF filter Calibration */ RTMPFilterCalibration(pAd); /* save R25, R26 for 2.4GHz */ BBP_IO_READ8_BY_REG_ID(pAd, BBP_R25, &pAd->Bbp25); BBP_IO_READ8_BY_REG_ID(pAd, BBP_R26, &pAd->Bbp26); /* set led open drain enable */ RTMP_IO_READ32(pAd, OPT_14, &data); data |= 0x01; RTMP_IO_WRITE32(pAd, OPT_14, data); }
void NICInitRT3090RFRegisters(struct rt_rtmp_adapter *pAd) { int i; /* Driver must read EEPROM to get RfIcType before initial RF registers */ /* Initialize RF register to default value */ if (IS_RT3090(pAd)) { /* Init RF calibration */ /* Driver should toggle RF R30 bit7 before init RF registers */ u32 RfReg = 0, data; RT30xxReadRFRegister(pAd, RF_R30, (u8 *)&RfReg); RfReg |= 0x80; RT30xxWriteRFRegister(pAd, RF_R30, (u8)RfReg); RTMPusecDelay(1000); RfReg &= 0x7F; RT30xxWriteRFRegister(pAd, RF_R30, (u8)RfReg); /* init R24, R31 */ RT30xxWriteRFRegister(pAd, RF_R24, 0x0F); RT30xxWriteRFRegister(pAd, RF_R31, 0x0F); /* RT309x version E has fixed this issue */ if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211)) { /* patch tx EVM issue temporarily */ RTMP_IO_READ32(pAd, LDO_CFG0, &data); data = ((data & 0xE0FFFFFF) | 0x0D000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, data); } else { RTMP_IO_READ32(pAd, LDO_CFG0, &data); data = ((data & 0xE0FFFFFF) | 0x01000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, data); } /* patch LNA_PE_G1 failed issue */ RTMP_IO_READ32(pAd, GPIO_SWITCH, &data); data &= ~(0x20); RTMP_IO_WRITE32(pAd, GPIO_SWITCH, data); /* Initialize RF register to default value */ for (i = 0; i < NUM_RF_REG_PARMS; i++) { RT30xxWriteRFRegister(pAd, RT30xx_RFRegTable[i].Register, RT30xx_RFRegTable[i].Value); } /* Driver should set RF R6 bit6 on before calibration */ RT30xxReadRFRegister(pAd, RF_R06, (u8 *)&RfReg); RfReg |= 0x40; RT30xxWriteRFRegister(pAd, RF_R06, (u8)RfReg); /*For RF filter Calibration */ RTMPFilterCalibration(pAd); /* Initialize RF R27 register, set RF R27 must be behind RTMPFilterCalibration() */ if ((pAd->MACVersion & 0xffff) < 0x0211) RT30xxWriteRFRegister(pAd, RF_R27, 0x3); /* set led open drain enable */ RTMP_IO_READ32(pAd, OPT_14, &data); data |= 0x01; RTMP_IO_WRITE32(pAd, OPT_14, data); /* set default antenna as main */ if (pAd->RfIcType == RFIC_3020) AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt); /* add by johnli, RF power sequence setup, load RF normal operation-mode setup */ RT30xxLoadRFNormalModeSetup(pAd); } }
/* this abstract layer is to hide these difference. */ static void ChgMacLedCfg( IN PRTMP_ADAPTER pAd) { LED_CFG_T LedCfgBuf; BYTE DataTxActivity, BeaconTxActivity; PSWMCU_LED_CONTROL pSWMCULedCntl = &pAd->LedCntl.SWMCULedCntl; PLED_OPERATION_MODE pCurrentLedCfg = &pAd->LedCntl.SWMCULedCntl.CurrentLedCfg; /* ** MCU_INT_STA (offset: 0x0414) ** bit 1: MTX2_INT, TX2Q to MAC frame transfer complete interrupt. ** bit 2: MTX1_INT, TX1Q to MAC frame transfer complete interrupt. ** bit 3: MTX0_INT, TX0Q to MAC frame transfer complete interrupt. */ if (TX_TRAFFIC_EXIST(pAd)) /* Check if there is Tx Traffic */ DataTxActivity = 1; else DataTxActivity = 0; /* Check if there are beacon */ BeaconTxActivity = BEN_TC_ACT(pAd); /* Clear Tx and beacon Tx complete interrupt */ RTMP_IO_WRITE32(pAd, MCU_INT_STATUS, 0x1e); RTMP_IO_READ32(pAd, MAC_LED_CFG, &LedCfgBuf.word); /* For backward compatible issue, * LedActMode: 0: None, 1: Solid ON, 2: Blink (data/mgr), 3: Blink (data,mgr,beacon) * =>Solid off = solid on + high polarity */ #ifdef RT5350 //#if defined(RT5350) || defined(RT6352) LedCfgBuf.field.LED_POL = !pCurrentLedCfg->field.LedActPolarity; #else LedCfgBuf.field.LED_POL = pCurrentLedCfg->field.LedActPolarity; #endif if(pSWMCULedCntl->LedBlinkTimer!=0) pSWMCULedCntl->LedBlinkTimer--; else pSWMCULedCntl->LedBlinkTimer = 0xff; /* LED Act. connect to G_LED. */ if (pSWMCULedCntl->LedParameter.LedMode == LED_MODE_8SEC_SCAN && pSWMCULedCntl->BlinkFor8sTimer) { UINT8 LedPolarity = pCurrentLedCfg->field.LedActPolarity ? 0 : 3; LedCfgBuf.field.G_LED_MODE = GetBitX(pSWMCULedCntl->LedBlinkTimer, 0) ? LedPolarity : ~LedPolarity; pSWMCULedCntl->BlinkFor8sTimer--; } else if (pCurrentLedCfg->field.LedActMode == MCU_LED_ACT_OFF) { LedCfgBuf.field.G_LED_MODE = pCurrentLedCfg->field.LedActPolarity ? MAC_LED_ON : MAC_LED_OFF; } else if (pCurrentLedCfg->field.LedActMode == MCU_LED_ACT_SOLID_ON) { LedCfgBuf.field.G_LED_MODE = pCurrentLedCfg->field.LedActPolarity ? MAC_LED_OFF : MAC_LED_ON; } else if ((DataTxActivity && pCurrentLedCfg->field.LedActMode > MCU_LED_ACT_SOLID_ON) /* Data packet transmited. */ || (BeaconTxActivity && pCurrentLedCfg->field.LedActMode == MCU_LED_ACT_BLINK_UPON_TX_DATA_MNG_BEN)) /* Beacon frame transmited. */ { LedCfgBuf.field.G_LED_MODE = GetBitX(pSWMCULedCntl->LedBlinkTimer, 0) ? MAC_LED_ON : MAC_LED_OFF; } else if (!DataTxActivity && !BeaconTxActivity) { if (pCurrentLedCfg->field.LedActModeNoTx == 0) /* solid on when no tx. */ LedCfgBuf.field.G_LED_MODE = pCurrentLedCfg->field.LedActPolarity ? MAC_LED_OFF : MAC_LED_ON; else /* slow blink. */ LedCfgBuf.field.G_LED_MODE = GetBitX(pSWMCULedCntl->LedBlinkTimer, 4) ? MAC_LED_ON : MAC_LED_OFF; } /* LED G. connect to Y_LED. */ if (pCurrentLedCfg->field.LedGMode == MCU_LED_G_FAST_BLINK) LedCfgBuf.field.Y_LED_MODE = GetBitX(pSWMCULedCntl->LedBlinkTimer, 0) ? MAC_LED_ON : MAC_LED_OFF; else if (pCurrentLedCfg->field.LedGMode == MCU_LED_G_SLOW_BLINK) LedCfgBuf.field.Y_LED_MODE = GetBitX(pSWMCULedCntl->LedBlinkTimer, 4) ? MAC_LED_ON : MAC_LED_OFF; else if (pCurrentLedCfg->field.LedGMode == MCU_LED_G_SOLID_ON) LedCfgBuf.field.Y_LED_MODE = pCurrentLedCfg->field.LedGPolarity ? MAC_LED_OFF : MAC_LED_ON; else /* dark */ LedCfgBuf.field.Y_LED_MODE = pCurrentLedCfg->field.LedGPolarity ? MAC_LED_ON : MAC_LED_OFF; /* LED A. connect to R_LED. */ if (pCurrentLedCfg->field.LedAMode == MCU_LED_A_FAST_BLINK) LedCfgBuf.field.R_LED_MODE = GetBitX(pSWMCULedCntl->LedBlinkTimer, 0) ? MAC_LED_ON : MAC_LED_OFF; else if (pCurrentLedCfg->field.LedAMode == MCU_LED_A_SLOW_BLINK) LedCfgBuf.field.R_LED_MODE = GetBitX(pSWMCULedCntl->LedBlinkTimer, 4) ? MAC_LED_ON : MAC_LED_OFF; else if (pCurrentLedCfg->field.LedAMode == MCU_LED_A_SOLID_ON) LedCfgBuf.field.R_LED_MODE = pCurrentLedCfg->field.LedAPolarity ? MAC_LED_OFF : MAC_LED_ON; else LedCfgBuf.field.R_LED_MODE = pCurrentLedCfg->field.LedAPolarity ? MAC_LED_ON : MAC_LED_OFF; if ((pSWMCULedCntl->bWlanLed) && !RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF)) { RTMP_IO_WRITE32(pAd, MAC_LED_CFG, LedCfgBuf.word); } else { { RTMP_IO_WRITE32(pAd, MAC_LED_CFG, 0); } } return; }
/* ======================================================================== Routine Description: Open raxx interface. Arguments: *net_dev the raxx interface pointer Return Value: 0 Open OK otherwise Open Fail Note: ======================================================================== */ int rt28xx_open(IN PNET_DEV dev) { struct net_device * net_dev = (struct net_device *)dev; PRTMP_ADAPTER pAd = NULL; int retval = 0; //POS_COOKIE pObj; GET_PAD_FROM_NET_DEV(pAd, net_dev); // Sanity check for pAd if (pAd == NULL) { /* if 1st open fail, pAd will be free; So the net_dev->priv will be NULL in 2rd open */ return -1; } #ifdef CONFIG_APSTA_MIXED_SUPPORT if (pAd->OpMode == OPMODE_AP) { CW_MAX_IN_BITS = 6; } else if (pAd->OpMode == OPMODE_STA) { CW_MAX_IN_BITS = 10; } #endif // CONFIG_APSTA_MIXED_SUPPORT // #if WIRELESS_EXT >= 12 if (RT_DEV_PRIV_FLAGS_GET(net_dev) == INT_MAIN) { #ifdef CONFIG_APSTA_MIXED_SUPPORT if (pAd->OpMode == OPMODE_AP) net_dev->wireless_handlers = (struct iw_handler_def *) &rt28xx_ap_iw_handler_def; #endif // CONFIG_APSTA_MIXED_SUPPORT // } #endif // WIRELESS_EXT >= 12 // // Request interrupt service routine for PCI device // register the interrupt routine with the os /* AP Channel auto-selection will be run in rt28xx_init(), so we must reqister IRQ hander here. */ RtmpOSIRQRequest(net_dev); // Init IRQ parameters stored in pAd RTMP_IRQ_INIT(pAd); // Chip & other init if (rt28xx_init(pAd, mac, hostname) == FALSE) goto err; #ifdef LINUX #ifdef RT_CFG80211_SUPPORT RT_CFG80211_REINIT(pAd); RT_CFG80211_CRDA_REG_RULE_APPLY(pAd); #endif // RT_CFG80211_SUPPORT // #endif // LINUX // // Enable Interrupt RTMP_IRQ_ENABLE(pAd); // Now Enable RxTx RTMPEnableRxTx(pAd); RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_START_UP); { UINT32 reg = 0; RTMP_IO_READ32(pAd, 0x1300, ®); // clear garbage interrupts if (reg); DBGPRINT(RT_DEBUG_TRACE, ("0x1300 = %08x\n", reg)); } { // u32 reg; // UINT8 byte; // u16 tmp; // RTMP_IO_READ32(pAd, XIFS_TIME_CFG, ®); // tmp = 0x0805; // reg = (reg & 0xffff0000) | tmp; // RTMP_IO_WRITE32(pAd, XIFS_TIME_CFG, reg); } #ifdef CONFIG_AP_SUPPORT #ifdef BG_FT_SUPPORT BG_FTPH_Init(); #endif // BG_FT_SUPPORT // #endif // CONFIG_AP_SUPPORT // #ifdef VENDOR_FEATURE2_SUPPORT printk("Number of Packet Allocated in open = %d\n", pAd->NumOfPktAlloc); printk("Number of Packet Freed in open = %d\n", pAd->NumOfPktFree); #endif // VENDOR_FEATURE2_SUPPORT // return (retval); err: //+++Add by shiang, move from rt28xx_init() to here. RtmpOSIRQRelease(net_dev); //---Add by shiang, move from rt28xx_init() to here. return (-1); } /* End of rt28xx_open */
VOID NICInitRT3370RFRegisters(IN PRTMP_ADAPTER pAd) { INT i; UINT8 RfReg = 0; UINT32 data; CHAR bbpreg; /* Driver must read EEPROM to get RfIcType before initial RF registers*/ /* Initialize RF register to default value*/ /* Init RF calibration*/ /* Driver should toggle RF R30 bit7 before init RF registers*/ RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RfReg); RfReg |= 0x80; RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg); RTMPusecDelay(1000); RfReg &= 0x7F; RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg); for (i = 0; i < RT3370_NUM_RF_REG_PARMS; i++) { RT30xxWriteRFRegister(pAd, RT3370_RFRegTable[i].Register, RT3370_RFRegTable[i].Value); } /* Driver should set RF R6 bit6 on before init RF registers */ RT30xxReadRFRegister(pAd, RF_R06, (PUCHAR)&RfReg); RfReg |= 0x40; RT30xxWriteRFRegister(pAd, RF_R06, (UCHAR)RfReg); /* RT3071 version E has fixed this issue*/ if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211)) { /* patch tx EVM issue temporarily*/ RTUSBReadMACRegister(pAd, LDO_CFG0, &data); data = ((data & 0xE0FFFFFF) | 0x0D000000); RTUSBWriteMACRegister(pAd, LDO_CFG0, data); } else { /* patch CCK ok, OFDM failed issue, just toggle and restore LDO_CFG0.*/ RTUSBReadMACRegister(pAd, LDO_CFG0, &data); data = ((data & 0xE0FFFFFF) | 0x0D000000); RTUSBWriteMACRegister(pAd, LDO_CFG0, data); RTMPusecDelay(1000); data = ((data & 0xE0FFFFFF) | 0x01000000); RTUSBWriteMACRegister(pAd, LDO_CFG0, data); } /* patch LNA_PE_G1 failed issue*/ RTMP_IO_READ32(pAd, GPIO_SWITCH, &data); data &= ~(0x20); RTMP_IO_WRITE32(pAd, GPIO_SWITCH, data); if (IS_RT3390(pAd)) /* Disable RF filter calibration*/ { pAd->Mlme.CaliBW20RfR24 = BW20RFR24; pAd->Mlme.CaliBW40RfR24 = BW40RFR24; pAd->Mlme.CaliBW20RfR31 = BW20RFR31; pAd->Mlme.CaliBW40RfR31 = BW40RFR31; } else { /*For RF filter Calibration*/ /*RTMPFilterCalibration(pAd);*/ } /* set led open drain enable*/ RTMP_IO_READ32(pAd, OPT_14, &data); data |= 0x01; RTMP_IO_WRITE32(pAd, OPT_14, data); /* set default antenna as main*/ if (pAd->RfIcType == RFIC_3320) AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt); /* From RT3071 Power Sequence v1.1 document, the Normal Operation Setting Registers as follow : BBP_R138 / RF_R1 / RF_R15 / RF_R17 / RF_R20 / RF_R21. */ /* add by johnli, RF power sequence setup, load RF normal operation-mode setup*/ RT33xxLoadRFNormalModeSetup(pAd); }
/* ======================================================================== Routine Description: Open raxx interface. Arguments: *net_dev the raxx interface pointer Return Value: 0 Open OK otherwise Open Fail Note: ======================================================================== */ int rt28xx_open(IN PNET_DEV dev) { struct net_device * net_dev = (struct net_device *)dev; PRTMP_ADAPTER pAd = RTMP_OS_NETDEV_GET_PRIV(net_dev); int retval = 0; //POS_COOKIE pObj; // Sanity check for pAd if (pAd == NULL) { /* if 1st open fail, pAd will be free; So the net_dev->priv will be NULL in 2rd open */ return -1; } #ifdef CONFIG_APSTA_MIXED_SUPPORT if (pAd->OpMode == OPMODE_AP) { CW_MAX_IN_BITS = 6; } else if (pAd->OpMode == OPMODE_STA) { CW_MAX_IN_BITS = 10; } #endif // CONFIG_APSTA_MIXED_SUPPORT // #if WIRELESS_EXT >= 12 if (net_dev->priv_flags == INT_MAIN) { #ifdef CONFIG_APSTA_MIXED_SUPPORT if (pAd->OpMode == OPMODE_AP) net_dev->wireless_handlers = (struct iw_handler_def *) &rt28xx_ap_iw_handler_def; #endif // CONFIG_APSTA_MIXED_SUPPORT // #ifdef CONFIG_STA_SUPPORT if (pAd->OpMode == OPMODE_STA) net_dev->wireless_handlers = (struct iw_handler_def *) &rt28xx_iw_handler_def; #endif // CONFIG_STA_SUPPORT // } #endif // WIRELESS_EXT >= 12 // // Request interrupt service routine for PCI device // register the interrupt routine with the os RTMP_IRQ_REQUEST(net_dev); // Init IRQ parameters stored in pAd RTMP_IRQ_INIT(pAd); // Chip & other init if (rt28xx_init(pAd, mac, hostname) == FALSE) goto err; #ifdef CONFIG_STA_SUPPORT #endif // CONFIG_STA_SUPPORT // // Enable Interrupt RTMP_IRQ_ENABLE(pAd); // Now Enable RxTx RTMPEnableRxTx(pAd); RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_START_UP); { UINT32 reg = 0; RTMP_IO_READ32(pAd, 0x1300, ®); // clear garbage interrupts printk("0x1300 = %08x\n", reg); } { // u32 reg; // UINT8 byte; // u16 tmp; // RTMP_IO_READ32(pAd, XIFS_TIME_CFG, ®); // tmp = 0x0805; // reg = (reg & 0xffff0000) | tmp; // RTMP_IO_WRITE32(pAd, XIFS_TIME_CFG, reg); } #ifdef CONFIG_STA_SUPPORT #ifdef RTMP_MAC_PCI IF_DEV_CONFIG_OPMODE_ON_STA(pAd) RTMPInitPCIeLinkCtrlValue(pAd); #endif // RTMP_MAC_PCI // #endif // CONFIG_STA_SUPPORT // return (retval); err: //+++Add by shiang, move from rt28xx_init() to here. RTMP_IRQ_RELEASE(net_dev); //---Add by shiang, move from rt28xx_init() to here. return (-1); } /* End of rt28xx_open */