VOID RT28xxUsbMlmeRadioOn( IN PRTMP_ADAPTER pAd) { DBGPRINT(RT_DEBUG_TRACE,("RT28xxUsbMlmeRadioOn()\n")); if (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF)) return; #ifdef CONFIG_STA_SUPPORT IF_DEV_CONFIG_OPMODE_ON_STA(pAd) { AsicSendCommandToMcu(pAd, 0x31, 0xff, 0x00, 0x00); RTMPusecDelay(10000); } #endif // CONFIG_STA_SUPPORT // NICResetFromError(pAd); // Enable Tx/Rx RTMPEnableRxTx(pAd); // Clear Radio off flag RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF); #ifdef CONFIG_STA_SUPPORT IF_DEV_CONFIG_OPMODE_ON_STA(pAd) RTUSBBulkReceive(pAd); #endif // CONFIG_STA_SUPPORT // // Set LED RTMPSetLED(pAd, LED_RADIO_ON); }
VOID RtmpDmaEnable( IN PRTMP_ADAPTER pAd, IN INT Enable) { BOOLEAN value; ULONG WaitCnt; WPDMA_GLO_CFG_STRUC GloCfg; value = Enable > 0 ? 1 : 0; /* check if DMA is in busy mode or not. */ WaitCnt = 0; while (TxDmaBusy(pAd) || RxDmaBusy(pAd)) { RTMPusecDelay(10); if (WaitCnt++ > 100) break; } RTMP_IO_READ32(pAd, WPDMA_GLO_CFG, &GloCfg.word); /* disable DMA */ GloCfg.field.EnableTxDMA = value; GloCfg.field.EnableRxDMA = value; RTMP_IO_WRITE32(pAd, WPDMA_GLO_CFG, GloCfg.word); /* abort all TX rings */ RtmpOsMsDelay(5); return; }
VOID RtmpDmaEnable( IN PRTMP_ADAPTER pAd, IN INT Enable) { BOOLEAN value; ULONG WaitCnt; USB_DMA_CFG_STRUC UsbCfg; value = Enable > 0 ? 1 : 0; /* check DMA is in busy mode. */ WaitCnt = 0; while (TxDmaBusy(pAd) || RxDmaBusy(pAd)) { RTMPusecDelay(10); if (WaitCnt++ > 100) break; } RTMP_IO_READ32(pAd, USB_DMA_CFG, &UsbCfg.word); /* disable DMA */ UsbCfg.field.TxBulkEn = value; UsbCfg.field.RxBulkEn = value; RTMP_IO_WRITE32(pAd, USB_DMA_CFG, UsbCfg.word); /* abort all TX rings */ RtmpOsMsDelay(5); return; }
/* ======================================================================== Routine Description: Write Firmware to NIC. Arguments: Return Value: IRQL = Note: ======================================================================== */ NTSTATUS RTUSBFirmwareWrite( IN PRTMP_ADAPTER pAd, IN PUCHAR pFwImage, IN ULONG FwLen) { UINT32 MacReg; NTSTATUS Status; // ULONG i; USHORT writeLen; Status = RTUSBReadMACRegister(pAd, MAC_CSR0, &MacReg); writeLen = FwLen; RTUSBMultiWrite(pAd, FIRMWARE_IMAGE_BASE, pFwImage, writeLen); Status = RTUSBWriteMACRegister(pAd, 0x7014, 0xffffffff); Status = RTUSBWriteMACRegister(pAd, 0x701c, 0xffffffff); Status = RTUSBFirmwareRun(pAd); #ifdef RT30xx RTMPusecDelay(10000); RTUSBWriteMACRegister(pAd,H2M_MAILBOX_CSR,0); AsicSendCommandToMcu(pAd, 0x72, 0x00, 0x00, 0x00);//reset rf by MCU supported by new firmware #endif return Status; }
INT WaitForAsicReady( IN RTMP_ADAPTER *pAd) { UINT32 mac_val = 0, reg = MAC_CSR0; int idx = 0; #ifdef RT3290 if (IS_RT3290(pAd)) reg = ASIC_VERSION; #endif /* RT3290 */ do { if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)) return FALSE; RTMP_IO_READ32(pAd, reg, &mac_val); if ((mac_val != 0x00) && (mac_val != 0xFFFFFFFF)) return TRUE; RTMPusecDelay(10); } while (idx++ < 100); DBGPRINT(RT_DEBUG_ERROR, ("%s(0x%x):AsicNotReady!\n", __FUNCTION__, mac_val)); return TRUE; }
/* ========================================================================== Description: IRQL = PASSIVE_LEVEL ========================================================================== */ VOID TDLS_MlmeChannelSwitchRspAction( IN PRTMP_ADAPTER pAd, IN MLME_QUEUE_ELEM *Elem) { PMLME_TDLS_CH_SWITCH_STRUCT pMlmeChSwitchRsp = NULL; NDIS_STATUS NStatus = NDIS_STATUS_SUCCESS; PRT_802_11_TDLS pTdls = NULL; int LinkId = 0xff; DBGPRINT(RT_DEBUG_WARN,("TDLS ===> TDLS_MlmeChannelSwitchRspAction() \n")); pMlmeChSwitchRsp = (PMLME_TDLS_CH_SWITCH_STRUCT)Elem->Msg; if (INFRA_ON(pAd)) { // Drop not within my TDLS Table that created before ! LinkId = TDLS_SearchLinkId(pAd, pMlmeChSwitchRsp->PeerMacAddr); if (LinkId == -1 || LinkId == MAX_NUM_OF_TDLS_ENTRY) { DBGPRINT(RT_DEBUG_OFF,("TDLS - TDLS_MlmeChannelSwitchRspAction() can not find the LinkId!\n")); return; } /* Point to the current Link ID */ pTdls = &pAd->StaCfg.TdlsInfo.TDLSEntry[LinkId]; /* Build TDLS channel switch Request Frame */ NStatus = TDLS_ChannelSwitchRspAction(pAd, pTdls, pTdls->ChSwitchTime, pTdls->ChSwitchTimeout, 0, (RTMP_TDLS_SPECIFIC_CS_RSP_NOACK + RTMP_TDLS_SPECIFIC_HCCA)); if (NStatus != NDIS_STATUS_SUCCESS) { DBGPRINT(RT_DEBUG_ERROR,("TDLS - TDLS_MlmeChannelSwitchRspAction() Build Channel Switch Response Fail !!!\n")); } else { RTMPusecDelay(300); NdisGetSystemUpTime(&pAd->StaCfg.TdlsGoBackStartTime); RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_TDLS_DOING_CHANNEL_SWITCH); if (pAd->CommonCfg.CentralChannel > pAd->CommonCfg.Channel) TDLS_InitChannelRelatedValue(pAd, pAd->CommonCfg.Channel, EXTCHA_ABOVE); else if (pAd->CommonCfg.CentralChannel < pAd->CommonCfg.Channel) TDLS_InitChannelRelatedValue(pAd, pAd->CommonCfg.Channel, EXTCHA_BELOW); else TDLS_InitChannelRelatedValue(pAd, pAd->CommonCfg.Channel, EXTCHA_NONE); TDLS_EnablePktChannel(pAd, TDLS_FIFO_ALL); RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_TDLS_DOING_CHANNEL_SWITCH); DBGPRINT(RT_DEBUG_WARN,("TDLS <=== TDLS_MlmeChannelSwitchRspAction() \n")); } } else { DBGPRINT(RT_DEBUG_ERROR,("TDLS - TDLS_MlmeChannelSwitchRspAction() TDLS only support infra mode !!!\n")); } return; }
VOID RT28xxUsbMlmeRadioOn( IN PRTMP_ADAPTER pAd) { DBGPRINT(RT_DEBUG_TRACE,("RT28xxUsbMlmeRadioOn()\n")); if (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF)) return; AsicSendCommandToMcu(pAd, 0x31, 0xff, 0x00, 0x02); RTMPusecDelay(10000); NICResetFromError(pAd); RTMPEnableRxTx(pAd); #ifdef RT3070 if (IS_RT3071(pAd)) { RT30xxReverseRFSleepModeSetup(pAd); } #endif RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF); RTUSBBulkReceive(pAd); RTMPSetLED(pAd, LED_RADIO_ON); }
int RtmpAsicLoadFirmware(struct rt_rtmp_adapter *pAd) { const struct firmware *fw; int Status = NDIS_STATUS_SUCCESS; unsigned long Index; u32 MacReg = 0; fw = rtmp_get_firmware(pAd); if (!fw) return NDIS_STATUS_FAILURE; RTMP_WRITE_FIRMWARE(pAd, fw->data, FIRMWAREIMAGE_LENGTH); /* check if MCU is ready */ Index = 0; do { RTMP_IO_READ32(pAd, PBF_SYS_CTRL, &MacReg); if (MacReg & 0x80) break; RTMPusecDelay(1000); } while (Index++ < 1000); if (Index > 1000) { DBGPRINT(RT_DEBUG_ERROR, ("NICLoadFirmware: MCU is not ready\n")); Status = NDIS_STATUS_FAILURE; } DBGPRINT(RT_DEBUG_TRACE, ("<=== %s (status=%d)\n", __func__, Status)); return Status; }
INT rtmp_bbp_set_bw(struct _RTMP_ADAPTER *pAd, INT bw) { UCHAR val, old_val = 0; BOOLEAN bstop = FALSE; UINT32 Data, MTxCycle, macStatus; if (bw != pAd->CommonCfg.BBPCurrentBW) bstop = TRUE; if (bstop) { /* Disable MAC Tx/Rx */ RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Data); Data &= (~0x0C); RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Data); /* Check MAC Tx/Rx idle */ for (MTxCycle = 0; MTxCycle < 10000; MTxCycle++) { RTMP_IO_READ32(pAd, MAC_STATUS_CFG, &macStatus); if (macStatus & 0x3) RTMPusecDelay(50); else break; } } RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &old_val); val = (old_val & (~0x18)); switch (bw) { case BW_20: val &= (~0x18); break; case BW_40: val |= (0x10); break; case BW_10: val |= 0x08; break; } if (val != old_val) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, val); } if (bstop) { /* Enable MAC Tx/Rx */ RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Data); Data |= 0x0C; RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Data); } pAd->CommonCfg.BBPCurrentBW = bw; return TRUE; }
INT RtmpChipOpsEepromHook( IN RTMP_ADAPTER *pAd, IN INT infType) { RTMP_CHIP_OP *pChipOps = &pAd->chipOps; #ifdef RT30xx #ifdef RTMP_EFUSE_SUPPORT UINT32 eFuseCtrl, MacCsr0; int index; index = 0; do { RTMP_IO_READ32(pAd, MAC_CSR0, &MacCsr0); pAd->MACVersion = MacCsr0; if ((pAd->MACVersion != 0x00) && (pAd->MACVersion != 0xFFFFFFFF)) break; RTMPusecDelay(10); } while (index++ < 100); pAd->bUseEfuse=FALSE; RTMP_IO_READ32(pAd, EFUSE_CTRL, &eFuseCtrl); pAd->bUseEfuse = ( (eFuseCtrl & 0x80000000) == 0x80000000) ? 1 : 0; if(pAd->bUseEfuse) { pChipOps->eeinit = eFuse_init; pChipOps->eeread = rtmp_ee_efuse_read16; pChipOps->eewrite = rtmp_ee_efuse_write16; DBGPRINT(RT_DEBUG_TRACE, ("NVM is EFUSE\n")); return 0 ; } else { pAd->bFroceEEPROMBuffer = FALSE; DBGPRINT(RT_DEBUG_TRACE, ("NVM is EEPROM\n")); } #endif // RTMP_EFUSE_SUPPORT // #endif // RT30xx // switch(infType) { #ifdef RTMP_USB_SUPPORT case RTMP_DEV_INF_USB: pChipOps->eeinit = NULL; pChipOps->eeread = RTUSBReadEEPROM16; pChipOps->eewrite = RTUSBWriteEEPROM16; break; #endif // RTMP_USB_SUPPORT // default: DBGPRINT(RT_DEBUG_ERROR, ("RtmpChipOpsEepromHook() failed!\n")); break; } return 0; }
// IRQL = PASSIVE_LEVEL static inline VOID RaiseClock( IN PRTMP_ADAPTER pAd, IN UINT32 *x) { *x = *x | EESK; RTMP_IO_WRITE32(pAd, E2PROM_CSR, *x); RTMPusecDelay(1); // Max frequency = 1MHz in Spec. definition }
// IRQL = PASSIVE_LEVEL static inline VOID LowerClock( IN PRTMP_ADAPTER pAd, IN UINT32 *x) { *x = *x & ~EESK; RTMP_IO_WRITE32(pAd, E2PROM_CSR, *x); RTMPusecDelay(1); }
VOID RTMP_EEPROM_WRITE16( IN PRTMP_ADAPTER pAd, IN USHORT Offset, IN USHORT Data) { UINT32 x; #ifdef RT2870 if (pAd->NicConfig2.field.AntDiversity) { pAd->EepromAccess = TRUE; } #endif Offset /= 2; EWEN(pAd); // reset bits and set EECS RTMP_IO_READ32(pAd, E2PROM_CSR, &x); x &= ~(EEDI | EEDO | EESK); x |= EECS; RTMP_IO_WRITE32(pAd, E2PROM_CSR, x); // patch can not access e-Fuse issue if (!IS_RT3090(pAd)) { // kick a pulse RaiseClock(pAd, &x); LowerClock(pAd, &x); } // output the read_opcode ,register number and data in that order ShiftOutBits(pAd, EEPROM_WRITE_OPCODE, 3); ShiftOutBits(pAd, Offset, pAd->EEPROMAddressNum); ShiftOutBits(pAd, Data, 16); // 16-bit access // read DO status RTMP_IO_READ32(pAd, E2PROM_CSR, &x); EEpromCleanup(pAd); RTMPusecDelay(10000); //delay for twp(MAX)=10ms EWDS(pAd); EEpromCleanup(pAd); #ifdef RT2870 // Antenna and EEPROM access are both using EESK pin, // Therefor we should avoid accessing EESK at the same time // Then restore antenna after EEPROM access if ((pAd->NicConfig2.field.AntDiversity) || (pAd->RfIcType == RFIC_3020)) { pAd->EepromAccess = FALSE; AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt); } #endif }
/* ======================================================================== Routine Description: Close kernel threads. Arguments: *pAd the raxx interface data pointer Return Value: NONE Note: ======================================================================== */ VOID RtmpMgmtTaskExit( IN RTMP_ADAPTER *pAd) { INT ret; RTMP_OS_TASK *pTask; /* Sleep 50 milliseconds so pending io might finish normally */ RTMPusecDelay(50000); /* We want to wait until all pending receives and sends to the */ /* device object. We cancel any */ /* irps. Wait until sends and receives have stopped. */ RTUSBCancelPendingIRPs(pAd); /* We need clear timerQ related structure before exits of the timer thread. */ RtmpTimerQExit(pAd); /* Terminate Mlme Thread */ pTask = &pAd->mlmeTask; ret = RtmpOSTaskKill(pTask); if (ret == NDIS_STATUS_FAILURE) { /* DBGPRINT(RT_DEBUG_ERROR, ("%s: kill task(%s) failed!\n", */ /* RTMP_OS_NETDEV_GET_DEVNAME(pAd->net_dev), pTask->taskName)); */ DBGPRINT(RT_DEBUG_ERROR, ("kill mlme task failed!\n")); } /* Terminate cmdQ thread */ pTask = &pAd->cmdQTask; RTMP_OS_TASK_LEGALITY(pTask) { NdisAcquireSpinLock(&pAd->CmdQLock); pAd->CmdQ.CmdQState = RTMP_TASK_STAT_STOPED; NdisReleaseSpinLock(&pAd->CmdQLock); /*RTUSBCMDUp(&pAd->cmdQTask); */ ret = RtmpOSTaskKill(pTask); if (ret == NDIS_STATUS_FAILURE) { /* DBGPRINT(RT_DEBUG_ERROR, ("%s: kill task(%s) failed!\n", */ /* RTMP_OS_NETDEV_GET_DEVNAME(pAd->net_dev), pTask->taskName)); */ DBGPRINT(RT_DEBUG_ERROR, ("kill command task failed!\n")); } pAd->CmdQ.CmdQState = RTMP_TASK_STAT_UNKNOWN; } /* Terminate timer thread */ pTask = &pAd->timerTask; ret = RtmpOSTaskKill(pTask); if (ret == NDIS_STATUS_FAILURE) { /* DBGPRINT(RT_DEBUG_ERROR, ("%s: kill task(%s) failed!\n", */ /* RTMP_OS_NETDEV_GET_DEVNAME(pAd->net_dev), pTask->taskName)); */ DBGPRINT(RT_DEBUG_ERROR, ("kill timer task failed!\n")); } }
static VOID P2PDiscListenAction( IN PRTMP_ADAPTER pAd, IN MLME_QUEUE_ELEM *Elem) { P2P_DISC_STATE *pCurrState = &(pAd->P2pCfg.DiscCurrentState); PRT_P2P_CONFIG pP2PCtrl = &pAd->P2pCfg; if (pP2PCtrl->P2pCounter.bStartScan == TRUE) pP2PCtrl->P2pCounter.ListenInterval = (RandomByte(pAd) % 3) + pP2PCtrl->P2pCounter.ListenIntervalBias; /* 1~3 */ else pP2PCtrl->P2pCounter.ListenInterval = 5; /* ExtListenInterval is in ms. So /100 */ if (IS_P2P_SUPPORT_EXT_LISTEN(pAd)) pP2PCtrl->P2pCounter.ListenInterval = pP2PCtrl->ExtListenPeriod/100; if (pAd->LatchRfRegs.Channel != pP2PCtrl->ListenChannel) { UINT32 Data = 0, macStatus; UINT32 MTxCycle, MRxCycle; UCHAR BBPValue = 0; /* Disable MAC Tx/Rx */ RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Data); Data &= (~0x0C); RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Data); /* Check MAC Tx/Rx idle */ for (MTxCycle = 0; MTxCycle < 10000; MTxCycle++) { RTMP_IO_READ32(pAd, MAC_STATUS_CFG, &macStatus); if (macStatus & 0x3) RTMPusecDelay(50); else break; } AsicSwitchChannel(pAd, pP2PCtrl->ListenChannel, FALSE); AsicLockChannel(pAd, pP2PCtrl->ListenChannel); /* Let BBP register at 20MHz */ RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue); BBPValue &= (~0x18); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue); /* Enable MAC Tx/Rx */ RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Data); Data |= 0x0C; RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Data); } DBGPRINT(RT_DEBUG_TRACE, ("%s:: Listen interval - %d\n", __FUNCTION__, pP2PCtrl->P2pCounter.ListenInterval)); pP2PCtrl->P2pCounter.bListen = TRUE; *pCurrState = P2P_DISC_LISTEN; }
/* ======================================================================== Routine Description: Arguments: Return Value: IRQL = Note: ======================================================================== */ VOID eFusePhysicalReadRegisters( IN PRTMP_ADAPTER pAd, IN USHORT Offset, IN USHORT Length, OUT USHORT* pData) { EFUSE_CTRL_STRUC eFuseCtrlStruc; int i; USHORT efuseDataOffset; UINT32 data; RTMP_IO_READ32(pAd, EFUSE_CTRL, (PUINT32) &eFuseCtrlStruc); //Step0. Write 10-bit of address to EFSROM_AIN (0x580, bit25:bit16). The address must be 16-byte alignment. eFuseCtrlStruc.field.EFSROM_AIN = Offset & 0xfff0; //Step1. Write EFSROM_MODE (0x580, bit7:bit6) to 1. //Read in physical view eFuseCtrlStruc.field.EFSROM_MODE = 1; //Step2. Write EFSROM_KICK (0x580, bit30) to 1 to kick-off physical read procedure. eFuseCtrlStruc.field.EFSROM_KICK = 1; NdisMoveMemory(&data, &eFuseCtrlStruc, 4); RTMP_IO_WRITE32(pAd, EFUSE_CTRL, data); //Step3. Polling EFSROM_KICK(0x580, bit30) until it become 0 again. i = 0; while(i < 100) { RTMP_IO_READ32(pAd, EFUSE_CTRL, (PUINT32) &eFuseCtrlStruc); if(eFuseCtrlStruc.field.EFSROM_KICK == 0) break; RTMPusecDelay(2); i++; } //Step4. Read 16-byte of data from EFUSE_DATA0-3 (0x59C-0x590) //Because the size of each EFUSE_DATA is 4 Bytes, the size of address of each is 2 bits. //The previous 2 bits is the EFUSE_DATA number, the last 2 bits is used to decide which bytes //Decide which EFUSE_DATA to read //590:F E D C //594:B A 9 8 //598:7 6 5 4 //59C:3 2 1 0 efuseDataOffset = EFUSE_DATA3 - (Offset & 0xC) ; RTMP_IO_READ32(pAd, efuseDataOffset, &data); data = data >> (8*(Offset & 0x3)); NdisMoveMemory(pData, &data, Length); }
/* ========================================================================== Description: IRQL = PASSIVE_LEVEL ========================================================================== */ VOID TDLS_ChannelSwitchTimeOutAction( IN PVOID SystemSpecific1, IN PVOID FunctionContext, IN PVOID SystemSpecific2, IN PVOID SystemSpecific3) { PRT_802_11_TDLS pTDLS = (PRT_802_11_TDLS)FunctionContext; PRTMP_ADAPTER pAd = pTDLS->pAd; BOOLEAN TimerCancelled; DBGPRINT(RT_DEBUG_WARN, ("TDLS - Failed to wait for channel switch, terminate the channel switch procedure (%02x:%02x:%02x:%02x:%02x:%02x)\n", pTDLS->MacAddr[0], pTDLS->MacAddr[1], pTDLS->MacAddr[2], pTDLS->MacAddr[3], pTDLS->MacAddr[4], pTDLS->MacAddr[5])); { ULONG Now, temp1; NdisGetSystemUpTime(&Now); temp1 = (((Now - pTDLS->ChannelSwitchTimerStartTime) * 1000) / OS_HZ); if (temp1 < (pTDLS->ChSwitchTimeout / 1000)) { RTMPSetTimer(&pTDLS->ChannelSwitchTimeoutTimer, ((pTDLS->ChSwitchTimeout / 1000) - temp1)); return; } if (temp1 < (pTDLS->ChSwitchTimeout / 1000)) { DBGPRINT(RT_DEBUG_OFF, ("Timer = %ld < 11 !!!\n", temp1)); } } RTMPCancelTimer(&pAd->StaCfg.TdlsResponderGoBackBaseChTimer, &TimerCancelled); pAd->StaCfg.bTdlsCurrentDoingChannelSwitchWaitSuccess = FALSE; pAd->StaCfg.bDoingPeriodChannelSwitch = FALSE; RTMPusecDelay(300); NdisGetSystemUpTime(&pAd->StaCfg.TdlsGoBackStartTime); RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_TDLS_DOING_CHANNEL_SWITCH); if (pAd->CommonCfg.CentralChannel > pAd->CommonCfg.Channel) TDLS_InitChannelRelatedValue(pAd, pAd->CommonCfg.Channel, EXTCHA_ABOVE); else if (pAd->CommonCfg.CentralChannel < pAd->CommonCfg.Channel) TDLS_InitChannelRelatedValue(pAd, pAd->CommonCfg.Channel, EXTCHA_BELOW); else TDLS_InitChannelRelatedValue(pAd, pAd->CommonCfg.Channel, EXTCHA_NONE); TDLS_EnablePktChannel(pAd, TDLS_FIFO_ALL); RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_TDLS_DOING_CHANNEL_SWITCH); }
int rtmp_ee_prom_write16( IN PRTMP_ADAPTER pAd, IN USHORT Offset, IN USHORT Data) { UINT32 x; #ifdef RT30xx #endif // RT30xx // Offset /= 2; EWEN(pAd); // reset bits and set EECS RTMP_IO_READ32(pAd, E2PROM_CSR, &x); x &= ~(EEDI | EEDO | EESK); x |= EECS; RTMP_IO_WRITE32(pAd, E2PROM_CSR, x); // patch can not access e-Fuse issue if (!(IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd) || IS_RT3593(pAd))) { // kick a pulse RaiseClock(pAd, &x); LowerClock(pAd, &x); } // output the read_opcode ,register number and data in that order ShiftOutBits(pAd, EEPROM_WRITE_OPCODE, 3); ShiftOutBits(pAd, Offset, pAd->EEPROMAddressNum); ShiftOutBits(pAd, Data, 16); // 16-bit access // read DO status RTMP_IO_READ32(pAd, E2PROM_CSR, &x); EEpromCleanup(pAd); RTMPusecDelay(10000); //delay for twp(MAX)=10ms EWDS(pAd); EEpromCleanup(pAd); #ifdef RT30xx #endif // RT30xx // return NDIS_STATUS_SUCCESS; }
/*************************************************************************** * * PCIe device initialization related procedures. * ***************************************************************************/ static VOID RTMPInitPCIeDevice( IN struct pci_dev *pci_dev, IN PRTMP_ADAPTER pAd) { USHORT device_id; POS_COOKIE pObj; pObj = (POS_COOKIE) pAd->OS_Cookie; pci_read_config_word(pci_dev, PCI_DEVICE_ID, &device_id); device_id = le2cpu16(device_id); pObj->DeviceID = device_id; OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE); if ( #ifdef RT2860 (device_id == NIC2860_PCIe_DEVICE_ID) || (device_id == NIC2790_PCIe_DEVICE_ID) || (device_id == VEN_AWT_PCIe_DEVICE_ID) || #endif // RT2860 // 0) { UINT32 MacCsr0 = 0, Index= 0; do { RTMP_IO_READ32(pAd, MAC_CSR0, &MacCsr0); if ((MacCsr0 != 0x00) && (MacCsr0 != 0xFFFFFFFF)) break; RTMPusecDelay(10); } while (Index++ < 100); // Support advanced power save after 2892/2790. // MAC version at offset 0x1000 is 0x2872XXXX/0x2870XXXX(PCIe, USB, SDIO). if ((MacCsr0&0xffff0000) != 0x28600000) { #ifdef PCIE_PS_SUPPORT OPSTATUS_SET_FLAG(pAd, fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE); #endif // PCIE_PS_SUPPORT // RtmpRaDevCtrlInit(pAd, RTMP_DEV_INF_PCIE); return; } } RtmpRaDevCtrlInit(pAd, RTMP_DEV_INF_PCI); }
VOID FrequencyCalibrationMode(PRTMP_ADAPTER pAd, UINT8 Mode) { UCHAR RFValue = 0; UINT32 PreRFValue = 0; #ifdef MT7601 if (Mode == FREQ_CAL_MODE2) { rlt_rf_write(pAd, RF_BANK0, RF_R12, pAd->FreqCalibrationCtrl.AdaptiveFreqOffset); AndesRFRandomWrite(pAd, 2, RF_BANK0, RF_R04, 0x0A, RF_BANK0, RF_R05, 0x20); rlt_rf_read(pAd, RF_BANK0, RF_R04, &RFValue); RFValue = ((RFValue & ~0x80) | 0x80); /* vcocal_en (initiate VCO calibration (reset after completion)) - It should be at the end of RF configuration. */ rlt_rf_write(pAd, RF_BANK0, RF_R04, RFValue); RTMPusecDelay(2000); } else #endif /* MT7601 */ DBGPRINT(RT_DEBUG_ERROR, ("Unknown FrqCalibration Mode\n")); }
VOID RtmpOsUsbEmptyUrbCheck( IN VOID **ppWait, IN NDIS_SPIN_LOCK *pBulkInLock, IN UCHAR *pPendingRx) { UINT32 i = 0; DECLARE_WAIT_QUEUE_HEAD(unlink_wakeup); DECLARE_WAITQUEUE(wait, current); /* ensure there are no more active urbs. */ add_wait_queue (&unlink_wakeup, &wait); *ppWait = &unlink_wakeup; /* maybe wait for deletions to finish. */ i = 0; /*while((i < 25) && atomic_read(&pAd->PendingRx) > 0) */ while(i < 25) { /* unsigned long IrqFlags; */ RTMP_SEM_LOCK(pBulkInLock); if (*pPendingRx == 0) { RTMP_SEM_UNLOCK(pBulkInLock); break; } RTMP_SEM_UNLOCK(pBulkInLock); #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,9) msleep(UNLINK_TIMEOUT_MS); /*Time in millisecond */ #else RTMPusecDelay(UNLINK_TIMEOUT_MS*1000); /*Time in microsecond */ #endif i++; } *ppWait = NULL; remove_wait_queue (&unlink_wakeup, &wait); }
static VOID RTMPInitPCIeDevice( IN struct pci_dev *pci_dev, IN PRTMP_ADAPTER pAd) { USHORT device_id; POS_COOKIE pObj; pObj = (POS_COOKIE) pAd->OS_Cookie; pci_read_config_word(pci_dev, PCI_DEVICE_ID, &device_id); device_id = le2cpu16(device_id); pObj->DeviceID = device_id; if ( #ifdef RT3090 (device_id == NIC3090_PCIe_DEVICE_ID) || (device_id == NIC3091_PCIe_DEVICE_ID) || (device_id == NIC3092_PCIe_DEVICE_ID) || #endif 0) { UINT32 MacCsr0 = 0, Index= 0; do { RTMP_IO_READ32(pAd, MAC_CSR0, &MacCsr0); if ((MacCsr0 != 0x00) && (MacCsr0 != 0xFFFFFFFF)) break; RTMPusecDelay(10); } while (Index++ < 100); if ((MacCsr0&0xffff0000) != 0x28600000) { OPSTATUS_SET_FLAG(pAd, fOP_STATUS_PCIE_DEVICE); } } }
VOID RTUSBHalt( IN PRTMP_ADAPTER pAd, IN BOOLEAN IsFree) { BOOLEAN TimerCancelled; DBGPRINT(RT_DEBUG_TRACE, "====> RTUSBHalt\n"); // // before set flag fRTMP_ADAPTER_HALT_IN_PROGRESS, // we should send a disassoc frame to our AP. // RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS); RTUSBCleanUpMLMEWaitQueue(pAd); RTUSBCleanUpMLMEBulkOutQueue(pAd); RTMPCancelTimer(&pAd->PortCfg.QuickResponeForRateUpTimer,&TimerCancelled); RTMPCancelTimer(&pAd->RxAnt.RxAntDiversityTimer,&TimerCancelled); // Free MLME stuff MlmeHalt(pAd); // Sleep 50 milliseconds so pending io might finish normally RTMPusecDelay(50000); // We want to wait until all pending receives and sends to the // device object. We cancel any // irps. Wait until sends and receives have stopped. // RTUSBCancelPendingIRPs(pAd); // Free the entire adapter object ReleaseAdapter(pAd, IsFree, FALSE); RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS); }
/*************************************************************************** * * PCIe device initialization related procedures. * ***************************************************************************/ static VOID RTMPInitPCIeDevice( IN struct pci_dev *pci_dev, IN PRTMP_ADAPTER pAd) { USHORT device_id; POS_COOKIE pObj; pObj = (POS_COOKIE) pAd->OS_Cookie; pci_read_config_word(pci_dev, PCI_DEVICE_ID, &device_id); device_id = le2cpu16(device_id); pObj->DeviceID = device_id; if ( #ifdef RT3090 (device_id == NIC3090_PCIe_DEVICE_ID) || (device_id == NIC3091_PCIe_DEVICE_ID) || (device_id == NIC3092_PCIe_DEVICE_ID) || #endif // RT3090 // 0) { UINT32 MacCsr0 = 0, Index= 0; do { RTMP_IO_READ32(pAd, MAC_CSR0, &MacCsr0); if ((MacCsr0 != 0x00) && (MacCsr0 != 0xFFFFFFFF)) break; RTMPusecDelay(10); } while (Index++ < 100); // Support advanced power save after 2892/2790. // MAC version at offset 0x1000 is 0x2872XXXX/0x2870XXXX(PCIe, USB, SDIO). if ((MacCsr0&0xffff0000) != 0x28600000) { OPSTATUS_SET_FLAG(pAd, fOP_STATUS_PCIE_DEVICE); } } }
/*************************************************************************** * * PCIe device initialization related procedures. * ***************************************************************************/ static void RTMPInitPCIeDevice(struct pci_dev *pci_dev, struct rt_rtmp_adapter *pAd) { u16 device_id; struct os_cookie *pObj; pObj = (struct os_cookie *)pAd->OS_Cookie; pci_read_config_word(pci_dev, PCI_DEVICE_ID, &device_id); device_id = le2cpu16(device_id); pObj->DeviceID = device_id; if ( #ifdef RT2860 (device_id == NIC2860_PCIe_DEVICE_ID) || (device_id == NIC2790_PCIe_DEVICE_ID) || (device_id == VEN_AWT_PCIe_DEVICE_ID) || #endif #ifdef RT3090 (device_id == NIC3090_PCIe_DEVICE_ID) || (device_id == NIC3091_PCIe_DEVICE_ID) || (device_id == NIC3092_PCIe_DEVICE_ID) || #endif /* RT3090 // */ 0) { u32 MacCsr0 = 0, Index = 0; do { RTMP_IO_READ32(pAd, MAC_CSR0, &MacCsr0); if ((MacCsr0 != 0x00) && (MacCsr0 != 0xFFFFFFFF)) break; RTMPusecDelay(10); } while (Index++ < 100); /* Support advanced power save after 2892/2790. */ /* MAC version at offset 0x1000 is 0x2872XXXX/0x2870XXXX(PCIe, USB, SDIO). */ if ((MacCsr0 & 0xffff0000) != 0x28600000) { OPSTATUS_SET_FLAG(pAd, fOP_STATUS_PCIE_DEVICE); } } }
VOID RT35xx_ChipSwitchChannel( IN PRTMP_ADAPTER pAd, IN UCHAR Channel, IN BOOLEAN bScan) { CHAR TxPwer = 0, TxPwer2 = DEFAULT_RF_TX_POWER; /*Bbp94 = BBPR94_DEFAULT, TxPwer2 = DEFAULT_RF_TX_POWER;*/ UCHAR index; UINT32 Value = 0; /*BbpReg, Value;*/ UCHAR RFValue; UINT32 i = 0; i = i; /* avoid compile warning */ RFValue = 0; /* Search Tx power value*/ /* We can't use ChannelList to search channel, since some central channl's txpowr doesn't list in ChannelList, so use TxPower array instead. */ for (index = 0; index < MAX_NUM_OF_CHANNELS; index++) { if (Channel == pAd->TxPower[index].Channel) { TxPwer = pAd->TxPower[index].Power; TxPwer2 = pAd->TxPower[index].Power2; break; } } if (index == MAX_NUM_OF_CHANNELS) { DBGPRINT(RT_DEBUG_ERROR, ("AsicSwitchChannel: Can't find the Channel#%d \n", Channel)); } #ifdef RT35xx /* 3562:RFIC_3052/ 3062:RFIC_3022 */ if (IS_RT3572(pAd) /*&& (pAd->RfIcType == RFIC_3052)*/) { for (index = 0; index < NUM_OF_3572_CHNL; index++) { if (Channel == FreqItems3572[index].Channel) { /* for 2.4G, restore BBP25, BBP26*/ if (Channel <= 14) { BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R25, pAd->Bbp25); BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R26, pAd->Bbp26); } /* hard code for 5GGhz, Gary 2008-12-10*/ else { /* Enable IQ Phase Correction*/ BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R25, 0x09); /* IQ Phase correction value*/ BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R26, 0xFF); } /* Programming channel parameters*/ RT30xxWriteRFRegister(pAd, RF_R02, FreqItems3572[index].N); RT30xxWriteRFRegister(pAd, RF_R03, FreqItems3572[index].K); RT30xxReadRFRegister(pAd, RF_R06, &RFValue); if (Channel <= 14) RFValue = (RFValue & 0xF0) | FreqItems3572[index].R | 0x8; else RFValue = (RFValue & 0xF0) | FreqItems3572[index].R | 0x4; RT30xxWriteRFRegister(pAd, RF_R06, RFValue); /* Pll mode for 2.4G or 5G*/ RT30xxReadRFRegister(pAd, RF_R05, &RFValue); if (Channel <= 14) RFValue = (RFValue & 0xF3) | 0x4; else RFValue = (RFValue & 0xF3) | 0x8; RT30xxWriteRFRegister(pAd, RF_R05, RFValue); /* Set Tx0 Power*/ RT30xxReadRFRegister(pAd, RF_R12, (PUCHAR)&RFValue); if (Channel <= 14) RFValue = 0x60 | TxPwer; else RFValue = 0xE0 | (TxPwer & 0x3) | ((TxPwer & 0xC) << 1); RT30xxWriteRFRegister(pAd, RF_R12, RFValue); /* Set Tx1 Power*/ RT30xxReadRFRegister(pAd, RF_R13, (PUCHAR)&RFValue); if (Channel <= 14) RFValue = 0x60 | TxPwer2; else RFValue = 0xE0 | (TxPwer2 & 0x3) | ((TxPwer2 & 0xC) << 1); RT30xxWriteRFRegister(pAd, RF_R13, RFValue); /* Tx/Rx Stream setting*/ RT30xxReadRFRegister(pAd, RF_R01, (PUCHAR)&RFValue); RFValue &= 0x03; /*clear bit[7~2]*/ if (pAd->Antenna.field.TxPath == 1) RFValue |= 0xA0; else if (pAd->Antenna.field.TxPath == 2) RFValue |= 0x80; if (pAd->Antenna.field.RxPath == 1) RFValue |= 0x50; else if (pAd->Antenna.field.RxPath == 2) RFValue |= 0x40; RT30xxWriteRFRegister(pAd, RF_R01, (UCHAR)RFValue); /* Set RF offset*/ RT30xxReadRFRegister(pAd, RF_R23, (PUCHAR)&RFValue); RFValue = (RFValue & 0x80) | pAd->RfFreqOffset; RT30xxWriteRFRegister(pAd, RF_R23, (UCHAR)RFValue); /* Set BW*/ if (!bScan && (pAd->CommonCfg.BBPCurrentBW == BW_40)) { RFValue = pAd->Mlme.CaliBW40RfR24; /*DISABLE_11N_CHECK(pAd);*/ } else { RFValue = pAd->Mlme.CaliBW20RfR24; } /* R24, R31, one is for tx, the other is for rx*/ RT30xxWriteRFRegister(pAd, RF_R24, (UCHAR)RFValue); RT30xxWriteRFRegister(pAd, RF_R31, (UCHAR)RFValue); /* Enable RF tuning*/ RT30xxReadRFRegister(pAd, RF_R07, (PUCHAR)&RFValue); if (Channel <= 14) /*RFValue = (RFValue & 0x37) | 0xCC;*/ RFValue = 0xd8; /*?? to check 3572?? hardcode*/ else RFValue = (RFValue & 0x37) | 0x14; RT30xxWriteRFRegister(pAd, RF_R07, (UCHAR)RFValue); /* TSSI_BS*/ RT30xxReadRFRegister(pAd, RF_R09, (PUCHAR)&RFValue); if (Channel <= 14) RFValue = 0xC3; /*RFValue = (RFValue & 0xBF) | 0x40;*/ else RFValue = 0xC0; /*RFValue = (RFValue & 0xBF) | 0x40;*/ RT30xxWriteRFRegister(pAd, RF_R09, (UCHAR)RFValue); /* Loop filter 1*/ RT30xxWriteRFRegister(pAd, RF_R10, (UCHAR)0xF1); /* Loop filter 2*/ if (Channel <= 14) RT30xxWriteRFRegister(pAd, RF_R11, (UCHAR)0xB9); else RT30xxWriteRFRegister(pAd, RF_R11, (UCHAR)0x00); /* tx_mx2_ic*/ if (Channel <= 14) RT30xxWriteRFRegister(pAd, RF_R15, (UCHAR)0x53); else RT30xxWriteRFRegister(pAd, RF_R15, (UCHAR)0x43); /* tx_mx1_ic*/ /*RT30xxReadRFRegister(pAd, RF_R16, (PUCHAR)&RFValue);*/ if (Channel <= 14) { RFValue = 0x4c; RFValue &= (~0x7); /* clean bit [2:0]*/ RFValue |= pAd->TxMixerGain24G; } else { RFValue = 0x7a; RFValue &= (~0x7); /* clean bit [2:0]*/ RFValue |= pAd->TxMixerGain5G; } RT30xxWriteRFRegister(pAd, RF_R16, (UCHAR)RFValue); /* tx_lo1*/ RT30xxWriteRFRegister(pAd, RF_R17, (UCHAR)0x23); /* tx_lo2*/ RFValue = ((Channel <= 14) ? (0x93) : ((Channel <= 64) ? (0xb7) : ((Channel <= 128) ? (0x74) : (0x72)))); RT30xxWriteRFRegister(pAd, RF_R19, (UCHAR)RFValue); /* rx_l01*/ RFValue = ((Channel <= 14) ? (0xB3) : ((Channel <= 64) ? (0xF6) : ((Channel <= 128) ? (0xF4) : (0xF3)))); RT30xxWriteRFRegister(pAd, RF_R20, (UCHAR)RFValue); /* pfd_delay*/ RFValue = ((Channel <= 14) ? (0x15) : ((Channel <= 64) ? (0x3d) : ((Channel <= 128) ? (0x01) : (0x01)))); RT30xxWriteRFRegister(pAd, RF_R25, (UCHAR)RFValue); /* rx_lo2*/ if (Channel <= 14) RT30xxWriteRFRegister(pAd, RF_R26, (UCHAR)0x85); else RT30xxWriteRFRegister(pAd, RF_R26, (UCHAR)0x87); /* ldo_rf_vc*/ if (Channel <= 14) RT30xxWriteRFRegister(pAd, RF_R27, (UCHAR)0x00); else RT30xxWriteRFRegister(pAd, RF_R27, (UCHAR)0x01); /* drv_cc*/ if (Channel <= 14) RT30xxWriteRFRegister(pAd, RF_R29, (UCHAR)0x9B); else RT30xxWriteRFRegister(pAd, RF_R29, (UCHAR)0x9F); RTMP_IO_READ32(pAd, GPIO_CTRL_CFG, &Value); if (Channel <= 14) Value = ((Value & 0xFFFF7FFF) | 0x00000080); else Value = (Value & 0xFFFF7F7F); RTMP_IO_WRITE32(pAd, GPIO_CTRL_CFG, Value); /* Enable RF tuning, this must be in the last*/ RT30xxReadRFRegister(pAd, RF_R07, (PUCHAR)&RFValue); RFValue = RFValue | 0x1; RT30xxWriteRFRegister(pAd, RF_R07, (UCHAR)RFValue); RTMPusecDelay(2000); /* latch channel for future usage.*/ pAd->LatchRfRegs.Channel = Channel; DBGPRINT(RT_DEBUG_TRACE, ("RT35xx: SwitchChannel#%d(RF=%d, Pwr0=%d, Pwr1=%d, %dT), N=0x%02X, K=0x%02X, R=0x%02X\n", Channel, pAd->RfIcType, TxPwer, TxPwer2, pAd->Antenna.field.TxPath, FreqItems3572[index].N, FreqItems3572[index].K, FreqItems3572[index].R)); break; } } } else #endif /* RT35xx */ { switch (pAd->RfIcType) { default: DBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d : unknown RFIC=%d\n", Channel, pAd->RfIcType)); break; } } /* Change BBP setting during siwtch from a->g, g->a*/ if (Channel <= 14) { ULONG TxPinCfg = 0x00050F0A;/*Gary 2007/08/09 0x050A0A*/ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd))); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd))); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd))); /* Rx High power VGA offset for LNA select*/ { if (pAd->NicConfig2.field.ExternalLNAForG) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x62); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46); } else { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x84); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50); } } /* 5G band selection PIN, bit1 and bit2 are complement*/ RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value); Value &= (~0x6); Value |= (0x04); RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value); #ifdef RT35xx if (IS_RT3572(pAd)) RT30xxWriteRFRegister(pAd, RF_R08, (UCHAR)0x00); #endif /* RT35xx */ { /* Turn off unused PA or LNA when only 1T or 1R*/ if (pAd->Antenna.field.TxPath == 1) { TxPinCfg &= 0xFFFFFFF3; } if (pAd->Antenna.field.RxPath == 1) { TxPinCfg &= 0xFFFFF3FF; } } RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg); #ifdef RT35xx if (IS_RT3572(pAd)) RT30xxWriteRFRegister(pAd, RF_R08, (UCHAR)0x80); #endif /* RT35xx */ } else { ULONG TxPinCfg = 0x00050F05;/*Gary 2007/8/9 0x050505*/ UINT8 bbpValue; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd))); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd))); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd))); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);/*(0x44 - GET_LNA_GAIN(pAd))); According the Rory's suggestion to solve the middle range issue. */ /* Set the BBP_R82 value here */ bbpValue = 0xF2; #ifdef RT35xx if (IS_RT3572(pAd)) { /* TODO: check if the BBP_R82 value is the same in both of following cases!!!*/ /* Rx High power VGA offset for LNA select*/ bbpValue = 0x94; } #endif /* RT35xx */ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, bbpValue); /* Rx High power VGA offset for LNA select*/ if (pAd->NicConfig2.field.ExternalLNAForA) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46); } else { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50); } /* 5G band selection PIN, bit1 and bit2 are complement*/ RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value); Value &= (~0x6); Value |= (0x02); RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value); /* Turn off unused PA or LNA when only 1T or 1R*/ #ifdef RT35xx if (IS_RT3572(pAd)) RT30xxWriteRFRegister(pAd, RF_R08, (UCHAR)0x00); #endif /* RT35xx */ { /* Turn off unused PA or LNA when only 1T or 1R*/ if (pAd->Antenna.field.TxPath == 1) { TxPinCfg &= 0xFFFFFFF3; } if (pAd->Antenna.field.RxPath == 1) { TxPinCfg &= 0xFFFFF3FF; } } RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg); #ifdef RT35xx if (IS_RT3572(pAd)) RT30xxWriteRFRegister(pAd, RF_R08, (UCHAR)0x80); #endif /* RT35xx */ } /* R66 should be set according to Channel and use 20MHz when scanning*/ /*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, (0x2E + GET_LNA_GAIN(pAd)));*/ if (bScan) RTMPSetAGCInitValue(pAd, BW_20); else RTMPSetAGCInitValue(pAd, pAd->CommonCfg.BBPCurrentBW); /* On 11A, We should delay and wait RF/BBP to be stable*/ /* and the appropriate time should be 1000 micro seconds */ /* 2005/06/05 - On 11G, We also need this delay time. Otherwise it's difficult to pass the WHQL.*/ RTMPusecDelay(1000); }
VOID NICInitRT3572RFRegisters(IN PRTMP_ADAPTER pAd) { INT i; UINT8 RfReg = 0; UINT32 data; /* Driver must read EEPROM to get RfIcType before initial RF registers Initialize RF register to default value Init RF calibration Driver should toggle RF R30 bit7 before init RF registers */ RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RfReg); RfReg |= 0x80; RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg); RTMPusecDelay(1000); RfReg &= 0x7F; RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg); /* Initialize RF register to default value */ for (i = 0; i < NUM_RF_3572REG_PARMS; i++) { RT30xxWriteRFRegister(pAd, RF3572_RFRegTable[i].Register, RF3572_RFRegTable[i].Value); } /* Driver should set RF R6 bit6 on before init RF registers */ RT30xxReadRFRegister(pAd, RF_R06, (PUCHAR)&RfReg); RfReg |= 0x40; RT30xxWriteRFRegister(pAd, RF_R06, (UCHAR)RfReg); /* init R31 */ /*RT30xxWriteRFRegister(pAd, RF_R31, 0x14);*/ if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211)) { /* patch tx EVM issue temporarily */ RTMP_IO_READ32(pAd, LDO_CFG0, &data); data = ((data & 0xF0FFFFFF) | 0x0D000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, data); } else { /* Patch for SRAM, increase voltage to 1.35V on core voltage and down to 1.2V after 1 msec*/ RTMP_IO_READ32(pAd, LDO_CFG0, &data); data = ((data & 0xE0FFFFFF) | 0x0D000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, data); RTMPusecDelay(1000); data = ((data & 0xE0FFFFFF) | 0x01000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, data); } /* patch LNA_PE_G1 (toggle GPIO_SWITCH) is not necessary for 3572 */ /* RTMP_IO_READ32(pAd, GPIO_SWITCH, &data); data &= ~(0x20); RTMP_IO_WRITE32(pAd, GPIO_SWITCH, data); */ /* For RF filter Calibration */ RTMPFilterCalibration(pAd); /* save R25, R26 for 2.4GHz */ BBP_IO_READ8_BY_REG_ID(pAd, BBP_R25, &pAd->Bbp25); BBP_IO_READ8_BY_REG_ID(pAd, BBP_R26, &pAd->Bbp26); /* set led open drain enable */ RTMP_IO_READ32(pAd, OPT_14, &data); data |= 0x01; RTMP_IO_WRITE32(pAd, OPT_14, data); }
VOID RT28xxUsbMlmeRadioOFF( IN PRTMP_ADAPTER pAd) { WPDMA_GLO_CFG_STRUC GloCfg; UINT32 Value, i; DBGPRINT(RT_DEBUG_TRACE,("RT28xxUsbMlmeRadioOFF()\n")); if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF)) return; RTMPSetLED(pAd, LED_RADIO_OFF); RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF); { if (INFRA_ON(pAd) || ADHOC_ON(pAd)) LinkDown(pAd, FALSE); RTMPusecDelay(10000); BssTableInit(&pAd->ScanTab); } if (pAd->CommonCfg.BBPCurrentBW == BW_40) { AsicTurnOffRFClk(pAd, pAd->CommonCfg.CentralChannel); } else { AsicTurnOffRFClk(pAd, pAd->CommonCfg.Channel); } RTUSBReadMACRegister(pAd, WPDMA_GLO_CFG, &GloCfg.word); GloCfg.field.EnableTxDMA = 0; GloCfg.field.EnableRxDMA = 0; RTUSBWriteMACRegister(pAd, WPDMA_GLO_CFG, GloCfg.word); i = 0; do { RTMP_IO_READ32(pAd, WPDMA_GLO_CFG, &GloCfg.word); if ((GloCfg.field.TxDMABusy == 0) && (GloCfg.field.RxDMABusy == 0)) break; RTMPusecDelay(1000); }while (i++ < 100); RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value); Value &= (0xfffffff3); RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value); AsicSendCommandToMcu(pAd, 0x30, 0xff, 0xff, 0x02); }
void NICInitRT3090RFRegisters(struct rt_rtmp_adapter *pAd) { int i; /* Driver must read EEPROM to get RfIcType before initial RF registers */ /* Initialize RF register to default value */ if (IS_RT3090(pAd)) { /* Init RF calibration */ /* Driver should toggle RF R30 bit7 before init RF registers */ u32 RfReg = 0, data; RT30xxReadRFRegister(pAd, RF_R30, (u8 *)&RfReg); RfReg |= 0x80; RT30xxWriteRFRegister(pAd, RF_R30, (u8)RfReg); RTMPusecDelay(1000); RfReg &= 0x7F; RT30xxWriteRFRegister(pAd, RF_R30, (u8)RfReg); /* init R24, R31 */ RT30xxWriteRFRegister(pAd, RF_R24, 0x0F); RT30xxWriteRFRegister(pAd, RF_R31, 0x0F); /* RT309x version E has fixed this issue */ if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211)) { /* patch tx EVM issue temporarily */ RTMP_IO_READ32(pAd, LDO_CFG0, &data); data = ((data & 0xE0FFFFFF) | 0x0D000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, data); } else { RTMP_IO_READ32(pAd, LDO_CFG0, &data); data = ((data & 0xE0FFFFFF) | 0x01000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, data); } /* patch LNA_PE_G1 failed issue */ RTMP_IO_READ32(pAd, GPIO_SWITCH, &data); data &= ~(0x20); RTMP_IO_WRITE32(pAd, GPIO_SWITCH, data); /* Initialize RF register to default value */ for (i = 0; i < NUM_RF_REG_PARMS; i++) { RT30xxWriteRFRegister(pAd, RT30xx_RFRegTable[i].Register, RT30xx_RFRegTable[i].Value); } /* Driver should set RF R6 bit6 on before calibration */ RT30xxReadRFRegister(pAd, RF_R06, (u8 *)&RfReg); RfReg |= 0x40; RT30xxWriteRFRegister(pAd, RF_R06, (u8)RfReg); /*For RF filter Calibration */ RTMPFilterCalibration(pAd); /* Initialize RF R27 register, set RF R27 must be behind RTMPFilterCalibration() */ if ((pAd->MACVersion & 0xffff) < 0x0211) RT30xxWriteRFRegister(pAd, RF_R27, 0x3); /* set led open drain enable */ RTMP_IO_READ32(pAd, OPT_14, &data); data |= 0x01; RTMP_IO_WRITE32(pAd, OPT_14, data); /* set default antenna as main */ if (pAd->RfIcType == RFIC_3020) AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt); /* add by johnli, RF power sequence setup, load RF normal operation-mode setup */ RT30xxLoadRFNormalModeSetup(pAd); } }
/* ======================================================================== Routine Description: Arguments: Return Value: Note: ======================================================================== */ VOID RTUSBCancelPendingBulkOutIRP( IN PRTMP_ADAPTER pAd) { PTX_CONTEXT pTxContext; PTX_CONTEXT pMLMEContext; PTX_CONTEXT pBeaconContext; PTX_CONTEXT pNullContext; PTX_CONTEXT pPsPollContext; PTX_CONTEXT pRTSContext; UINT i, Idx; unsigned long IrqFlags; for (Idx = 0; Idx < 4; Idx++) { for (i = 0; i < TX_RING_SIZE; i++) { pTxContext = &(pAd->TxContext[Idx][i]); if (pTxContext->IRPPending == TRUE) { // Get the USB_CONTEXT and cancel it's IRP; the completion routine will itself // remove it from the HeadPendingSendList and NULL out HeadPendingSendList // when the last IRP on the list has been cancelled; that's how we exit this loop // RTUSB_UNLINK_URB(pTxContext->pUrb); // Sleep 200 microseconds to give cancellation time to work RTMPusecDelay(200); } } } for (i = 0; i < PRIO_RING_SIZE; i++) { pMLMEContext = &(pAd->MLMEContext[i]); if(pMLMEContext->IRPPending == TRUE) { // Get the USB_CONTEXT and cancel it's IRP; the completion routine will itself // remove it from the HeadPendingSendList and NULL out HeadPendingSendList // when the last IRP on the list has been cancelled; that's how we exit this loop // RTUSB_UNLINK_URB(pMLMEContext->pUrb); // Sleep 200 microsecs to give cancellation time to work RTMPusecDelay(200); } } for (i = 0; i < BEACON_RING_SIZE; i++) { pBeaconContext = &(pAd->BeaconContext[i]); if(pBeaconContext->IRPPending == TRUE) { // Get the USB_CONTEXT and cancel it's IRP; the completion routine will itself // remove it from the HeadPendingSendList and NULL out HeadPendingSendList // when the last IRP on the list has been cancelled; that's how we exit this loop // RTUSB_UNLINK_URB(pBeaconContext->pUrb); // Sleep 200 microsecs to give cancellation time to work RTMPusecDelay(200); } } pNullContext = &(pAd->NullContext); if (pNullContext->IRPPending == TRUE) RTUSB_UNLINK_URB(pNullContext->pUrb); pRTSContext = &(pAd->RTSContext); if (pRTSContext->IRPPending == TRUE) RTUSB_UNLINK_URB(pRTSContext->pUrb); pPsPollContext = &(pAd->PsPollContext); if (pPsPollContext->IRPPending == TRUE) RTUSB_UNLINK_URB(pPsPollContext->pUrb); for (Idx = 0; Idx < 4; Idx++) { NdisAcquireSpinLock(&pAd->BulkOutLock[Idx], IrqFlags); pAd->BulkOutPending[Idx] = FALSE; NdisReleaseSpinLock(&pAd->BulkOutLock[Idx], IrqFlags); } }