int __init msm7x2x_misc_init(void)
{
	if (machine_is_msm8625_rumi3()) {
		msm_clock_init(&msm8625_dummy_clock_init_data);
		msm_cpr_init();
		return 0;
	}

	msm_clock_init(&msm7x27a_clock_init_data);
	if (cpu_is_msm7x27aa() || cpu_is_msm7x25ab())
		platform_device_register(&msm7x27aa_device_acpuclk);
	else if (cpu_is_msm8625()) {
		if (msm8625_cpu_id() == MSM8625)
			platform_device_register(&msm7x27aa_device_acpuclk);
		else if (msm8625_cpu_id() == MSM8625A)
			platform_device_register(&msm8625_device_acpuclk);
		else if (msm8625_cpu_id() == MSM8625AB)
			platform_device_register(&msm8625ab_device_acpuclk);
	} else {
		platform_device_register(&msm7x27a_device_acpuclk);
	}

	if (cpu_is_msm8625() &&
			(SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 2))
		msm_cpr_init();

	return 0;
}
static int __init acpuclk_8064_probe(struct platform_device *pdev)
{
#ifdef CONFIG_LGE_PM
	if (lge_get_factory_boot()) 
	{
		if(lge_get_boot_cable_type() == LGE_BOOT_LT_CABLE_56K ||
// #ifdef CONFIG_MACH_APQ8064_L05E
			lge_get_boot_cable_type() == LGE_BOOT_LT_CABLE_910K ||
// #endif
			lge_get_boot_cable_type() == LGE_BOOT_LT_CABLE_130K)
		{
			pr_info("apq8064:::select pvs_tables to factory_1026\n");
			acpuclk_8064_params.pvs_tables = pvs_tables_factory_1026;
		}
		else
		{
			pr_info("select pvs_tables to original pvs_table\n");
			acpuclk_8064_params.pvs_tables = pvs_tables;
		}
	}
#endif //             
	if (cpu_is_apq8064ab() ||
		SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2) {
		acpuclk_8064_params.hfpll_data->low_vdd_l_max = 37;
		acpuclk_8064_params.hfpll_data->nom_vdd_l_max = 74;
	}

	return acpuclk_krait_init(&pdev->dev, &acpuclk_8064_params);
}
void __init msm8930_init_gpu(void)
{
	unsigned int version = socinfo_get_version();

	/* Set the turbo speed for the AA and AB respectively */

	if (cpu_is_msm8930aa())
		kgsl_3d0_pdata.pwrlevel[0].gpu_freq = 487500000;
	else if (cpu_is_msm8930ab()) {
		kgsl_3d0_pdata.pwrlevel[0].gpu_freq = 500000000;
		grp3d_max_vectors[0].ib = KGSL_CONVERT_TO_MBPS(4800);
	}

	/* Set up the chip ID based on the SoC version */

	if (cpu_is_msm8930ab())
		kgsl_3d0_pdata.chipid = ADRENO_CHIPID(3, 0, 5, 3);
	else if ((SOCINFO_VERSION_MAJOR(version) == 1) &&
		(SOCINFO_VERSION_MINOR(version) == 2))
		kgsl_3d0_pdata.chipid = ADRENO_CHIPID(3, 0, 5, 2);
	else
		kgsl_3d0_pdata.chipid = ADRENO_CHIPID(3, 0, 5, 0);

	platform_device_register(&device_kgsl_3d0);
}
void __init msm8930_init_gpu(void)
{
	unsigned int version = socinfo_get_version();

	

	if (cpu_is_msm8930aa())
		kgsl_3d0_pdata.pwrlevel[0].gpu_freq = 450000000;
	else if (cpu_is_msm8930ab()) {
		kgsl_3d0_pdata.pwrlevel[0].gpu_freq = 500000000;
		grp3d_max_vectors[0].ib = KGSL_CONVERT_TO_MBPS(4800);
	}

	

	if (cpu_is_msm8930ab())
		kgsl_3d0_pdata.chipid = ADRENO_CHIPID(3, 0, 5, 3);
	else if ((SOCINFO_VERSION_MAJOR(version) == 1) &&
		(SOCINFO_VERSION_MINOR(version) == 2))
		kgsl_3d0_pdata.chipid = ADRENO_CHIPID(3, 0, 5, 2);
	else
		kgsl_3d0_pdata.chipid = ADRENO_CHIPID(3, 0, 5, 0);

	platform_device_register(&device_kgsl_3d0);
}
void __init msm8960_init_fb(void)
{
    uint32_t soc_platform_version = socinfo_get_version();


    if (SOCINFO_VERSION_MAJOR(soc_platform_version) >= 3)
        mdp_pdata.mdp_rev = MDP_REV_43;

    if (cpu_is_msm8960ab())
        mdp_pdata.mdp_rev = MDP_REV_44;

#ifdef CONFIG_FB_MSM_WRITEBACK_MSM_PANEL
    platform_device_register(&wfd_device);
#endif

#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
    platform_device_register(&hdmi_msm_device);
#endif
    mipi_dsi_panel_add_device();
    platform_device_register(&msm_fb_device);
    msm_fb_register_device("mdp", &mdp_pdata);
    msm_fb_register_device("mipi_dsi", &mipi_dsi_pdata);
#ifdef CONFIG_MSM_BUS_SCALING
    msm_fb_register_device("dtv", &dtv_pdata);
#endif
}
void __init apq8064_init_mmc(void)
{
	if (apq8064_sdc1_pdata) {
		/* 8064 v2 supports upto 200MHz clock on SDC1 slot */
		if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 2) {
			apq8064_sdc1_pdata->sup_clk_table =
					sdc1_sup_clk_rates_all;
			apq8064_sdc1_pdata->sup_clk_cnt	=
					ARRAY_SIZE(sdc1_sup_clk_rates_all);
		}
		apq8064_add_sdcc(1, apq8064_sdc1_pdata);
		apq8064_add_uio();
	}

	if (apq8064_sdc2_pdata)
		apq8064_add_sdcc(2, apq8064_sdc2_pdata);

	if (apq8064_sdc3_pdata) {
		if (!machine_is_apq8064_cdp()) {
			apq8064_sdc3_pdata->wpswitch_gpio = 0;
			apq8064_sdc3_pdata->is_wpswitch_active_low = false;
		}
		if (machine_is_mpq8064_cdp() || machine_is_mpq8064_hrd() ||
			machine_is_mpq8064_dtv()) {
			int rc;
			struct pm_gpio sd_card_det_init_cfg = {
				.direction      = PM_GPIO_DIR_IN,
				.output_buffer  = PM_GPIO_OUT_BUF_CMOS,
				.pull           = PM_GPIO_PULL_UP_30,
				.vin_sel        = PM_GPIO_VIN_S4,
				.out_strength   = PM_GPIO_STRENGTH_NO,
				.function       = PM_GPIO_FUNC_NORMAL,
			};

			apq8064_sdc3_pdata->status_gpio =
				PM8921_GPIO_PM_TO_SYS(31);
			apq8064_sdc3_pdata->status_irq =
				PM8921_GPIO_IRQ(PM8921_IRQ_BASE, 31);
			rc = pm8xxx_gpio_config(apq8064_sdc3_pdata->status_gpio,
					&sd_card_det_init_cfg);
			if (rc) {
				pr_info("%s: SD_CARD_DET GPIO%d config "
					"failed(%d)\n", __func__,
					apq8064_sdc3_pdata->status_gpio, rc);
				apq8064_sdc3_pdata->status_gpio = 0;
				apq8064_sdc3_pdata->status_irq = 0;
			}
		}
		if (machine_is_apq8064_cdp()) {
			int i;

			for (i = 0;
			     i < apq8064_sdc3_pdata->pin_data->pad_data->\
				 drv->size;
			     i++)
				apq8064_sdc3_pdata->pin_data->pad_data->\
					drv->on[i].val = GPIO_CFG_10MA;
		}
		apq8064_add_sdcc(3, apq8064_sdc3_pdata);
	}
void __init msm_pm_register_cpr_ops(void)
{
	/* CPR presents on revision >= v2.0 chipsets */
	if (cpu_is_msm8625() &&
			SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 2)
		msm_pm_set_cpr_ops(&msm8625_pm_cpr_ops);
}
Exemple #8
0
static int msm_fb_detect_panel(const char *name)
{
	if (machine_is_msm8x60_fluid()) {
		uint32_t soc_platform_version = socinfo_get_platform_version();
		if (SOCINFO_VERSION_MAJOR(soc_platform_version) < 3) {
#ifdef CONFIG_FB_MSM_LCDC_SAMSUNG_OLED_PT
			if (!strncmp(name, LCDC_SAMSUNG_OLED_PANEL_NAME,
					strlen(LCDC_SAMSUNG_OLED_PANEL_NAME)))
				return 0;
#endif
		} else { /*P3 and up use AUO panel */
#ifdef CONFIG_FB_MSM_LCDC_AUO_WVGA
			if (!strncmp(name, LCDC_AUO_PANEL_NAME,
					strlen(LCDC_AUO_PANEL_NAME)))
				return 0;
#endif
		}
		if (!strncmp(name, LCDC_SAMSUNG_WSVGA_PANEL_NAME,
				strlen(LCDC_SAMSUNG_WSVGA_PANEL_NAME)))
			return -ENODEV;
	} else {
		if (!strncmp(name, LCDC_SAMSUNG_WSVGA_PANEL_NAME,
				strlen(LCDC_SAMSUNG_WSVGA_PANEL_NAME)))
			return 0;
		if (!strncmp(name, LCDC_SAMSUNG_OLED_PANEL_NAME,
				strlen(LCDC_SAMSUNG_OLED_PANEL_NAME)))
			return -ENODEV;
	}
	pr_warning("%s: not supported '%s'", __func__, name);
	return -ENODEV;
}
void __init msm8960_init_fb(void)
{
	uint32_t soc_platform_version = socinfo_get_version();


	if (SOCINFO_VERSION_MAJOR(soc_platform_version) >= 3)
		mdp_pdata.mdp_rev = MDP_REV_43;

	if (cpu_is_msm8960ab())
		mdp_pdata.mdp_rev = MDP_REV_44;

	sony_viskan_add_lcd_device();
#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
	platform_device_register(&hdmi_msm_device);
#endif
	platform_device_register(&msm_fb_device);
#ifdef CONFIG_FB_MSM_WRITEBACK_MSM_PANEL
	platform_device_register(&wfd_device);
#endif
	msm_fb_register_device("mdp", &mdp_pdata);
#ifdef CONFIG_FB_MSM_MIPI_DSI_VENDOR_DET
	if (sony_viskan_is_dric_det() == LCD_VENDOR_SAMSUNG)
		mipi_dsi_pdata.dsi_power_save = s6d6aa0_lcd_power;
	else
		mipi_dsi_pdata.dsi_power_save = r63306_lcd_power;
#endif /* CONFIG_FB_MSM_MIPI_DSI_VENDOR_DET */
	msm_fb_register_device("mipi_dsi", &mipi_dsi_pdata);
#ifdef CONFIG_MSM_BUS_SCALING
	msm_fb_register_device("dtv", &dtv_pdata);
#endif
}
void __init msm8930_init_mmc(void)
{
#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
	/* SDC1 : eMMC card connected */
	msm_add_sdcc(1, &msm8930_sdc1_data);
#endif
#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
	/*
	 * All 8930 platform boards using the 1.2 SoC have been reworked so that
	 * the sd card detect line's esd circuit is no longer powered by the sd
	 * card's voltage regulator. So this means we can turn the regulator off
	 * to save power without affecting the sd card detect functionality.
	 * This change to the boards will be true for newer versions of the SoC
	 * as well.
	 */
	if ((SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 1 &&
			SOCINFO_VERSION_MINOR(socinfo_get_version()) >= 2) ||
			machine_is_msm8930_cdp()) {
		msm8930_sdc3_data.vreg_data->vdd_data->always_on = false;
		msm8930_sdc3_data.vreg_data->vdd_data->reset_at_init = false;
	}
	/* SDC3: External card slot */
	if (!machine_is_msm8930_cdp()) {
		msm8930_sdc3_data.wpswitch_gpio = 0;
		msm8930_sdc3_data.wpswitch_polarity = 0;
	}
	msm_add_sdcc(3, &msm8930_sdc3_data);
#endif
}
static int lvds_pixel_remap(void)
{
	u32 ver = socinfo_get_version();

	if (machine_is_apq8064_cdp() ||
	    machine_is_apq8064_liquid()) {
		if ((SOCINFO_VERSION_MAJOR(ver) == 1) &&
		    (SOCINFO_VERSION_MINOR(ver) == 0))
			return LVDS_PIXEL_MAP_PATTERN_1;
	} else if (machine_is_mpq8064_dtv()) {
		if ((SOCINFO_VERSION_MAJOR(ver) == 1) &&
		    (SOCINFO_VERSION_MINOR(ver) == 0))
			return LVDS_PIXEL_MAP_PATTERN_2;
	}
	return 0;
}
int __init meminfo_init(unsigned int type, unsigned int min_bank_size)
{
	unsigned int i;
	unsigned long bank_size;
	unsigned long bank_start;
	struct smem_ram_ptable *ram_ptable;
	/* physical memory banks */
	unsigned int nr_mem_banks = 0;
	/* logical memory regions for dmm */
	nr_mem_regions = 0;

	ram_ptable = smem_alloc(SMEM_USABLE_RAM_PARTITION_TABLE,
				sizeof(struct smem_ram_ptable));

	if (!ram_ptable) {
		pr_err("Could not read ram partition table\n");
		return -EINVAL;
	}

	/* Determine power control mode based on the hw version */
	/* This check will be removed when PASR is fully supported */
	if (cpu_is_msm8960() &&
		SOCINFO_VERSION_MAJOR(socinfo_get_version()) < 2)
		dmm_mode = MEM_DEEP_POWER_DOWN;
	else
		dmm_mode = MEM_SELF_REFRESH;

	pr_info("meminfo_init: smem ram ptable found: ver: %d len: %d\n",
			ram_ptable->version, ram_ptable->len);

	for (i = 0; i < ram_ptable->len; i++) {
		if (ram_ptable->parts[i].type == type &&
			ram_ptable->parts[i].size >= min_bank_size) {
			bank_start = ram_ptable->parts[i].start;
			bank_size = ram_ptable->parts[i].size;
			/* Divide into logical memory regions of same size */
			while (bank_size) {
				mem_regions[nr_mem_regions].start =
					bank_start;
				mem_regions[nr_mem_regions].size =
					MIN_MEMORY_BLOCK_SIZE;
				mutex_init(&mem_regions[nr_mem_regions]
							.state_mutex);
				mem_regions[nr_mem_regions].state =
							STATE_DEFAULT;
				mem_regions[nr_mem_regions].mask = default_mask;
				bank_start += MIN_MEMORY_BLOCK_SIZE;
				bank_size -= MIN_MEMORY_BLOCK_SIZE;
				nr_mem_regions++;
			}
			nr_mem_banks++;
		}
	}
	pr_info("Found %d memory banks grouped into %d memory regions\n",
			nr_mem_banks, nr_mem_regions);
	return 0;
}
Exemple #13
0
static void __init msm7x2x_map_io(void)
{
	msm_map_common_io();

	msm_msm7x2x_allocate_memory_regions();

	if (socinfo_init() < 0)
		BUG();

#ifdef CONFIG_CACHE_L2X0
	if ((SOCINFO_VERSION_MAJOR(socinfo_get_version()) > 1)
		|| ((SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 1)
		&& (SOCINFO_VERSION_MINOR(socinfo_get_version()) >= 3)))
		l2x0_init(MSM_L2CC_BASE, 0x0006801B, 0xfe000000);
	else
		l2x0_init(MSM_L2CC_BASE, 0x00068012, 0xfe000000);
#endif
}
void __init apq8064_init_gpu(void)
{
	unsigned int version = socinfo_get_version();

	if (cpu_is_apq8064ab())
		kgsl_3d0_pdata.pwrlevel[0].gpu_freq = 450000000;
	if (SOCINFO_VERSION_MAJOR(version) == 2) {
		kgsl_3d0_pdata.chipid = ADRENO_CHIPID(3, 2, 0, 2);
	} else {
		if ((SOCINFO_VERSION_MAJOR(version) == 1) &&
				(SOCINFO_VERSION_MINOR(version) == 1))
			kgsl_3d0_pdata.chipid = ADRENO_CHIPID(3, 2, 0, 1);
		else
			kgsl_3d0_pdata.chipid = ADRENO_CHIPID(3, 2, 0, 0);
	}

	platform_device_register(&device_kgsl_3d0);
}
/*
 * this a software workaround for not having two distinct board
 * files for 8660v1 and 8660v2. 8660v1 has a faulty 2d clock, and
 * this workaround detects the cpu version to tell if the kernel is on a
 * 8660v1, and should disable the 2d core. it is called from the board file
 */
void __init msm8x60_check_2d_hardware(void)
{
	if ((SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 1) &&
	    (SOCINFO_VERSION_MINOR(socinfo_get_version()) == 0)) {
		printk(KERN_WARNING "kgsl: 2D cores disabled on 8660v1\n");
		kgsl_pdata.grp2d0_clk_name = NULL;
		kgsl_pdata.grp2d1_clk_name = NULL;
	}
}
int __init msm8960_init_gpiomux(void)
{
	int rc = msm_gpiomux_init(NR_GPIO_IRQS);
	if (rc) {
		pr_err(KERN_ERR "msm_gpiomux_init failed %d\n", rc);
		return rc;
	}

#if defined(CONFIG_KS8851) || defined(CONFIG_KS8851_MODULE)
	msm_gpiomux_install(msm8960_ethernet_configs,
			ARRAY_SIZE(msm8960_ethernet_configs));
#endif

	msm_gpiomux_install(msm8960_gsbi_configs,
			ARRAY_SIZE(msm8960_gsbi_configs));

	msm_gpiomux_install(msm8960_cyts_configs,
			ARRAY_SIZE(msm8960_cyts_configs));

	msm_gpiomux_install(msm8960_slimbus_config,
			ARRAY_SIZE(msm8960_slimbus_config));

	msm_gpiomux_install(msm8960_audio_codec_configs,
			ARRAY_SIZE(msm8960_audio_codec_configs));

	msm_gpiomux_install(msm8960_audio_auxpcm_configs,
			ARRAY_SIZE(msm8960_audio_auxpcm_configs));

	msm_gpiomux_install(wcnss_5wire_interface,
			ARRAY_SIZE(wcnss_5wire_interface));

	if (machine_is_msm8960_mtp() || machine_is_msm8960_fluid() ||
		machine_is_msm8960_liquid() || machine_is_msm8960_cdp())
		msm_gpiomux_install(hap_lvl_shft_config,
			ARRAY_SIZE(hap_lvl_shft_config));

	if (PLATFORM_IS_CHARM25())
		msm_gpiomux_install(mdm_configs,
			ARRAY_SIZE(mdm_configs));

#ifdef CONFIG_USB_EHCI_MSM_HSIC
	if ((SOCINFO_VERSION_MAJOR(socinfo_get_version()) != 1) &&
		(PLATFORM_IS_CHARM25() || machine_is_msm8960_liquid()))
		msm_gpiomux_install(msm8960_hsic_configs,
			ARRAY_SIZE(msm8960_hsic_configs));
#endif

#ifdef CONFIG_FB_MSM_HDMI_MSM_PANEL
	msm_gpiomux_install(msm8960_hdmi_configs,
			ARRAY_SIZE(msm8960_hdmi_configs));
#endif

	msm_gpiomux_install(msm8960_mdp_vsync_configs,
			ARRAY_SIZE(msm8960_mdp_vsync_configs));

	return 0;
}
static int msm_fb_detect_panel(const char *name)
{
	/* OPPO 2012-07-24 zhengzk Modify for MIPI start */
#ifndef CONFIG_VENDOR_EDIT
	u32 version;
	if (machine_is_apq8064_liquid()) {
		version = socinfo_get_platform_version();
		if ((SOCINFO_VERSION_MAJOR(version) == 1) &&
			(SOCINFO_VERSION_MINOR(version) == 1)) {
			if (!strncmp(name, MIPI_VIDEO_CHIMEI_WXGA_PANEL_NAME,
				strnlen(MIPI_VIDEO_CHIMEI_WXGA_PANEL_NAME,
					PANEL_NAME_MAX_LEN)))
				return 0;
		} else {
			if (!strncmp(name, LVDS_CHIMEI_PANEL_NAME,
				strnlen(LVDS_CHIMEI_PANEL_NAME,
					PANEL_NAME_MAX_LEN)))
				return 0;
		}
	} else if (machine_is_apq8064_mtp()) {
		if (!strncmp(name, MIPI_VIDEO_TOSHIBA_WSVGA_PANEL_NAME,
			strnlen(MIPI_VIDEO_TOSHIBA_WSVGA_PANEL_NAME,
				PANEL_NAME_MAX_LEN)))
			return 0;
	} else if (machine_is_apq8064_cdp()) {
		if (!strncmp(name, LVDS_CHIMEI_PANEL_NAME,
			strnlen(LVDS_CHIMEI_PANEL_NAME,
				PANEL_NAME_MAX_LEN)))
			return 0;
	} else if (machine_is_mpq8064_dtv()) {
		if (!strncmp(name, LVDS_FRC_PANEL_NAME,
			strnlen(LVDS_FRC_PANEL_NAME,
			PANEL_NAME_MAX_LEN))) {
			set_mdp_clocks_for_wuxga();
			return 0;
		}
	}
#else
	if (!strncmp(name, MIPI_VIDEO_ORISE_OPPO_PANEL_NAME,
		strnlen(MIPI_VIDEO_ORISE_OPPO_PANEL_NAME,
			PANEL_NAME_MAX_LEN)))
		return 0;
#endif
/* OPPO 2012-07-24 zhengzk Modify for MIPI end */

	if (!strncmp(name, HDMI_PANEL_NAME,
			strnlen(HDMI_PANEL_NAME,
				PANEL_NAME_MAX_LEN))) {
		if (apq8064_hdmi_as_primary_selected())
			set_mdp_clocks_for_wuxga();
		return 0;
	}


	return -ENODEV;
}
static int __init acpuclk_8064_probe(struct platform_device *pdev)
{
	if (cpu_is_apq8064ab() ||
		SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2) {
		acpuclk_8064_params.hfpll_data->low_vdd_l_max = 37;
		acpuclk_8064_params.hfpll_data->nom_vdd_l_max = 74;
	}

	return acpuclk_krait_init(&pdev->dev, &acpuclk_8064_params);
}
static int lvds_pixel_remap(void)
{
	if (machine_is_apq8064_cdp() ||
	    machine_is_apq8064_liquid()) {
		u32 ver = socinfo_get_version();
		if ((SOCINFO_VERSION_MAJOR(ver) == 1) &&
		    (SOCINFO_VERSION_MINOR(ver) == 0))
			return 1;
	}
	return 0;
}
static int lvds_pixel_remap(void)
{
	if (machine_is_apq8064_cdp() ||
	    machine_is_apq8064_liquid()) {
		u32 ver = socinfo_get_platform_version(); //+++ ASUS_BSP : miniporting
		if ((SOCINFO_VERSION_MAJOR(ver) == 1) &&
		    (SOCINFO_VERSION_MINOR(ver) == 0))
			return 1;
	}
	return 0;
}
Exemple #21
0
void __init apq8064_init_gpu(void)
{
	unsigned int version = socinfo_get_version();

	if ((SOCINFO_VERSION_MAJOR(version) == 1) &&
			(SOCINFO_VERSION_MINOR(version) == 1))
		kgsl_3d0_pdata.chipid = ADRENO_CHIPID(3, 2, 0, 1);
	else
		kgsl_3d0_pdata.chipid = ADRENO_CHIPID(3, 2, 0, 0);

	platform_device_register(&device_kgsl_3d0);
}
void __init msm8930_init_mmc(void)
{
#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
	/*
	 * When eMMC runs in DDR mode on CDP platform, we have
	 * seen instability due to DATA CRC errors. These errors are
	 * attributed to long physical path between MSM and eMMC on CDP.
	 * So let's not enable the DDR mode on CDP platform but let other
	 * platforms take advantage of eMMC DDR mode.
	 */
	if (!machine_is_msm8930_cdp())
		msm8960_sdc1_data.uhs_caps |= (MMC_CAP_1_8V_DDR |
					       MMC_CAP_UHS_DDR50);
	/* SDC1 : eMMC card connected */
	msm_add_sdcc(1, &msm8960_sdc1_data);
#endif
#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
	/*
	 * All 8930 platform boards using the 1.2 SoC have been reworked so that
	 * the sd card detect line's esd circuit is no longer powered by the sd
	 * card's voltage regulator. So this means we can turn the regulator off
	 * to save power without affecting the sd card detect functionality.
	 * This change to the boards will be true for newer versions of the SoC
	 * as well.
	 */
	if ((SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 1 &&
			SOCINFO_VERSION_MINOR(socinfo_get_version()) >= 2) ||
			machine_is_msm8930_cdp()) {
		msm8960_sdc3_data.vreg_data->vdd_data->always_on = false;
		msm8960_sdc3_data.vreg_data->vdd_data->reset_at_init = false;
	}

	/* SDC3: External card slot */
	if (!machine_is_msm8930_cdp()) {
		msm8960_sdc3_data.wpswitch_gpio = 0;
		msm8960_sdc3_data.is_wpswitch_active_low = false;
	}
	
	/* Emily Jiang, 20130326, modify clk rate from MMC_CAP_UHS_SDR104 to MMC_CAP_UHS_SDR25,in order to support UHS-1 SDR104 sd card. {*/  
	if ( msm_project_id <= SAPPORO && system_rev >= EVT0) {
		msm8960_sdc3_data.uhs_caps |= (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
			MMC_CAP_MAX_CURRENT_800);
	} else { 
		// unknown project
		msm8960_sdc3_data.uhs_caps |= (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
			MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50 |
			MMC_CAP_UHS_SDR104 | MMC_CAP_MAX_CURRENT_800);
	}
	/* } Emily Jiang, 20130326, modify clk rate from MMC_CAP_UHS_SDR104 to MMC_CAP_UHS_SDR25,in order to support UHS-1 SDR104 sd card. */
	msm_add_sdcc(3, &msm8960_sdc3_data);
#endif
}
Exemple #23
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static void __init halibut_init(void)
{
	if (socinfo_init() < 0)
		BUG();

	if (machine_is_msm7201a_ffa()) {
		smc91x_resources[0].start = 0x98000300;
		smc91x_resources[0].end = 0x98000400;
		smc91x_resources[1].start = MSM_GPIO_TO_INT(85);
		smc91x_resources[1].end = MSM_GPIO_TO_INT(85);
	}

	/* All 7x01 2.0 based boards are expected to have RAM chips capable
	 * of 160 MHz. */
	if (cpu_is_msm7x01()
	    && SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2)
		halibut_clock_data.max_axi_khz = 160000;

#if defined(CONFIG_MSM_SERIAL_DEBUGGER)
	msm_serial_debug_init(MSM_UART3_PHYS, INT_UART3,
			      &msm_device_uart3.dev, 1);
#endif
	msm_hsusb_pdata.soc_version = socinfo_get_version();
	msm_acpu_clock_init(&halibut_clock_data);
	msm_device_hsusb_peripheral.dev.platform_data = &msm_hsusb_pdata,
	msm_device_hsusb_host.dev.platform_data = &msm_hsusb_pdata,
	platform_add_devices(devices, ARRAY_SIZE(devices));
	msm_camera_add_device();
	msm_device_i2c_init();
	i2c_register_board_info(0, i2c_devices, ARRAY_SIZE(i2c_devices));

#ifdef CONFIG_SURF_FFA_GPIO_KEYPAD
	if (machine_is_msm7201a_ffa())
		platform_device_register(&keypad_device_7k_ffa);
	else
		platform_device_register(&keypad_device_surf);
#endif

	halibut_init_mmc();
#ifdef CONFIG_USB_FUNCTION
	hsusb_gpio_init();
#endif
	msm_fb_add_devices();
	bt_power_init();
#ifdef CONFIG_USB_ANDROID
	msm_hsusb_rpc_connect();
	msm_hsusb_set_vbus_state(1) ;
#endif
	msm_pm_set_platform_data(msm_pm_data);
}
void __init msm8930_init_gpu(void)
{
	unsigned int version = socinfo_get_version();

	if (cpu_is_msm8930aa())
		kgsl_3d0_pdata.pwrlevel[0].gpu_freq = 450000000;

	if ((SOCINFO_VERSION_MAJOR(version) == 1) &&
		(SOCINFO_VERSION_MINOR(version) == 2))
		kgsl_3d0_pdata.chipid = ADRENO_CHIPID(3, 0, 5, 2);
	else
		kgsl_3d0_pdata.chipid = ADRENO_CHIPID(3, 0, 5, 0);

	platform_device_register(&device_kgsl_3d0);
}
static int __init acpuclk_8064_probe(struct platform_device *pdev)
{
    if (cpu_is_apq8064ab() ||
            SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 2) {
        acpuclk_8064_params.hfpll_data->low_vdd_l_max = 37;
        acpuclk_8064_params.hfpll_data->nom_vdd_l_max = 74;
    }

#ifdef CONFIG_PANTECH_SMB347_CHARGER
    if(pantech_charging_status())
        acpuclk_8064_params.pvs_tables = pvs_tables_offline;
#endif

    return acpuclk_krait_init(&pdev->dev, &acpuclk_8064_params);
}
static void __init marvelc_map_io(void)
{
	printk("marvelc_init_map_io()\n");
	msm_map_common_io();
	if (socinfo_init() < 0)
		BUG();
#ifdef CONFIG_CACHE_L2X0
	/* 7x27 has 256KB L2 cache:
	64Kb/Way and 4-Way Associativity;
	evmon/parity/share disabled. */
	if ((SOCINFO_VERSION_MAJOR(socinfo_get_version()) > 1)
		|| ((SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 1)
		&& (SOCINFO_VERSION_MINOR(socinfo_get_version()) >= 3)))
		{
			/* R/W latency: 4 cycles; */
			l2x0_init(MSM_L2CC_BASE, 0x0006801B, 0xfe000000);
			printk("Marvelc_init L2-cache latency 4 cyc for 7x27-t\n");
		}else{
		/* R/W latency: 3 cycles; */
	l2x0_init(MSM_L2CC_BASE, 0x00068012, 0xfe000000);
			printk("Marvelc_init L2-cache latency 3 cyc for 7x27\n");
		}
#endif
}
void __init msm8x25_kgsl_3d0_init(void)
{
	if (cpu_is_msm8625()) {
		kgsl_3d0_pdata.idle_timeout = HZ/5;
		kgsl_3d0_pdata.strtstp_sleepwake = false;

		if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) >= 2)
			/* 8x25 v2.0 & above supports a higher GPU frequency */
		kgsl_3d0_pdata.pwrlevel[0].gpu_freq = 320000000;
		else
			kgsl_3d0_pdata.pwrlevel[0].gpu_freq = 300000000;

		kgsl_3d0_pdata.pwrlevel[0].bus_freq = 200000000;
	}
}
void __init msm8930_init_mmc(void)
{
#ifdef CONFIG_MMC_MSM_SDC1_SUPPORT
	/*
	 * When eMMC runs in DDR mode on CDP platform, we have
	 * seen instability due to DATA CRC errors. These errors are
	 * attributed to long physical path between MSM and eMMC on CDP.
	 * So let's not enable the DDR mode on CDP platform but let other
	 * platforms take advantage of eMMC DDR mode.
	 */
	if (!machine_is_msm8930_cdp())
		msm8960_sdc1_data.uhs_caps |= (MMC_CAP_1_8V_DDR |
					       MMC_CAP_UHS_DDR50);
	/* SDC1 : eMMC card connected */
	msm_add_sdcc(1, &msm8960_sdc1_data);
#endif
#ifdef CONFIG_MMC_MSM_SDC3_SUPPORT
	/*
	 * All 8930 platform boards using the 1.2 SoC have been reworked so that
	 * the sd card detect line's esd circuit is no longer powered by the sd
	 * card's voltage regulator. So this means we can turn the regulator off
	 * to save power without affecting the sd card detect functionality.
	 * This change to the boards will be true for newer versions of the SoC
	 * as well.
	 */
	if (SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 1 &&
			SOCINFO_VERSION_MINOR(socinfo_get_version()) < 2) {
		msm8960_sdc3_data.vreg_data->vdd_data->always_on = true;
		msm8960_sdc3_data.vreg_data->vdd_data->reset_at_init = true;
	}
	/* SDC3: External card slot */
	if (!machine_is_msm8930_cdp()) {
		msm8960_sdc3_data.wpswitch_gpio = 0;
		msm8960_sdc3_data.is_wpswitch_active_low = false;
	}

	if (machine_is_msm8930_evt()) {
		msm8960_sdc3_data.status_gpio = 90;
		msm8960_sdc3_data.status_irq = MSM_GPIO_TO_INT(90);
	}

	msm_add_sdcc(3, &msm8960_sdc3_data);
#endif
#ifdef CONFIG_MMC_MSM_SDC4_SUPPORT
	/* SDC4: WIFI BCM4334 */
	msm_add_sdcc(4, &msm8960_sdc4_data);
#endif
}
Exemple #29
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void __init elite_init_gpu(void)
{
	unsigned int version = socinfo_get_version();

	if (SOCINFO_VERSION_MAJOR(version) == 1) {
		struct kgsl_device_platform_data *kgsl_3d0_pdata =
				msm_kgsl_3d0.dev.platform_data;
		kgsl_3d0_pdata->pwrlevel[0].gpu_freq = 320000000;
		kgsl_3d0_pdata->pwrlevel[1].gpu_freq = 266667000;
		kgsl_3d0_pdata->nap_allowed = false;
	}

	platform_device_register(&device_kgsl_3d0);
	platform_device_register(&msm_kgsl_2d0);
	platform_device_register(&msm_kgsl_2d1);
}
static int msm_fb_detect_panel(const char *name)
{
	u32 version;
	if (machine_is_apq8064_liquid()) {
		version = socinfo_get_platform_version();
		if ((SOCINFO_VERSION_MAJOR(version) == 1) &&
			(SOCINFO_VERSION_MINOR(version) == 1)) {
			if (!strncmp(name, MIPI_VIDEO_CHIMEI_WXGA_PANEL_NAME,
				strnlen(MIPI_VIDEO_CHIMEI_WXGA_PANEL_NAME,
					PANEL_NAME_MAX_LEN)))
				return 0;
		} else {
			if (!strncmp(name, LVDS_CHIMEI_PANEL_NAME,
				strnlen(LVDS_CHIMEI_PANEL_NAME,
					PANEL_NAME_MAX_LEN)))
				return 0;
		}
	} else if (machine_is_apq8064_mtp()) {
		if (!strncmp(name, MIPI_VIDEO_TOSHIBA_WSVGA_PANEL_NAME,
			strnlen(MIPI_VIDEO_TOSHIBA_WSVGA_PANEL_NAME,
				PANEL_NAME_MAX_LEN)))
			return 0;
	} else if (machine_is_apq8064_cdp()) {
		if (!strncmp(name, LVDS_CHIMEI_PANEL_NAME,
			strnlen(LVDS_CHIMEI_PANEL_NAME,
				PANEL_NAME_MAX_LEN)))
			return 0;
	} else if (machine_is_mpq8064_dtv()) {
		if (!strncmp(name, LVDS_FRC_PANEL_NAME,
			strnlen(LVDS_FRC_PANEL_NAME,
			PANEL_NAME_MAX_LEN))) {
			set_mdp_clocks_for_wuxga();
			return 0;
		}
	}

	if (!strncmp(name, HDMI_PANEL_NAME,
			strnlen(HDMI_PANEL_NAME,
				PANEL_NAME_MAX_LEN))) {
		if (apq8064_hdmi_as_primary_selected())
			set_mdp_clocks_for_wuxga();
		return 0;
	}


	return -ENODEV;
}