static int spi_qmsi_configure(struct device *dev, struct spi_config *config) { struct spi_qmsi_runtime *context = dev->driver_data; qm_spi_config_t *cfg = &context->cfg; cfg->frame_size = SPI_WORD_SIZE_GET(config->config) - 1; cfg->bus_mode = config_to_bmode(SPI_MODE(config->config)); /* As loopback is implemented inside the controller, * the bus mode doesn't matter. */ context->loopback = SPI_MODE(config->config) & SPI_MODE_LOOP; cfg->clk_divider = config->max_sys_freq; /* Will set the configuration before the transfer starts */ return 0; }
static int spi_dw_configure(struct device *dev, struct spi_config *config) { const struct spi_dw_config *info = dev->config->config_info; struct spi_dw_data *spi = dev->driver_data; u32_t flags = config->config; u32_t ctrlr0 = 0; u32_t mode; SYS_LOG_DBG("%p (0x%x), %p", dev, info->regs, config); /* Check status */ if (!_spi_dw_is_controller_ready(dev)) { SYS_LOG_DBG("Controller is busy"); return -EBUSY; } /* Word size */ ctrlr0 |= DW_SPI_CTRLR0_DFS(SPI_WORD_SIZE_GET(flags)); /* Determine how many bytes are required per-frame */ spi->dfs = SPI_WS_TO_DFS(SPI_WORD_SIZE_GET(flags)); /* SPI mode */ mode = SPI_MODE(flags); if (mode & SPI_MODE_CPOL) { ctrlr0 |= DW_SPI_CTRLR0_SCPOL; } if (mode & SPI_MODE_CPHA) { ctrlr0 |= DW_SPI_CTRLR0_SCPH; } if (mode & SPI_MODE_LOOP) { ctrlr0 |= DW_SPI_CTRLR0_SRL; } /* Installing the configuration */ write_ctrlr0(ctrlr0, info->regs); /* * Configure the rate. Use this small hack to allow the user to call * spi_configure() with both a divider (as the driver was initially * written) and a frequency (as the SPI API suggests to). The clock * divider is a 16bit value, hence we can fairly, and safely, assume * that everything above this value is a frequency. The trade-off is * that if one wants to use a bus frequency of 64kHz (or less), it has * the use a divider... */ if (config->max_sys_freq > 0xffff) { write_baudr(SPI_DW_CLK_DIVIDER(config->max_sys_freq), info->regs); } else { write_baudr(config->max_sys_freq, info->regs); } return 0; }
static int spi_dw_configure(struct device *dev, struct spi_config *config) { struct spi_dw_config *info = dev->config->config_info; struct spi_dw_data *spi = dev->driver_data; uint32_t flags = config->config; uint32_t ctrlr0 = 0; uint32_t mode; DBG("%s: %p (0x%x), %p\n", __func__, dev, info->regs, config); /* Check status */ if (!_spi_dw_is_controller_ready(dev)) { DBG("%s: Controller is busy\n", __func__); return DEV_USED; } /* Word size */ ctrlr0 |= DW_SPI_CTRLR0_DFS(SPI_WORD_SIZE_GET(flags)); /* Determine how many bytes are required per-frame */ spi->dfs = SPI_DFS_TO_BYTES(SPI_WORD_SIZE_GET(flags)); /* SPI mode */ mode = SPI_MODE(flags); if (mode & SPI_MODE_CPOL) { ctrlr0 |= DW_SPI_CTRLR0_SCPOL; } if (mode & SPI_MODE_CPHA) { ctrlr0 |= DW_SPI_CTRLR0_SCPH; } if (mode & SPI_MODE_LOOP) { ctrlr0 |= DW_SPI_CTRLR0_SRL; } /* Installing the configuration */ write_ctrlr0(ctrlr0, info->regs); /* Configuring the rate */ write_baudr(config->max_sys_freq, info->regs); return DEV_OK; }