/******************************************************************************
* This function reads a number of bytes from an IIC chip into a
* specified buffer.
* This function implements extended 16 bit addressing.
*
* @param ChipAddress contains the address of the IIC core.
* @param RegAddress contains the address of the register to write to.
* @param pBuffer contains the address of the data buffer to be filled.
* @param ByteCount contains the number of bytes in the buffer to be read.
* This value is constrained by the page size of the device such
* that up to 64K may be read in one call.
*
* @return The number of bytes read. A value less than the specified input
* value indicates an error.
*
* @note None.
*
******************************************************************************/
int fmc_iic_axi_IicERead(fmc_iic_t *pIIC, Xuint8 ChipAddress, Xuint16 RegAddress,
Xuint8 *pBuffer, Xuint8 ByteCount)
{
Xuint8 ReceivedByteCount = 0;
Xuint8 SentByteCount = 0;
Xuint8 WriteBuffer[2];
Xuint8 StatusReg;
XStatus TestStatus=XST_FAILURE;
int cnt = 0;
fmc_iic_axi_t *pContext = (fmc_iic_axi_t *)(pIIC->pContext);
#if 1
// Make sure all the Fifo's are cleared and Bus is Not busy.
do
{
StatusReg = Xil_In8(pContext->CoreAddress + XIIC_SR_REG_OFFSET);
//xil_printf("[%s] Xil_In8(pContext->CoreAddress + XIIC_SR_REG_OFFSET) => 0x%02X\n\r", pContext->szName, StatusReg );
StatusReg = StatusReg & (XIIC_SR_RX_FIFO_EMPTY_MASK |
XIIC_SR_TX_FIFO_EMPTY_MASK |
XIIC_SR_BUS_BUSY_MASK);
} while (StatusReg != (XIIC_SR_RX_FIFO_EMPTY_MASK |
XIIC_SR_TX_FIFO_EMPTY_MASK));
#endif
/*
* A temporary write buffer must be used which contains both the address
* and the data to be written, put the address in first
*/
WriteBuffer[0] = (Xuint8)((RegAddress>>8) & 0x00FF);
WriteBuffer[1] = (Xuint8)( RegAddress & 0x00FF);
// Position the Read pointer to specific location.
do
{
StatusReg = Xil_In8(pContext->CoreAddress + XIIC_SR_REG_OFFSET);
//xil_printf("[%s] Xil_In8(pContext->CoreAddress + XIIC_SR_REG_OFFSET) => 0x%02X\n\r", pContext->szName, StatusReg );
if(!(StatusReg & XIIC_SR_BUS_BUSY_MASK))
{
SentByteCount = XIic_DynSend(pContext->CoreAddress, ChipAddress,
WriteBuffer, 2,
XIIC_REPEATED_START);
}
cnt++;
}while(SentByteCount != 1 && (cnt < 100));
// Error writing chip address so return SentByteCount
if (SentByteCount < 1) { return SentByteCount; }
// Receive the data.
ReceivedByteCount = XIic_DynRecv(pContext->CoreAddress, ChipAddress, pBuffer,
ByteCount);
// Return the number of bytes received.
return ReceivedByteCount;
}
/******************************************************************************
* This function reads a number of bytes from an IIC chip into a
* specified buffer.
*
* @param ChipAddress contains the address of the IIC core.
* @param RegAddress contains the address of the register to write to.
* @param pBuffer contains the address of the data buffer to be filled.
* @param ByteCount contains the number of bytes in the buffer to be read.
* This value is constrained by the page size of the device such
* that up to 64K may be read in one call.
*
* @return The number of bytes read. A value less than the specified input
* value indicates an error.
*
* @note None.
*
******************************************************************************/
int fmc_iic_axi_IicRead(fmc_iic_t *pIIC, Xuint8 ChipAddress, Xuint8 RegAddress,
Xuint8 *pBuffer, Xuint8 ByteCount)
{
Xuint8 ReceivedByteCount = 0;
Xuint8 SentByteCount = 0;
Xuint8 StatusReg;
XStatus TestStatus=XST_FAILURE;
int cnt = 0;
fmc_iic_axi_t *pContext = (fmc_iic_axi_t *)(pIIC->pContext);
#if 1
// Make sure all the Fifo's are cleared and Bus is Not busy.
do
{
StatusReg = Xil_In8(pContext->CoreAddress + XIIC_SR_REG_OFFSET);
//xil_printf("[%s] Xil_In8(pContext->CoreAddress + XIIC_SR_REG_OFFSET) => 0x%02X\n\r", pContext->szName, StatusReg );
StatusReg = StatusReg & (XIIC_SR_RX_FIFO_EMPTY_MASK |
XIIC_SR_TX_FIFO_EMPTY_MASK |
XIIC_SR_BUS_BUSY_MASK);
} while (StatusReg != (XIIC_SR_RX_FIFO_EMPTY_MASK |
XIIC_SR_TX_FIFO_EMPTY_MASK));
#endif
// Position the Read pointer to specific location.
do
{
StatusReg = Xil_In8(pContext->CoreAddress + XIIC_SR_REG_OFFSET);
//xil_printf("[%s] Xil_In8(pContext->CoreAddress + XIIC_SR_REG_OFFSET) => 0x%02X\n\r", pContext->szName, StatusReg );
if(!(StatusReg & XIIC_SR_BUS_BUSY_MASK))
{
SentByteCount = XIic_DynSend(pContext->CoreAddress, ChipAddress,
(Xuint8 *)&RegAddress, 1,
XIIC_REPEATED_START);
}
cnt++;
}while(SentByteCount != 1 && (cnt < 100));
// Error writing chip address so return SentByteCount
if (SentByteCount < 1) { return SentByteCount; }
// Receive the data.
ReceivedByteCount = XIic_DynRecv(pContext->CoreAddress, ChipAddress, pBuffer,
ByteCount);
// Return the number of bytes received.
return ReceivedByteCount;
}
/******************************************************************************
* This function initializes the IIC controller.
*
* @param CoreAddress contains the address of the IIC core.
*
* @return If successfull, returns 1. Otherwise, returns 0.
*
* @note None.
*
******************************************************************************/
int fmc_iic_axi_init( fmc_iic_t *pIIC, char szName[], Xuint32 CoreAddress )
{
XStatus Status;
Xuint8 StatusReg;
Xuint32 timeout = 10000;
//fmc_iic_axi_t *pContext = (fmc_iic_axi_t *)malloc( sizeof(fmc_iic_axi_t) );
//if ( pContext == NULL )
//{
// xil_printf("Failed to allocate context data for FMC-IIC-AXI implementation\n\r" );
// return 0;
//}
fmc_iic_axi_t *pContext = (fmc_iic_axi_t *) (pIIC->ContextBuffer);
if ( sizeof(fmc_iic_axi_t) > FMC_IIC_CONTEXT_BUFFER_SIZE )
{
printf("FMC_IIC_CONTEXT_BUFFER_SIZE is not large enough for fic_iic_xps_t structure (increase to %d)\n\r", sizeof(fmc_iic_axi_t) );
return 0;
}
pContext->CoreAddress = CoreAddress;
/*
* Initialize the IIC Core.
*/
Status = XIic_DynInit(pContext->CoreAddress);
if(Status != XST_SUCCESS)
{
printf("Failed to initialize I2C chain\n\r" );
return 0;
}
/*
* Check to see if the core was initialized successfully
*/
do
{
StatusReg = Xil_In8(pContext->CoreAddress + XIIC_SR_REG_OFFSET);
//xil_printf("[%s] Xil_In8(pContext->CoreAddress + XIIC_SR_REG_OFFSET) => 0x%02X\n\r", pContext->szName, StatusReg );
StatusReg = StatusReg & (XIIC_SR_RX_FIFO_EMPTY_MASK |
XIIC_SR_TX_FIFO_EMPTY_MASK |
XIIC_SR_BUS_BUSY_MASK);
} while ( (timeout-- > 0) &&
(StatusReg != (XIIC_SR_RX_FIFO_EMPTY_MASK | XIIC_SR_TX_FIFO_EMPTY_MASK)) );
/*
* Initialize the IIC structure
*/
pIIC->uVersion = 1;
strcpy( pIIC->szName, szName );
pIIC->pContext = (void *)pContext;
pIIC->fpGpoRead = &fmc_iic_axi_GpoRead;
pIIC->fpGpoWrite = &fmc_iic_axi_GpoWrite;
pIIC->fpIicRead = &fmc_iic_axi_IicRead;
pIIC->fpIicWrite = &fmc_iic_axi_IicWrite;
pIIC->fpIicERead = &fmc_iic_axi_IicERead;
pIIC->fpIicEWrite = &fmc_iic_axi_IicEWrite;
return 1;
}
/******************************************************************************
* This function writes a buffer of bytes to the IIC chip.
* This function implements extended 16 bit addressing.
*
* @param ChipAddress contains the address of the chip.
* @param RegAddress contains the address of the register to write to.
* @param pBuffer contains the address of the data to write.
* @param ByteCount contains the number of bytes in the buffer to be written.
* Note that this should not exceed the page size as noted by the
* constant PAGE_SIZE.
*
* @return The number of bytes written, a value less than that which was
* specified as an input indicates an error.
*
* @note None.
*
******************************************************************************/
int fmc_iic_axi_IicEWrite(fmc_iic_t *pIIC, Xuint8 ChipAddress, Xuint16 RegAddress,
Xuint8 *pBuffer, Xuint8 ByteCount)
{
Xuint8 SentByteCount;
Xuint8 WriteBuffer[PAGE_SIZE + 1];
Xuint8 Index;
Xuint8 StatusReg;
fmc_iic_axi_t *pContext = (fmc_iic_axi_t *)(pIIC->pContext);
#if 1
// Make sure all the Fifo's are cleared and Bus is Not busy.
do
{
StatusReg = Xil_In8(pContext->CoreAddress + XIIC_SR_REG_OFFSET);
//xil_printf("[%s] Xil_In8(pContext->CoreAddress + XIIC_SR_REG_OFFSET) => 0x%02X\n\r", pContext->szName, StatusReg );
StatusReg = StatusReg & (XIIC_SR_RX_FIFO_EMPTY_MASK |
XIIC_SR_TX_FIFO_EMPTY_MASK |
XIIC_SR_BUS_BUSY_MASK);
} while (StatusReg != (XIIC_SR_RX_FIFO_EMPTY_MASK |
XIIC_SR_TX_FIFO_EMPTY_MASK));
#endif
/*
* A temporary write buffer must be used which contains both the address
* and the data to be written, put the address in first
*/
WriteBuffer[0] = (Xuint8)((RegAddress>>8) & 0x00FF);
WriteBuffer[1] = (Xuint8)( RegAddress & 0x00FF);
/*
* Put the data in the write buffer following the address.
*/
for (Index = 0; Index < ByteCount; Index++)
{
WriteBuffer[Index + 2] = pBuffer[Index];
}
/*
* Write data at the specified address.
*/
SentByteCount = XIic_DynSend(pContext->CoreAddress, ChipAddress, WriteBuffer,
ByteCount + 2, XIIC_STOP);
if (SentByteCount < 1) { SentByteCount = 1; }
// Return the number of bytes written.
return SentByteCount - 1;
}
static void TimerIntrHandler(void *CallBackRef)
{
unsigned int cpu0;
XScuTimer *TimerInstancePtr = (XScuTimer *) CallBackRef;
XScuTimer_ClearInterruptStatus(TimerInstancePtr);
//load timer
XScuTimer_LoadTimer(&Timer, TIMER_LOAD_VALUE);
//start timer
cpu0 = Xil_In8(LED_PAT);
XGpio_DiscreteWrite(&Gpio,CHANNEL,cpu0);
XScuTimer_Start(&Timer);
}
int Xil_TestIO8(u8 *Addr, int Len, u8 Value)
{
u8 ValueIn;
int Index;
for (Index = 0; Index < Len; Index++) {
Xil_Out8((u32)Addr, Value);
ValueIn = Xil_In8((u32)Addr);
if (Value != ValueIn) {
return -1;
}
}
return 0;
}
s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value)
{
u8 ValueIn;
s32 Index;
s32 Status = 0;
for (Index = 0; Index < Length; Index++) {
Xil_Out8((INTPTR)Addr, Value);
ValueIn = Xil_In8((INTPTR)Addr);
if ((Value != ValueIn) && (Status == 0)) {
Status = -1;
break;
}
}
return Status;
}
void encripta(void)
{
int bo_0 = 0;
int bo_1 = 0;
int bo_2 = 0;
int bo_3 = 0;
int config = 0;
int i;
int cnt =0;
unsigned int key[4];
int config1, config2, config3, config4, config5, config6, config7, config8, config9, config10;
/* int debug_signal_0 = 0;
int debug_signal_31, debug_signal_32, debug_signal_33, debug_signal_34,debug_signal_35, debug_signal_36, debug_signal_37, debug_signal_38, debug_signal_39;
int debug_signal_1 = 0;
int debug_signal_2 = 0;
int debug_signal_3 = 0;
*/
key[0] = 0x09cf4f3c;
key[1] = 0xabf71588;
key[2] = 0x28aed2a6;
key[3] = 0x2b7e1516;
i = aes_expand_key(key);
xil_printf("i = %d\n\r",i);
/*
xil_printf("Teste: %d %d %d %d %d\n\r", bo_0, bo_1, bo_2, bo_3, config);
// Set config = 1
xil_printf("Inicializando CONFIG\n\r");
Xil_Out8(AES_BASEADDR+CONFIG_0_OFFSET,0x10);
// verifica config
xil_printf("\nConferindo Config\n\r");
config = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
xil_printf("Config = %08x \n\r",config);
//printf("Endereço de reg16 é 0x%08x \n",AES_BASEADDR+CONFIG_OFFSET);
// escreve a chave e inicializa KeyExpansion
xil_printf("Escrevendo chave K0\n\r");
Xil_Out32(AES_BASEADDR+BI_E_0_OFFSET,0x09cf4f3c);
Xil_Out32(AES_BASEADDR+BI_E_1_OFFSET,0xabf71588);
Xil_Out32(AES_BASEADDR+BI_E_2_OFFSET,0x28aed2a6);
Xil_Out32(AES_BASEADDR+BI_E_3_OFFSET,0x2b7e1516);
xil_printf("Inicializando Key_Expansion\n\r");
Xil_Out8(AES_BASEADDR+CONFIG_0_OFFSET,0x11);
xil_printf("Colocando atraso...\n\r");
//while( config == 0xca10d009 )
xil_printf("\n\rConferindo se Key_Expansion terminou\n\r");
config = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
xil_printf("Config = %08x \n\r",config);
*/
xil_printf("Preparando Encriptação\n\r");
Xil_Out8(AES_BASEADDR+CONFIG_0_OFFSET,0x01);
xil_printf("Escrevendo bloco de entrada 0x3243f6a8885a308d313198a2e0370734\n\r");
Xil_Out32(AES_BASEADDR+BI_E_0_OFFSET,0xe0370734);
Xil_Out32(AES_BASEADDR+BI_E_1_OFFSET,0x313198a2);
Xil_Out32(AES_BASEADDR+BI_E_2_OFFSET,0x885a308d);
Xil_Out32(AES_BASEADDR+BI_E_3_OFFSET,0x3243f6a8);
xil_printf("Inicializando Encriptação\n\r");
Xil_Out8(AES_BASEADDR+CONFIG_1_OFFSET,0x01);
config = Xil_In8(AES_BASEADDR+CONFIG_3_OFFSET);
while ( config != 3)
{
config = Xil_In8(AES_BASEADDR+CONFIG_3_OFFSET);
cnt++;
}
xil_printf("contador = %d\n\r",cnt);
config1 = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
config2 = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
config3 = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
config4 = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
config5 = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
config6 = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
config7 = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
config8 = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
config9 = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
config10 = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
xil_printf("Config1 = %08x \n\r",config1);
xil_printf("Config2 = %08x \n\r",config2);
xil_printf("Config3 = %08x \n\r",config3);
xil_printf("Config4 = %08x \n\r",config4);
xil_printf("Config5 = %08x \n\r",config5);
xil_printf("Config6 = %08x \n\r",config6);
xil_printf("Config7 = %08x \n\r",config7);
xil_printf("Config8 = %08x \n\r",config8);
xil_printf("Config9 = %08x \n\r",config9);
xil_printf("Config10 = %08x \n\r",config10);
for( i=0; i<2; i++)
{
//xil_printf("Conferindo Sinais Internos\n\r");
//config = Xil_In32(AES_BASEADDR+CONFIG_OFFSET);
//xil_printf("Config = %08x \n\r",config);
/* Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_S0);
//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_31 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_32 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_33 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_34 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_35 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_36 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_37 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_38 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_39 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_31);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_32);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_33);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_34);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_35);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_36);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_37);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_38);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_39);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_0);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_1);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_2);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z0);
//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_K2);
debug_signal_31 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z1);
debug_signal_32 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z2);
debug_signal_33 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z3);
debug_signal_34 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z4);
debug_signal_35 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z0);
debug_signal_36 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_37 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_K2);
debug_signal_38 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_39 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
xil_printf("z0 = %08x __ ___ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);
xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_31);
xil_printf("z1 = %08x __ ___ ___ __\n\r",debug_signal_32);
xil_printf("z2 = %08x __ ___ ___ __\n\r",debug_signal_33);
xil_printf("z3 = %08x __ ___ ___ __\n\r",debug_signal_34);
xil_printf("z4 = %08x __ ___ ___ __\n\r",debug_signal_35);
xil_printf("z0 = %08x __ ___ ___ __\n\r",debug_signal_36);
xil_printf("z0 = %08x __ ___ ___ __\n\r",debug_signal_37);
xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_38);
xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_39);
xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_0);
xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_1);
xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_2);
//config = Xil_In32(AES_BASEADDR+CONFIG_OFFSET);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_K2);
//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
xil_printf("k2 = %08x __ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z0);
//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
xil_printf("z0 = %08x __ ___ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z0);
//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
xil_printf("z0 = %08x __ ___ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);
//xil_printf("Config = %08x \n\r",config);
*/
xil_printf("Lendo bloco encriptado\n\r");
bo_0 = Xil_In32(AES_BASEADDR+BO_E_0_OFFSET);
bo_1 = Xil_In32(AES_BASEADDR+BO_E_1_OFFSET);
bo_2 = Xil_In32(AES_BASEADDR+BO_E_2_OFFSET);
bo_3 = Xil_In32(AES_BASEADDR+BO_E_3_OFFSET);
xil_printf("Bo_e = %x %x %x %x\n\r",bo_3, bo_2, bo_1, bo_0);
/* xil_printf("Reinicializando Encriptação\n\r");
Xil_Out8(AES_BASEADDR+CONFIG_0_OFFSET,0x08);
Xil_Out8(AES_BASEADDR+CONFIG_0_OFFSET,0x0A);
*/
//xil_printf("-----------------------------------------\n\r");
}
// xil_printf("Preparando Decriptação\n\r");
// Xil_Out8(AES_BASEADDR+CONFIG_1_OFFSET,0x01);
xil_printf("Escrevendo bloco de entrada bo_e\n\r");
Xil_Out32(AES_BASEADDR+BI_D_0_OFFSET,bo_0);
Xil_Out32(AES_BASEADDR+BI_D_1_OFFSET,bo_1);
Xil_Out32(AES_BASEADDR+BI_D_2_OFFSET,bo_2);
Xil_Out32(AES_BASEADDR+BI_D_3_OFFSET,bo_3);
xil_printf("Lendo bloco escrito para decriptação\n\r");
bo_0 = Xil_In32(AES_BASEADDR+BO_D_0_OFFSET);
bo_1 = Xil_In32(AES_BASEADDR+BO_D_1_OFFSET);
bo_2 = Xil_In32(AES_BASEADDR+BO_D_2_OFFSET);
bo_3 = Xil_In32(AES_BASEADDR+BO_D_3_OFFSET);
xil_printf("Bo_e = %x %x %x %x\n\r",bo_3, bo_2, bo_1, bo_0);
xil_printf("Inicializando Decriptação\n\r");
Xil_Out8(AES_BASEADDR+CONFIG_2_OFFSET,0x01);
for( i=0; i<2; i++)
{
//xil_printf("Conferindo Sinais Internos\n\r");
//config = Xil_In32(AES_BASEADDR+CONFIG_OFFSET);
//xil_printf("Config = %08x \n\r",config);
/* Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_S0);
//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_31 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_32 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_33 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_34 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_35 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_36 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_37 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_38 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_39 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_31);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_32);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_33);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_34);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_35);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_36);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_37);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_38);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_39);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_0);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_1);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_2);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z0);
//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_K2);
debug_signal_31 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z1);
debug_signal_32 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z2);
debug_signal_33 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z3);
debug_signal_34 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z4);
debug_signal_35 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z0);
debug_signal_36 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_37 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_K2);
debug_signal_38 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_39 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
xil_printf("z0 = %08x __ ___ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);
xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_31);
xil_printf("z1 = %08x __ ___ ___ __\n\r",debug_signal_32);
xil_printf("z2 = %08x __ ___ ___ __\n\r",debug_signal_33);
xil_printf("z3 = %08x __ ___ ___ __\n\r",debug_signal_34);
xil_printf("z4 = %08x __ ___ ___ __\n\r",debug_signal_35);
xil_printf("z0 = %08x __ ___ ___ __\n\r",debug_signal_36);
xil_printf("z0 = %08x __ ___ ___ __\n\r",debug_signal_37);
xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_38);
xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_39);
xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_0);
xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_1);
xil_printf("k2 = %08x __ ___ ___ __\n\r",debug_signal_2);
//config = Xil_In32(AES_BASEADDR+CONFIG_OFFSET);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_K2);
//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
xil_printf("k2 = %08x __ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z0);
//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
xil_printf("z0 = %08x __ ___ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_Z0);
//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
xil_printf("z0 = %08x __ ___ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);
//xil_printf("Config = %08x \n\r",config);
*/
xil_printf("Lendo bloco decriptado\n\r");
bo_0 = Xil_In32(AES_BASEADDR+BO_D_0_OFFSET);
bo_1 = Xil_In32(AES_BASEADDR+BO_D_1_OFFSET);
bo_2 = Xil_In32(AES_BASEADDR+BO_D_2_OFFSET);
bo_3 = Xil_In32(AES_BASEADDR+BO_D_3_OFFSET);
xil_printf("Bo_d = %x %x %x %x\n\r",bo_3, bo_2, bo_1, bo_0);
/* xil_printf("Reinicializando Encriptação\n\r");
Xil_Out8(AES_BASEADDR+CONFIG_0_OFFSET,0x08);
Xil_Out8(AES_BASEADDR+CONFIG_0_OFFSET,0x0A);
*/
//xil_printf("-----------------------------------------\n\r");
}
xil_printf("Lendo config\n\r");
config = Xil_In32(AES_BASEADDR+CONFIG_0_OFFSET);
xil_printf("Config = %8x\n\r",config);
/*
Xil_Out8(AES_BASEADDR+DEBUG_SEL_OFFSET,CODE_S0);
//debug_signal_0 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_0_OFFSET);
//debug_signal_1 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_1_OFFSET);
//debug_signal_2 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_2_OFFSET);
debug_signal_3 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_31 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_32 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
debug_signal_33 = Xil_In32(AES_BASEADDR+DEBUG_SIGNAL_3_OFFSET);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_3);//,debug_signal_2,debug_signal_1,debug_signal_0);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_31);
xil_printf("s0 = %08x __ ___ ___ __\n\r",debug_signal_32);
xil_printf("s0 = %08x __ ___ ___ __\n\r\n\r",debug_signal_33);
xil_printf("Lendo bloco encriptado\n\r");
bo_0 = Xil_In32(AES_BASEADDR+BO_E_0_OFFSET);
bo_1 = Xil_In32(AES_BASEADDR+BO_E_1_OFFSET);
bo_2 = Xil_In32(AES_BASEADDR+BO_E_2_OFFSET);
bo_3 = Xil_In32(AES_BASEADDR+BO_E_3_OFFSET);
xil_printf("Bo = %x %x %x %x\n\r",bo_3, bo_2, bo_1, bo_0);
*/
xil_printf("Done\n\r");
}
/******************************************************************************
* This function reads a number of bytes from an IIC chip into a
* specified buffer.
*
* @param ChipAddress contains the address of the IIC core.
* @param RegAddress contains the address of the register to write to.
* @param pBuffer contains the address of the data buffer to be filled.
* @param ByteCount contains the number of bytes in the buffer to be read.
* This value is constrained by the page size of the device such
* that up to 64K may be read in one call.
*
* @return The number of bytes read. A value less than the specified input
* value indicates an error.
*
* @note None.
*
******************************************************************************/
int zed_iic_axi_IicRead(zed_iic_t *pIIC, Xuint8 ChipAddress, Xuint8 RegAddress,
Xuint8 *pBuffer, Xuint8 ByteCount)
{
Xuint8 ReceivedByteCount = 0;
Xuint8 SentByteCount = 0;
Xuint8 ControlReg;
Xuint8 StatusReg;
int cnt = 0;
zed_iic_axi_t *pContext = (zed_iic_axi_t *)(pIIC->pContext);
#if 1
// Make sure all the Fifo's are cleared and Bus is Not busy.
do
{
StatusReg = Xil_In8(pContext->CoreAddress + XIIC_SR_REG_OFFSET);
//xil_printf("[%s] Xil_In8(pContext->CoreAddress + XIIC_SR_REG_OFFSET) => 0x%02X\n\r", pContext->szName, StatusReg );
StatusReg = StatusReg & (XIIC_SR_RX_FIFO_EMPTY_MASK |
XIIC_SR_TX_FIFO_EMPTY_MASK |
XIIC_SR_BUS_BUSY_MASK);
if ((StatusReg & XIIC_SR_RX_FIFO_EMPTY_MASK) != XIIC_SR_RX_FIFO_EMPTY_MASK)
{
/*
* The RX buffer is not empty and it is assumed there is a stale
* message in there. Attempt to clear out the RX buffer, otherwise
* this loop spins forever.
*/
XIic_ReadReg(pContext->CoreAddress, XIIC_DRR_REG_OFFSET);
}
/*
* Check to see if the bus is busy. Since we are master, if the bus is
* still busy that means that arbitration has been lost.
*
* According to Product Guide PG090, October 16, 2012:
*
* Control Register (0x100), Bit 2 MSMS:
*
* "Master/Slave Mode Select. When this bit is changed from 0 to 1,
* the AXI IIC bus interface generates a START condition in master
* mode. When this bit is cleared, a STOP condition is generated and
* the AXI IIC bus interface switches to slave mode. When this bit is
* cleared by the hardware, because arbitration for the bus has been
* lost, a STOP condition is not generated. (See also Interrupt(0):
* Arbitration Lost in Chapter 3.)"
*
* According to this, it should be okay to clear the master/slave mode
* select to clear a false start condition with a stop and regain
* arbitration over the bus.
*/
if ((StatusReg & XIIC_SR_BUS_BUSY_MASK) == XIIC_SR_BUS_BUSY_MASK)
{
ControlReg = Xil_In8(pContext->CoreAddress + XIIC_CR_REG_OFFSET);
ControlReg = ControlReg & 0xFB; // Clear the MSMS bit.
Xil_Out8(pContext->CoreAddress + XIIC_CR_REG_OFFSET, ControlReg);
}
} while (StatusReg != (XIIC_SR_RX_FIFO_EMPTY_MASK |
XIIC_SR_TX_FIFO_EMPTY_MASK));
#endif
// Position the Read pointer to specific location.
do
{
StatusReg = Xil_In8(pContext->CoreAddress + XIIC_SR_REG_OFFSET);
//xil_printf("[%s] Xil_In8(pContext->CoreAddress + XIIC_SR_REG_OFFSET) => 0x%02X\n\r", pContext->szName, StatusReg );
if(!(StatusReg & XIIC_SR_BUS_BUSY_MASK))
{
SentByteCount = XIic_DynSend(pContext->CoreAddress, ChipAddress,
(Xuint8 *)&RegAddress, 1,
XIIC_REPEATED_START);
}
cnt++;
}while(SentByteCount != 1 && (cnt < 100));
// Error writing chip address so return SentByteCount
if (SentByteCount < 1) { return SentByteCount; }
// Receive the data.
ReceivedByteCount = XIic_DynRecv(pContext->CoreAddress, ChipAddress, pBuffer,
ByteCount);
// Return the number of bytes received.
return ReceivedByteCount;
}
uint8_t axi_read8(uint32_t addr) {
return Xil_In8(offset + addr);
}
int main(void)
{
colorPoint tempRead;
int x;
//Initialize the color sensor
init_csens();
//initialize the hapt AND Calibrate the hapt
for (x=1; x<4; x++){
init_hapt(x);
autoCal_hapt(x);
}
u8 val, ampR, ampG, ampB;
int VIB, SLEEP;
while (1)
{
//with a switch we turn it on
val = Xil_In8 (base+leve);
if ((val==1) || (val==2) || (val==4) || (val==8))
{
xil_printf ("Il dispositivo è acceso\n");
tempRead = readRGB_csens();
xil_printf("Red value is %d. \n",tempRead.Red);
xil_printf("Green value is %d. \n",tempRead.Green);
xil_printf("Blue value is %d. \n",tempRead.Blue);
xil_printf("Clear value is %d.\n",tempRead.Clear);
ampR = 12 * tempRead.Red /25;
ampG = 12 * tempRead.Green /25;
ampB = 12 * tempRead.Blue /25;
if (tempRead.Clear > 100)
{
VIB= 500;
SLEEP=500;
}
else
{
VIB= 2000;
SLEEP= 2000;
}
{
write_hapt(MODE_Reg, 0x05, 1, 1);
write_hapt(MODE_Reg, 0x05, 1, 2);
write_hapt(MODE_Reg, 0x05, 1, 3);
write_hapt(RTP_INPUT_Reg, ampR, 1, 1);
write_hapt(RTP_INPUT_Reg, ampG, 1, 2);
write_hapt(RTP_INPUT_Reg, ampB, 1, 3);
MB_Sleep (VIB);
write_hapt(MODE_Reg,0x40,1, 1);
write_hapt(MODE_Reg,0x40,1, 2);
write_hapt(MODE_Reg,0x40,1, 3);
MB_Sleep (SLEEP);
write_hapt(GO_Reg, 0x00,1, 1);
write_hapt(GO_Reg, 0x00,1, 2);
write_hapt(GO_Reg, 0x00,1, 3);
}
}
}
return 0;
}
int main()
{
int i;
int prekidac;
init_platform();
XStatus Status;
//Set Terminal count for my_timer
//XIo_Out32(XPAR_MY_TIMER_0_BASEADDR + 0x0, 0x5F5E100);
// Run my_timer
XIo_Out32(XPAR_MY_TIMER_0_BASEADDR + 0x4, 0x2);
Status = XIntc_Initialize (&Intc, XPAR_INTC_0_DEVICE_ID);
if (Status != XST_SUCCESS)
xil_printf ("\r\nInterrupt controller initialization failure");
else
xil_printf("\r\nInterrupt controller initialized");
// Connect my_timer_interrupt_handler
Status = XIntc_Connect (&Intc, XPAR_INTC_0_DEVICE_ID,
(XInterruptHandler) my_timer_interrupt_handler,(void *)0);
if (Status != XST_SUCCESS)
xil_printf ("\r\nRegistering MY_TIMER Interrupt Failed");
else
xil_printf("\r\nMY_TIMER Interrupt registered");
//start the interrupt controller in real mode
Status = XIntc_Start(&Intc, XIN_REAL_MODE);
//enable interrupt controller
XIntc_Enable (&Intc, XPAR_INTC_0_DEVICE_ID);
microblaze_enable_interrupts();
unsigned char string_s[] = "LPRS 2 BRATE\n";
VGA_PERIPH_MEM_mWriteMemory(XPAR_VGA_PERIPH_MEM_0_S_AXI_MEM0_BASEADDR + 0x00, 0x0);// direct mode 0
VGA_PERIPH_MEM_mWriteMemory(XPAR_VGA_PERIPH_MEM_0_S_AXI_MEM0_BASEADDR + 0x04, 0x3);// display_mode 1
VGA_PERIPH_MEM_mWriteMemory(XPAR_VGA_PERIPH_MEM_0_S_AXI_MEM0_BASEADDR + 0x08, 0x1);// show frame 2
VGA_PERIPH_MEM_mWriteMemory(XPAR_VGA_PERIPH_MEM_0_S_AXI_MEM0_BASEADDR + 0x0C, 0x1);// font size 3
VGA_PERIPH_MEM_mWriteMemory(XPAR_VGA_PERIPH_MEM_0_S_AXI_MEM0_BASEADDR + 0x10, 0xFF0000);// foreground 4 crvena
VGA_PERIPH_MEM_mWriteMemory(XPAR_VGA_PERIPH_MEM_0_S_AXI_MEM0_BASEADDR + 0x14, 0x00FF00);// foreground 4 green
VGA_PERIPH_MEM_mWriteMemory(XPAR_VGA_PERIPH_MEM_0_S_AXI_MEM0_BASEADDR + 0x18, 0x0000FF);// foreground 4 plava
VGA_PERIPH_MEM_mWriteMemory(XPAR_VGA_PERIPH_MEM_0_S_AXI_MEM0_BASEADDR + 0x1c, 0xffff00);// foreground 4 zuta
VGA_PERIPH_MEM_mWriteMemory(XPAR_VGA_PERIPH_MEM_0_S_AXI_MEM0_BASEADDR + 0x20, 0x000000);// background color crna
VGA_PERIPH_MEM_mWriteMemory(XPAR_VGA_PERIPH_MEM_0_S_AXI_MEM0_BASEADDR + 0x24, 0xFF0000);// frame color 6
xil_printf("Hello World\n\r");
clear_text_screen(XPAR_VGA_PERIPH_MEM_0_S_AXI_MEM0_BASEADDR);
clear_graphics_screen(XPAR_VGA_PERIPH_MEM_0_S_AXI_MEM0_BASEADDR);
for(i=0;i<1200;i++){
set_cursor(i);
print_char(XPAR_VGA_PERIPH_MEM_0_S_AXI_MEM0_BASEADDR, 0, '2');
}
/*
set_cursor(0);
print_char(XPAR_VGA_PERIPH_MEM_0_S_AXI_MEM0_BASEADDR, 0, '2');
set_cursor(1);
print_char(XPAR_VGA_PERIPH_MEM_0_S_AXI_MEM0_BASEADDR, 1, 'G');
set_cursor(2);
print_char(XPAR_VGA_PERIPH_MEM_0_S_AXI_MEM0_BASEADDR, 2, 'B');
set_cursor(3);
print_char(XPAR_VGA_PERIPH_MEM_0_S_AXI_MEM0_BASEADDR, 3, 'Y');
set_cursor(6);
print_string(XPAR_VGA_PERIPH_MEM_0_S_AXI_MEM0_BASEADDR, 2, string_s, 12);
set_cursor(45);
unsigned char znak = '2';
if(znak >= 0x40){
znak -= 0x40;
}
VGA_PERIPH_MEM_mWriteMemory(XPAR_VGA_PERIPH_MEM_0_S_AXI_MEM0_BASEADDR + TEXT_MEM_OFF + 4*4, znak);
for(i=64;i<76;i++){
set_cursor(i);
print_char(XPAR_VGA_PERIPH_MEM_0_S_AXI_MEM0_BASEADDR, 2, string_s[i-64]);
}*/
while (1){
prekidac = Xil_In8(XPAR_MY_PERIPHERAL_0_BASEADDR);//iscitavanje prekidaca
//xil_printf("0x%08x\r\n", prekidac);
/*
value3 = XIo_In32(XPAR_MY_TIMER_0_BASEADDR + 0x0);
value1 = XIo_In32(XPAR_MY_TIMER_0_BASEADDR + 0x4);
value2 = XIo_In32(XPAR_MY_TIMER_0_BASEADDR + 0x8);
xil_printf("\n\rvalue1 = %x, value2 = %x, value3 = %x.", value1, value2, value3);
*/
}
cleanup_platform();
return 0;
}
static void sgi_handler(void *CallBackRef)
{
u32 INT;
INT = Xil_In32(0xF8F0010C);
cpu0 = Xil_In8(LED_PAT);
}
int getButtons(void) {
return Xil_In8(XPAR_PUSH_BUTTONS_5BITS_BASEADDR);
}
int main(void)
{
while (1)
{
unsigned char c, d, e;
c = 0x00;
d = 0x00;
e = 0x00;
while(c == 0x00){
c = XUartLite_RecvByte(0x84000000); //receive letter
}
XUartLite_SendByte(0x84000000, c);
while(d == 0x00){
d = XUartLite_RecvByte(0x84000000); //receive letter
}
XUartLite_SendByte(0x84000000, d);
while(e == 0x00){
e = XUartLite_RecvByte(0x84000000); //receive letter
}
XUartLite_SendByte(0x84000000, e);
XUartLite_SendByte(0x84000000, 0x20); //send space char
//led command
if((c == 0x6C) && (d == 0x65) && (e == 0x64)){
c = 0x00;
d = 0x00;
e = 0x00;
while(c == 0x00){
c = XUartLite_RecvByte(0x84000000) - 0x30; //receive letter
d = c - 0x27;
if((c >= 0x0) && (c <= 0x9)){
e = c;
}
else if((d >= 0xA) && (d <= 0xF)){
e = d;
}
else{
e = 0x0;
}
}
XUartLite_SendByte(0x84000000, c + 0x30);
e = e << 4;
c = 0x00;
d = 0x00;
while(c == 0x00){
c = XUartLite_RecvByte(0x84000000) - 0x30; //receive letter
d = c - 0x27;
if((c >= 0x0) && (c <= 0x9)){
e += c;
}
else if((d >= 0xA) && (d <= 0xF)){
e += d;
}
else{
e = e;
}
}
XUartLite_SendByte(0x84000000, c + 0x30);
Xil_Out8(0x83000000, e);
}
//switch command
if((c == 0x73) && (d == 0x77) && (e == 0x74)){
c = 0x00;
d = 0x00;
e = 0x00;
c = Xil_In8(0x83000004) & 0xF;
d = Xil_In8(0x83000004) & 0xF0;
d = d >> 4;
if(c <= 0x9){
c = c + 0x30;
}
else{
c = c + 0x57;
}
if(d <= 0x9){
d = d + 0x30;
}
else{
d = d + 0x57;
}
XUartLite_SendByte(0x84000000, d);
XUartLite_SendByte(0x84000000, c);
}
XUartLite_SendByte(0x84000000, 0xA); //send new line char
XUartLite_SendByte(0x84000000, 0xD); //send return char
}