static int ath79_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
u32 mask = 0, t;
int clk_cfg_idx = 0;
int clk_cfg_array_size =sizeof(clk_cfg)/(sizeof(*clk_cfg));
printk("%s\n", __FUNCTION__);
/* find right frequency setting: */
for(clk_cfg_idx=0;clk_cfg_idx<clk_cfg_array_size;clk_cfg_idx++)
{
if(params_rate(params) == clk_cfg[clk_cfg_idx].freq)
{
printk(KERN_NOTICE "Set clk config: %x-%x-%x for freq: %d\n", clk_cfg[clk_cfg_idx].divint,
clk_cfg[clk_cfg_idx].divfrac,
clk_cfg[clk_cfg_idx].posedgde,
clk_cfg[clk_cfg_idx].freq);
break;
}
}
if(clk_cfg_idx == clk_cfg_array_size)
{
printk(KERN_ERR "No valid clock config found for frequency %d\n", params_rate(params));
return -ENOTSUPP;
}
//ar7240_reg_wr(AR7240_STEREO_CLK_DIV, ((clk_cfg[clk_cfg_idx].divint << 16) + clk_cfg[clk_cfg_idx].divfrac));
ath79_stereo_wr(AR934X_STEREO_CONFIG_CLK_DIV, ((clk_cfg[clk_cfg_idx].divint << 16) + clk_cfg[clk_cfg_idx].divfrac));
switch(params_format(params))
{
case SNDRV_PCM_FORMAT_S8:
mask |= AR934X_STEREO_CONFIG_DATA_WORD_8 << AR934X_STEREO_CONFIG_DATA_WORD_SIZE_SHIFT;
break;
case SNDRV_PCM_FORMAT_S16_LE:
mask |= AR934X_STEREO_CONFIG_PCM_SWAP;
case SNDRV_PCM_FORMAT_S16_BE:
mask |= AR934X_STEREO_CONFIG_DATA_WORD_16 << AR934X_STEREO_CONFIG_DATA_WORD_SIZE_SHIFT;
break;
default:
printk(KERN_ERR "%s: Format %d not supported\n",__FUNCTION__, params_format(params));
return -ENOTSUPP;
}
spin_lock(&ath79_stereo_lock);
t = ath79_stereo_rr(AR934X_STEREO_REG_CONFIG);
t &= ~(AR934X_STEREO_CONFIG_DATA_WORD_SIZE_MASK
<< AR934X_STEREO_CONFIG_DATA_WORD_SIZE_SHIFT);
t &= ~(AR934X_STEREO_CONFIG_I2S_WORD_SIZE);
t |= mask;
t |= AR934X_STEREO_CONFIG_PSEDGE(2);
ath79_stereo_wr(AR934X_STEREO_REG_CONFIG, t);
spin_unlock(&ath79_stereo_lock);
ath79_stereo_reset();
return 0;
}
static void ath79_i2s_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
if (!dai->active) {
ath79_stereo_wr(AR934X_STEREO_REG_CONFIG, 0);
}
return;
}
void ath79_stereo_reset(void)
{
u32 t;
spin_lock(&ath79_stereo_lock);
t = ath79_stereo_rr(AR934X_STEREO_REG_CONFIG);
t |= AR934X_STEREO_CONFIG_RESET;
ath79_stereo_wr(AR934X_STEREO_REG_CONFIG, t);
spin_unlock(&ath79_stereo_lock);
}
void ath79_stereo_reset(void)
{
u32 t;
printk("%s\n", __FUNCTION__);
spin_lock(&ath79_stereo_lock);
t = ath79_stereo_rr(AR934X_STEREO_REG_CONFIG);
t |= AR934X_STEREO_CONFIG_RESET;
ath79_stereo_wr(AR934X_STEREO_REG_CONFIG, t);
spin_unlock(&ath79_stereo_lock);
}
static int ath79_i2s_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
u32 mask = 0, t;
ath79_audio_set_freq(params_rate(params));
switch(params_format(params)) {
case SNDRV_PCM_FORMAT_S8:
mask |= AR934X_STEREO_CONFIG_DATA_WORD_8
<< AR934X_STEREO_CONFIG_DATA_WORD_SIZE_SHIFT;
break;
case SNDRV_PCM_FORMAT_S16_LE:
mask |= AR934X_STEREO_CONFIG_PCM_SWAP;
case SNDRV_PCM_FORMAT_S16_BE:
mask |= AR934X_STEREO_CONFIG_DATA_WORD_16
<< AR934X_STEREO_CONFIG_DATA_WORD_SIZE_SHIFT;
break;
case SNDRV_PCM_FORMAT_S24_LE:
mask |= AR934X_STEREO_CONFIG_PCM_SWAP;
case SNDRV_PCM_FORMAT_S24_BE:
mask |= AR934X_STEREO_CONFIG_DATA_WORD_24
<< AR934X_STEREO_CONFIG_DATA_WORD_SIZE_SHIFT;
mask |= AR934X_STEREO_CONFIG_I2S_WORD_SIZE;
break;
case SNDRV_PCM_FORMAT_S32_LE:
mask |= AR934X_STEREO_CONFIG_PCM_SWAP;
case SNDRV_PCM_FORMAT_S32_BE:
mask |= AR934X_STEREO_CONFIG_DATA_WORD_32
<< AR934X_STEREO_CONFIG_DATA_WORD_SIZE_SHIFT;
mask |= AR934X_STEREO_CONFIG_I2S_WORD_SIZE;
break;
default:
printk(KERN_ERR "%s: Format %d not supported\n",
__FUNCTION__, params_format(params));
return -ENOTSUPP;
}
spin_lock(&ath79_stereo_lock);
t = ath79_stereo_rr(AR934X_STEREO_REG_CONFIG);
t &= ~(AR934X_STEREO_CONFIG_DATA_WORD_SIZE_MASK
<< AR934X_STEREO_CONFIG_DATA_WORD_SIZE_SHIFT);
t &= ~(AR934X_STEREO_CONFIG_I2S_WORD_SIZE);
t |= mask;
ath79_stereo_wr(AR934X_STEREO_REG_CONFIG, t);
spin_unlock(&ath79_stereo_lock);
ath79_stereo_reset();
return 0;
}
static int ath79_i2s_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
/* Enable I2S and SPDIF by default */
if (!dai->active) {
ath79_stereo_wr(AR934X_STEREO_REG_CONFIG,
AR934X_STEREO_CONFIG_SPDIF_ENABLE |
AR934X_STEREO_CONFIG_I2S_ENABLE |
AR934X_STEREO_CONFIG_SAMPLE_CNT_CLEAR_TYPE |
AR934X_STEREO_CONFIG_MASTER);
ath79_stereo_reset();
}
return 0;
}
