void
ath_rate_setupxtxdesc(struct ath_softc *sc, struct ath_node *an,
struct ath_desc *ds, int shortPreamble, u_int8_t rix)
{
struct sample_node *sn = ATH_NODE_SAMPLE(an);
int rateCode = -1;
int frame_size = 0;
int size_bin = 0;
int ndx = 0;
size_bin = size_to_bin(frame_size); // TODO: it's correct that frame_size alway 0 ?
ndx = sn->current_rate[size_bin]; /* retry at the current bit-rate */
if (!sn->stats[size_bin][ndx].packets_acked) {
ndx = 0; /* use the lowest bit-rate */
}
if (shortPreamble) {
rateCode = sn->rates[ndx].shortPreambleRateCode;
} else {
rateCode = sn->rates[ndx].rateCode;
}
ath_hal_setupxtxdesc(sc->sc_ah, ds
, rateCode, 3 /* series 1 */
, sn->rates[0].rateCode, 3 /* series 2 */
, 0, 0 /* series 3 */
);
}
void
ath_rate_setupxtxdesc(struct ath_softc *sc, struct ath_node *an,
struct ath_desc *ds, int shortPreamble, u_int8_t rix)
{
struct amrr_node *amn = ATH_NODE_AMRR(an);
ath_hal_setupxtxdesc(sc->sc_ah, ds
, amn->amn_tx_rate1sp, amn->amn_tx_try1 /* series 1 */
, amn->amn_tx_rate2sp, amn->amn_tx_try2 /* series 2 */
, amn->amn_tx_rate3sp, amn->amn_tx_try3 /* series 3 */
);
}
void
ath_rate_setupxtxdesc(struct ath_softc *sc, struct ath_node *an,
struct ath_desc *ds, int shortPreamble, u_int8_t rix)
{
struct onoe_node *on = ATH_NODE_ONOE(an);
ath_hal_setupxtxdesc(sc->sc_ah, ds
, on->on_tx_rate1sp, 2 /* series 1 */
, on->on_tx_rate2sp, 2 /* series 2 */
, on->on_tx_rate3sp, 2 /* series 3 */
);
}
void
ath_rate_setupxtxdesc(struct ath_softc *sc, struct ath_node *an,
struct ath_desc *ds, int shortPreamble, u_int8_t rix)
{
struct sample_node *sn = ATH_NODE_SAMPLE(an);
const struct txschedule *sched = &sn->sched[rix];
const HAL_RATE_TABLE *rt = sc->sc_currates;
uint8_t rix1, s1code, rix2, s2code, rix3, s3code;
/* XXX precalculate short preamble tables */
rix1 = sched->r1;
s1code = rt->info[rix1].rateCode
| (shortPreamble ? rt->info[rix1].shortPreamble : 0);
rix2 = sched->r2;
s2code = rt->info[rix2].rateCode
| (shortPreamble ? rt->info[rix2].shortPreamble : 0);
rix3 = sched->r3;
s3code = rt->info[rix3].rateCode
| (shortPreamble ? rt->info[rix3].shortPreamble : 0);
ath_hal_setupxtxdesc(sc->sc_ah, ds,
s1code, sched->t1, /* series 1 */
s2code, sched->t2, /* series 2 */
s3code, sched->t3); /* series 3 */
}
void ath_cont_data(struct ath_softc *sc ,int val,ath_callback ath_draintxq, ath_callback ath_stoprecv)
{
static struct sk_buff *skb = NULL;
struct ieee80211_frame *hdr;
static struct ieee80211com *ic;
static struct ath_buf *bf,*prev,*first;
static struct ath_desc *ds;
static struct ath_hal *ah;
static STAILQ_HEAD(tpc_buf,ath_buf) tmp_q;
static int is_inited=0;
struct ath_txq *txq;
const HAL_RATE_TABLE *rt;
u_int8_t *p;
u_int32_t flags, txrate, r,i;
u_int16_t hdrlen, framelen, dmalen,delay=0;
#define MIN(a,b) ((a) < (b) ? (a) : (b))
if(ath_hal_getdiagstate(sc->sc_ah, 19,0,10,NULL,NULL) == AH_FALSE)
{
printk("HAL does not support TX99 mode \n");
printk("compile HAL with AH_PRIVATE_DIAG turned on \n");
return;
}
if(is_inited == 0)
{
STAILQ_INIT(&tmp_q);
is_inited=1;
}
/* enter CONT_DATA mode */
if (val && skb==NULL) {
skb = ath_alloc_skb(4096, 32);
if (skb == NULL)
goto out;
/* build output packet */
hdr = (struct ieee80211_frame *)skb_put(skb, sizeof(*hdr));
IEEE80211_ADDR_COPY(&hdr->i_addr1, test_addr);
IEEE80211_ADDR_COPY(&hdr->i_addr2, test_addr);
IEEE80211_ADDR_COPY(&hdr->i_addr3, test_addr);
hdr->i_dur[0] = 0x0;
hdr->i_dur[1] = 0x0;
hdr->i_seq[0] = 0x5a;
hdr->i_seq[1] = 0x5a;
hdr->i_fc[0] = IEEE80211_FC0_TYPE_DATA;
hdr->i_fc[1] = 0;
hdrlen = sizeof(*hdr);
for(r=0; r<2000; ) {
p = skb_put(skb, sizeof(PN9Data));
memcpy(p, PN9Data, sizeof(PN9Data));
r += sizeof(PN9Data);
}
framelen = hdrlen + r + IEEE80211_CRC_LEN;
ic = &sc->sc_ic;
ah = sc->sc_ah;
rt = sc->sc_currates;
if (rt==NULL) {
printk("no rate table\n");
goto out;
}
txrate = rt->info[rt->rateCount-1].rateCode; /* send at highest rate */
{
int rix;
if (sc->sc_txrx99.txrate==0)
sc->sc_txrx99.txrate = 6000;
for(rix=0; rix<rt->rateCount; rix++) {
if (rt->info[rix].rateKbps==sc->sc_txrx99.txrate) {
txrate = rt->info[rix].rateCode;
printk("txrate set to %dKbps\n", sc->sc_txrx99.txrate);
break;
}
}
}
ath_draintxq(sc);
prev=first=NULL;
printk("txpower set to %d\n", sc->sc_txrx99.txpower);
/* send 20 frames for the Power Amp to settle down */
for(i=0;i<20;++i)
{
ATH_TXBUF_LOCK_BH(sc);
bf = STAILQ_FIRST(&sc->sc_txbuf);
if (bf != NULL) {
STAILQ_REMOVE_HEAD(&sc->sc_txbuf,bf_list);
}
ATH_TXBUF_UNLOCK_BH(sc);
if (bf==NULL) {
printk("no tx buf\n");
goto out;
}
if(!i) first=bf;
framelen = skb->len + IEEE80211_CRC_LEN;
dmalen = skb->len;
txq = sc->sc_ac2q[WME_AC_VO];
bf->bf_skbaddr = bus_map_single(sc->sc_bdev, skb->data, framelen, BUS_DMA_TODEVICE);
bf->bf_skb = skb;
bf->bf_node = 0;
flags = HAL_TXDESC_CLRDMASK;
ds = bf->bf_desc;
if(prev)
prev->bf_desc->ds_link = bf->bf_daddr; /* link from prev desc */
ds->ds_data = bf->bf_skbaddr;
r = ath_hal_setuptxdesc(ah, ds, framelen, hdrlen,
HAL_PKT_TYPE_NORMAL,
sc->sc_txrx99.txpower,
txrate, /* tx rate */
1, /* max retries */
HAL_TXKEYIX_INVALID, /* no WEP */
1, /* select Omni Antenna 0 */
flags,
0, /* rts/cts rate */
0 /* rts/cts duration */
);
if (r==AH_FALSE) {
printk("fail setuptxdesc r(%d)\n", r);
goto out;
}
r = ath_hal_filltxdesc(ah, ds, skb->len, AH_TRUE, AH_TRUE,ds);
if (r==AH_FALSE) {
printk("fail fill tx desc r(%d)\n", r);
goto out;
}
ath_hal_setupxtxdesc(ah, ds
, txrate, 15 /* series 1 */
, txrate, 15 /* series 2 */
, txrate, 15 /* series 3 */
);
/* insert the buffers in to tmp_q */
STAILQ_INSERT_HEAD(&tmp_q,bf,bf_list);
prev=bf;
}
ath_hal_intrset(ah, 0); /* disable interrupts */
//sc->sc_imask = HAL_INT_RX | HAL_INT_TX
// | HAL_INT_RXEOL | HAL_INT_RXORN
// | HAL_INT_FATAL | HAL_INT_GLOBAL;
sc->sc_imask = 0;
//ath_hal_intrset(ah, sc->sc_imask);
bf->bf_desc->ds_link = 0;
r = ath_hal_puttxbuf(ah, txq->axq_qnum, first->bf_daddr);
ath_hal_txstart(ah, txq->axq_qnum);
while(ath_hal_txprocdesc(ah,bf->bf_desc) == HAL_EINPROGRESS)
{
udelay(2000);
++delay;
}
/* sleep for 20ms */
udelay(20000);
printk("took %d msec to transmit the 20 frames \n",2*delay);
/* start TX99 mode */
ath_stoprecv(sc); /* stop recv side */
bf->bf_desc->ds_link = first->bf_daddr; /* link to self */
ath_hal_getdiagstate(ah, 19,(void *) sc->sc_txrx99.prefetch,9,NULL,NULL);
ath_hal_getdiagstate(ah, 19, (void *)txq->axq_qnum, val,NULL,NULL);
r = ath_hal_puttxbuf(ah, txq->axq_qnum, first->bf_daddr);
ath_hal_txstart(ah, txq->axq_qnum);
}
/* leave CONT_DATA mode, reset the chip */
if (val==0 && skb) {
int j=0;
ath_hal_getdiagstate(ah, 19, 0, 0,NULL,NULL);
/* insert the buffers back into txbuf list */
ATH_TXBUF_LOCK_BH(sc);
bf = STAILQ_FIRST(&tmp_q);
while(bf)
{
bf->bf_skb=NULL;
STAILQ_REMOVE_HEAD(&tmp_q,bf_list);
STAILQ_INSERT_HEAD(&sc->sc_txbuf,bf,bf_list);
bf = STAILQ_FIRST(&tmp_q);
++j;
}
ATH_TXBUF_UNLOCK_BH(sc);
printk("inserted back %d buffers \n",j);
ic->ic_reset(ic->ic_dev);
skb = NULL;
bf = NULL;
}
if (val==7 && skb) {
ath_hal_getdiagstate(ah, 19, ds, 7,NULL,NULL);
}
sc->sc_txrx99.tx99mode=val;
out:
return;
#undef MIN
}