void ax88796Init(void)
{
unsigned char delaycount=10;
unsigned char tcrFduFlag;
ax88796SetupPorts();
// do a hard reset
AX88796_RESET_PORT |= _BV(AX88796_RESET_PIN);
delay_ms(10);
AX88796_RESET_PORT &= ~_BV(AX88796_RESET_PIN);
// do soft reset
ax88796Write(ISR, ax88796Read(ISR));
delay_ms(50);
// wait for PHY to come out of reset
ax88796Read(RSTPORT);
while(ax88796Read(TR) & RST_B);
ax88796WriteMii(0x10,0x00,0x0800);
while(delaycount--)
delay_ms(255);
ax88796WriteMii(0x10,0x00,0x1200);
ax88796Write(CR,(RD2|STOP)); // stop the NIC, abort DMA, page 0
delay_ms(5); // make sure nothing is coming in or going out
ax88796Write(DCR,DCR_INIT);
ax88796Write(RBCR0,0x00);
ax88796Write(RBCR1,0x00);
ax88796Write(IMR,0x00);
ax88796Write(ISR,0xFF);
ax88796Write(RCR,0x20);
ax88796Write(BNRY,RXSTART_INIT);
ax88796Write(PSTART,RXSTART_INIT);
ax88796Write(PSTOP,RXSTOP_INIT);
// switch to page 1
ax88796Write(CR,(PS0|RD2|STOP));
// write mac address
ax88796Write(PAR0+0, MYMAC_0);
ax88796Write(PAR0+1, MYMAC_1);
ax88796Write(PAR0+2, MYMAC_2);
ax88796Write(PAR0+3, MYMAC_3);
ax88796Write(PAR0+4, MYMAC_4);
ax88796Write(PAR0+5, MYMAC_5);
// set start point
ax88796Write(CURR,RXSTART_INIT+1);
ax88796Write(CR,(RD2|START));
ax88796Write(RCR,RCR_INIT);
if(ax88796Read(GPI) & I_SPD) // check PHY speed setting
tcrFduFlag = FDU; // if 100base, do full duplex
else
tcrFduFlag = 0; // if 10base, do half duplex
ax88796Write(TCR,(tcrFduFlag|TCR_INIT));
ax88796Write(GPOC,MPSEL); // select media interface
ax88796Write(TPSR,TXSTART_INIT);
ax88796Write(CR,(RD2|STOP));
ax88796Write(DCR,DCR_INIT);
ax88796Write(CR,(RD2|START));
ax88796Write(ISR,0xFF);
ax88796Write(IMR,IMR_INIT);
ax88796Write(TCR,(tcrFduFlag|TCR_INIT));
}
void ax88796Init(void)
{
unsigned char tcrFduFlag;
// initialize I/O ports
ax88796SetupPorts();
// do a hard reset
sbi(AX88796_RESET_PORT, AX88796_RESET_PIN);
delay_ms(100);
cbi(AX88796_RESET_PORT, AX88796_RESET_PIN);
// do soft reset
ax88796Write(ISR, ax88796Read(ISR));
delay_ms(50);
// wait for PHY to come out of reset
ax88796Read(RSTPORT);
while(ax88796Read(TR) & RST_B);
ax88796WriteMii(0x10,0x00,0x0800);
delay_ms(255);
ax88796WriteMii(0x10,0x00,0x1200);
ax88796Write(CR,(RD2|STOP)); // stop the NIC, abort DMA, page 0
delay_ms(5); // make sure nothing is coming in or going out
ax88796Write(DCR,DCR_INIT);
ax88796Write(RBCR0,0x00);
ax88796Write(RBCR1,0x00);
ax88796Write(IMR,0x00);
ax88796Write(ISR,0xFF);
ax88796Write(RCR,0x20);
ax88796Write(BNRY,RXSTART_INIT);
ax88796Write(PSTART,RXSTART_INIT);
ax88796Write(PSTOP,RXSTOP_INIT);
// switch to page 1
ax88796Write(CR,(PS0|RD2|STOP));
// write mac address
ax88796Write(PAR0+0, AX88796_MAC0);
ax88796Write(PAR0+1, AX88796_MAC1);
ax88796Write(PAR0+2, AX88796_MAC2);
ax88796Write(PAR0+3, AX88796_MAC3);
ax88796Write(PAR0+4, AX88796_MAC4);
ax88796Write(PAR0+5, AX88796_MAC5);
// set start point
ax88796Write(CURR,RXSTART_INIT+1);
ax88796Write(CR,(RD2|START));
ax88796Write(RCR,RCR_INIT);
if(ax88796Read(GPI) & I_SPD) // check PHY speed setting
tcrFduFlag = FDU; // if 100base, do full duplex
else
tcrFduFlag = 0; // if 10base, do half duplex
ax88796Write(TCR,(tcrFduFlag|TCR_INIT));
ax88796Write(GPOC,MPSEL); // select media interface
ax88796Write(TPSR,TXSTART_INIT);
ax88796Write(CR,(RD2|STOP));
ax88796Write(DCR,DCR_INIT);
ax88796Write(CR,(RD2|START));
ax88796Write(ISR,0xFF);
ax88796Write(IMR,IMR_INIT);
ax88796Write(TCR,(tcrFduFlag|TCR_INIT));
//test
/*
while(1)
{
vt100SetCursorPos(18,0);
ax88796RegDump();
}
*/
}
