void gottlieb_sh_w(int offset,int data) { data &= 0xff; if (data != 0xff) { if (Machine->gamedrv->samplenames) { /* if we have loaded samples, we must be Q*Bert */ switch(data ^ 0xff) { case 0x12: /* play a sample here (until Votrax speech is emulated) */ sample_start (0, 0, 0); break; case 0x14: /* play a sample here (until Votrax speech is emulated) */ sample_start (0, 1, 0); break; case 0x16: /* play a sample here (until Votrax speech is emulated) */ sample_start (0, 2, 0); break; case 0x11: /* play a sample here (until Votrax speech is emulated) */ sample_start (0, 3, 0); break; } } soundlatch_w(offset,data); switch (cpu_gettotalcpu()) { case 2: /* Revision 1 sound board */ cpu_cause_interrupt(1,M6502_INT_IRQ); break; case 3: case 4: /* Revision 2 & 3 sound board */ cpu_cause_interrupt(cpu_gettotalcpu()-1,M6502_INT_IRQ); cpu_cause_interrupt(cpu_gettotalcpu()-2,M6502_INT_IRQ); break; } } }
static WRITE_HANDLER( pandoras_int_control_w ){ /* byte 0: irq enable (CPU A) byte 2: coin counter 1 byte 3: coin counter 2 byte 5: flip screen byte 6: irq enable (CPU B) byte 7: NMI to CPU B other bytes unknown */ switch (offset){ case 0x00: if (!data) cpu_set_irq_line(0, M6809_IRQ_LINE, CLEAR_LINE); irq_enable_a = data; break; case 0x02: coin_counter_w(0,data & 0x01); break; case 0x03: coin_counter_w(1,data & 0x01); break; case 0x05: pandoras_flipscreen_w(0, data); break; case 0x06: if (!data) cpu_set_irq_line(1, M6809_IRQ_LINE, CLEAR_LINE); irq_enable_b = data; break; case 0x07: cpu_cause_interrupt(1,M6809_INT_NMI); break; default: //logerror("%04x: (irq_ctrl) write %02x to %02x\n",cpu_get_pc(), data, offset); break; } }
void starwars_main_wr_w(int offset, int data) { port_A |= 0x80; /* command from main cpu pending */ sound_data = data; if (PA7_irq) cpu_cause_interrupt (1, M6809_INT_IRQ); }
static WRITE_HANDLER( ddragon3_io_w ){ reg[offset/2] = COMBINE_WORD(reg[offset],data); switch (offset) { case 0x0: ddragon3_vreg = reg[0]; break; case 0x2: /* soundlatch_w */ soundlatch_w(1,reg[1]&0xff); cpu_cause_interrupt( 1, Z80_NMI_INT ); break; case 0x4: /* this gets written to on startup and at the end of IRQ6 ** possibly trigger IRQ on sound CPU */ break; case 0x6: /* this gets written to on startup, ** and at the end of IRQ5 (input port read) */ break; case 0x8: /* this gets written to at the end of IRQ6 only */ break; default: //logerror("OUTPUT 1400[%02x] %08x, pc=%06x \n", offset,(unsigned)data, cpu_get_pc() ); break; } }
static WRITE_HANDLER( battlera_sound_w ) { if (offset==0) { soundlatch_w(0,data); cpu_cause_interrupt(1,H6280_INT_IRQ1); } }
static WRITE_HANDLER( sound_command_w ) { d400 = data; soundlatch_w(0,data); cpu_cause_interrupt(1,Z80_NMI_INT); logerror("sound command %02x\n",data); }
static WRITE16_HANDLER( heberpop_sound_command_w ) { if (ACCESSING_LSB) { soundlatch_w(0,data & 0xff); cpu_cause_interrupt(1,0xff); /* RST 38h */ } }
void firetrap_adpcm_int (int data) { static int toggle; toggle = 1 - toggle; if (firetrap_irq_enable && toggle) cpu_cause_interrupt (1, M6502_INT_IRQ); }
static void atarisys2_soundint (void) { if (!irq_hold0 && (READ_WORD (&atarisys2_interrupt_enable[0]) & 1)) { cpu_cause_interrupt (0, 0); irq_hold0 = 1; } }
void blstroid_int1_callback (int param) { /* generate the interrupt */ cpu_cause_interrupt (0, 1); /* set ourselves up to go off next frame */ int1_timer[param] = timer_set (TIME_IN_HZ (Machine->drv->frames_per_second), param, blstroid_int1_callback); }
static WRITE_HANDLER( splash_sh_irqtrigger_w ) { if ((data & 0x00ff0000) == 0) { soundlatch_w(0,data & 0xff); cpu_cause_interrupt(1,Z80_IRQ_INT); } }
static WRITE_HANDLER( jumping_sound_w ) { if (offset == 0) { jumping_latch = data & 0xff; /*M68000 writes .b to $400007*/ /*logerror("jumping M68k write latch=%02x\n",jumping_latch);*/ cpu_cause_interrupt(1,Z80_IRQ_INT); } }
static void CPUB_int_enable( int offset, int data ){ if( CPUB_latch & SNK_NMI_PENDING ){ cpu_cause_interrupt( 1, Z80_NMI_INT ); CPUB_latch = 0; } else { CPUB_latch |= SNK_NMI_ENABLE; } }
static WRITE_HANDLER( meteor_soundtrigger_w ) { if ((meteor_soundtrigger & 0x08) && (~data & 0x08)) { cpu_cause_interrupt(1, I8039_EXT_INT); } meteor_soundtrigger = data; }
static WRITE_HANDLER( sound_command_w ){ /*if( sound_fetched==0 ){ logerror("missed sound command: %02x\n", sound_command ); }*/ sound_fetched = 0; sound_command = data; sound_cpu_ready = 0; cpu_cause_interrupt( 2, Z80_IRQ_INT ); }
static void sound_command_w( int offset, int data ){ if( sound_fetched==0 ){ if( errorlog ) fprintf( errorlog, "missed sound command: %02x\n", sound_command ); } sound_fetched = 0; sound_command = data; sound_cpu_ready = 0; cpu_cause_interrupt( 2, Z80_IRQ_INT ); }
static int CPUB_int_trigger( int offset ){ if( CPUB_latch&SNK_NMI_ENABLE ){ cpu_cause_interrupt( 1, Z80_NMI_INT ); CPUB_latch = 0; } else { CPUB_latch |= SNK_NMI_PENDING; } return 0xff; }
void pacland_timer_proc( int param ) { pacland_timer = 0; /* update current time with compare time */ hd_regs[0x09] = hd_regs[0x0b]; hd_regs[0x0a] = hd_regs[0x0c]; if ( hd_regs[0x08] & 8 ) cpu_cause_interrupt( 1, M6808_INT_OCI ); }
void toki_adpcm_int (int data) { static int toggle=0; MSM5205_data_w (0,msm5205next); msm5205next>>=4; toggle ^= 1; if (toggle) cpu_cause_interrupt(1,Z80_NMI_INT); }
static void battlera_adpcm_int(int data) { static int toggle; MSM5205_data_w(0,msm5205next >> 4); msm5205next<<=4; toggle = 1 - toggle; if (toggle) cpu_cause_interrupt(1,H6280_INT_IRQ2); }
int docastle_shared0_r(int offset) { /* this shouldn't be done, however it's the only way I've found */ /* to make dip switches work in Do Run Run. */ if (offset == 8) { cpu_cause_interrupt(1,Z80_NMI_INT); cpu_spinuntil_trigger(500); } return buffer0[offset]; }
static void TMS34061_intcallback(int param) { timer_reset(timer, cpu_getscanlinetime(regs[REG_VERINT])); if (!(regs[REG_CONTROL1] & 0x400)) return; regs[REG_STATUS] |= 0x0001; cpu_cause_interrupt (param, intf->vertical_interrupt()); }
static WRITE_HANDLER( bking2_soundlatch_w ) { int i,code; code = 0; for (i = 0;i < 8;i++) if (data & (1 << i)) code |= 0x80 >> i; soundlatch_w(offset,code); if (sndnmi_enable) cpu_cause_interrupt(1,Z80_NMI_INT); }
static WRITE_HANDLER( CPUB_int_enable_w ) { if( CPUB_latch & SNK_NMI_PENDING ) { cpu_cause_interrupt( 1, Z80_NMI_INT ); CPUB_latch = 0; } else { CPUB_latch |= SNK_NMI_ENABLE; } }
void frogger2_sh_irqtrigger_w(int offset,int data) { static int last; if (last == 0 && (data & 0x01) != 0) { /* setting bit 0 low then high triggers IRQ on the sound CPU */ cpu_cause_interrupt(1,0xff); } last = data & 0x01; }
void mikie_sh_irqtrigger_w(int offset,int data) { static int last; if (last == 0 && data == 1) { /* setting bit 0 low then high triggers IRQ on the sound CPU */ cpu_cause_interrupt(1,0xff); } last = data; }
static READ_HANDLER( CPUB_int_trigger_r ) { if( CPUB_latch&SNK_NMI_ENABLE ) { cpu_cause_interrupt( 1, Z80_NMI_INT ); CPUB_latch = 0; } else { CPUB_latch |= SNK_NMI_PENDING; } return 0xff; }
void atarisys2_32v_interrupt (int param) { /* generate the 32V interrupt (IRQ 2) */ if (!irq_hold2 && (READ_WORD (&atarisys2_interrupt_enable[0]) & 4)) { cpu_cause_interrupt (0, 2); irq_hold2 = 1; } /* set the timer for the next one */ param += 64; if (param < 384) timer_set (64.0 * cpu_getscanlineperiod (), param, atarisys2_32v_interrupt); }
static WRITE_HANDLER( stadhero_control_w ) { switch (offset) { case 4: /* Interrupt ack (VBL - IRQ 5) */ break; case 6: /* 6502 sound cpu */ soundlatch_w(0,data & 0xff); cpu_cause_interrupt(1,M6502_INT_NMI); break; default: //logerror("CPU #0 PC %06x: warning - write %02x to unmapped memory address %06x\n",cpu_get_pc(),data,0x30c010+offset); break; } }
static void kangaroo_init_machine(void) { /* I think there is a bug in the startup checks of the game. At the very */ /* beginning, during the RAM check, it goes one byte too far, and ends up */ /* trying to write, and re-read, location dfff. To the best of my knowledge, */ /* that is a ROM address, so the test fails and the code keeps jumping back */ /* at 0000. */ /* However, a NMI causes a successful reset. Maybe the hardware generates a */ /* NMI short after power on, therefore masking the bug? The NMI is generated */ /* by the MB8841 custom microcontroller, so this could be a way to disguise */ /* the copy protection. */ /* Anyway, what I do here is just immediately generate the NMI, so the game */ /* properly starts. */ cpu_cause_interrupt(0,Z80_NMI_INT); }