/* * Return the number of cores on this SOC. */ int cpu_numcores(void) { int numcores; u32 mask; mask = cpu_mask(); numcores = hweight32(cpu_mask()); /* Verify if M4 is deactivated */ if (mask & 0x1) numcores--; return numcores; }
int core_to_pos(int nr) { u32 cores = cpu_mask(); int i, count = 0; if (nr == 0) { return 0; } else if (nr >= hweight32(cores)) { puts("Not a valid core number.\n"); return -1; } for (i = 1; i < 32; i++) { if (is_core_valid(i)) { count++; if (count == nr) break; } } return count; }
int fsl_layerscape_wake_seconday_cores(void) { struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); #ifdef CONFIG_FSL_LSCH3 struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR); #elif defined(CONFIG_FSL_LSCH2) struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR); #endif u32 cores, cpu_up_mask = 1; int i, timeout = 10; u64 *table = get_spin_tbl_addr(); #ifdef COUNTER_FREQUENCY_REAL /* update for secondary cores */ __real_cntfrq = COUNTER_FREQUENCY_REAL; flush_dcache_range((unsigned long)&__real_cntfrq, (unsigned long)&__real_cntfrq + 8); #endif cores = cpu_mask(); /* Clear spin table so that secondary processors * observe the correct value after waking up from wfe. */ memset(table, 0, CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE); flush_dcache_range((unsigned long)table, (unsigned long)table + (CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE)); printf("Waking secondary cores to start from %lx\n", gd->relocaddr); #ifdef CONFIG_FSL_LSCH3 gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32)); gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr); gur_out32(&gur->scratchrw[6], 1); asm volatile("dsb st" : : : "memory"); rst->brrl = cores; asm volatile("dsb st" : : : "memory"); #elif defined(CONFIG_FSL_LSCH2) scfg_out32(&scfg->scratchrw[0], (u32)(gd->relocaddr >> 32)); scfg_out32(&scfg->scratchrw[1], (u32)gd->relocaddr); asm volatile("dsb st" : : : "memory"); gur_out32(&gur->brrl, cores); asm volatile("dsb st" : : : "memory"); /* Bootup online cores */ scfg_out32(&scfg->corebcr, cores); #endif /* This is needed as a precautionary measure. * If some code before this has accidentally released the secondary * cores then the pre-bootloader code will trap them in a "wfe" unless * the scratchrw[6] is set. In this case we need a sev here to get these * cores moving again. */ asm volatile("sev"); while (timeout--) { flush_dcache_range((unsigned long)table, (unsigned long)table + CONFIG_MAX_CPUS * 64); for (i = 1; i < CONFIG_MAX_CPUS; i++) { if (table[i * WORDS_PER_SPIN_TABLE_ENTRY + SPIN_TABLE_ELEM_STATUS_IDX]) cpu_up_mask |= 1 << i; } if (hweight32(cpu_up_mask) == hweight32(cores)) break; udelay(10); } if (timeout <= 0) { printf("Not all cores (0x%x) are up (0x%x)\n", cores, cpu_up_mask); return 1; } printf("All (%d) cores are up.\n", hweight32(cores)); return 0; }
int is_core_valid(unsigned int core) { return !!((1 << core) & cpu_mask()); }
inline Dtype mask_at(const vector<int>& index) const { return cpu_mask()[offset(index)]; }
inline Dtype mask_at(const int n, const int c, const int h, const int w) const{ return cpu_mask()[offset(n, c, h, w)]; }
int checkcpu (void) { sys_info_t sysinfo; uint pvr, svr; uint ver; uint major, minor; struct cpu_type *cpu; char buf1[32], buf2[32]; #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) ccsr_gur_t __iomem *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif /* * Cornet platforms use ddr sync bit in RCW to indicate sync vs async * mode. Previous platform use ddr ratio to do the same. This * information is only for display here. */ #ifdef CONFIG_FSL_CORENET #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 u32 ddr_sync = 0; /* only async mode is supported */ #else u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ #else /* CONFIG_FSL_CORENET */ #ifdef CONFIG_DDR_CLK_FREQ u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; #else u32 ddr_ratio = 0; #endif /* CONFIG_DDR_CLK_FREQ */ #endif /* CONFIG_FSL_CORENET */ unsigned int i, core, nr_cores = cpu_numcores(); u32 mask = cpu_mask(); svr = get_svr(); major = SVR_MAJ(svr); minor = SVR_MIN(svr); if (cpu_numcores() > 1) { #ifndef CONFIG_MP puts("Unicore software on multiprocessor system!!\n" "To enable mutlticore build define CONFIG_MP\n"); #endif volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); printf("CPU%d: ", pic->whoami); } else { puts("CPU: "); } cpu = gd->arch.cpu; puts(cpu->name); if (IS_E_PROCESSOR(svr)) puts("E"); printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); pvr = get_pvr(); ver = PVR_VER(pvr); major = PVR_MAJ(pvr); minor = PVR_MIN(pvr); printf("Core: "); switch(ver) { case PVR_VER_E500_V1: case PVR_VER_E500_V2: puts("e500"); break; case PVR_VER_E500MC: puts("e500mc"); break; case PVR_VER_E5500: puts("e5500"); break; case PVR_VER_E6500: puts("e6500"); break; default: puts("Unknown"); break; } printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); if (nr_cores > CONFIG_MAX_CPUS) { panic("\nUnexpected number of cores: %d, max is %d\n", nr_cores, CONFIG_MAX_CPUS); } get_sys_info(&sysinfo); puts("Clock Configuration:"); for_each_cpu(i, core, nr_cores, mask) { if (!(i & 3)) printf ("\n "); printf("CPU%d:%-4s MHz, ", core, strmhz(buf1, sysinfo.freqProcessor[core])); } printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); #ifdef CONFIG_FSL_CORENET if (ddr_sync == 1) { printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Synchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); } else { printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Asynchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); } #else switch (ddr_ratio) { case 0x0: printf(" DDR:%-4s MHz (%s MT/s data rate), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; case 0x7: printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Synchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; default: printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Asynchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; } #endif #if defined(CONFIG_FSL_LBC) if (sysinfo.freqLocalBus > LCRR_CLKDIV) { printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); } else { printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", sysinfo.freqLocalBus); } #endif #if defined(CONFIG_FSL_IFC) printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); #endif #ifdef CONFIG_CPM2 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); #endif #ifdef CONFIG_QE printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); #endif #ifdef CONFIG_SYS_DPAA_FMAN for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { printf(" FMAN%d: %s MHz\n", i + 1, strmhz(buf1, sysinfo.freqFMan[i])); } #endif #ifdef CONFIG_SYS_DPAA_QBMAN printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freqQMAN)); #endif #ifdef CONFIG_SYS_DPAA_PME printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); #endif puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); #ifdef CONFIG_FSL_CORENET /* Display the RCW, so that no one gets confused as to what RCW * we're actually using for this boot. */ puts("Reset Configuration Word (RCW):"); for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { u32 rcw = in_be32(&gur->rcwsr[i]); if ((i % 4) == 0) printf("\n %08x:", i * 4); printf(" %08x", rcw); } puts("\n"); #endif return 0; }
int checkcpu (void) { sys_info_t sysinfo; uint pvr, svr; uint ver; uint major, minor; struct cpu_type *cpu; char buf1[32], buf2[32]; #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) ccsr_gur_t __iomem *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif /* * Cornet platforms use ddr sync bit in RCW to indicate sync vs async * mode. Previous platform use ddr ratio to do the same. This * information is only for display here. */ #ifdef CONFIG_FSL_CORENET #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 u32 ddr_sync = 0; /* only async mode is supported */ #else u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */ #else /* CONFIG_FSL_CORENET */ #ifdef CONFIG_DDR_CLK_FREQ u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; #else u32 ddr_ratio = 0; #endif /* CONFIG_DDR_CLK_FREQ */ #endif /* CONFIG_FSL_CORENET */ unsigned int i, core, nr_cores = cpu_numcores(); u32 mask = cpu_mask(); #ifdef CONFIG_HETROGENOUS_CLUSTERS unsigned int j, dsp_core, dsp_numcores = cpu_num_dspcores(); u32 dsp_mask = cpu_dsp_mask(); #endif svr = get_svr(); major = SVR_MAJ(svr); minor = SVR_MIN(svr); #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) if (SVR_SOC_VER(svr) == SVR_T4080) { ccsr_rcpm_t *rcpm = (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 || FSL_CORENET_DEVDISR2_DTSEC1_9); setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3); setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3); /* It needs SW to disable core4~7 as HW design sake on T4080 */ for (i = 4; i < 8; i++) cpu_disable(i); /* request core4~7 into PH20 state, prior to entering PCL10 * state, all cores in cluster should be placed in PH20 state. */ setbits_be32(&rcpm->pcph20setr, 0xf0); /* put the 2nd cluster into PCL10 state */ setbits_be32(&rcpm->clpcl10setr, 1 << 1); } #endif if (cpu_numcores() > 1) { #ifndef CONFIG_MP puts("Unicore software on multiprocessor system!!\n" "To enable mutlticore build define CONFIG_MP\n"); #endif volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); printf("CPU%d: ", pic->whoami); } else { puts("CPU: "); } cpu = gd->arch.cpu; puts(cpu->name); if (IS_E_PROCESSOR(svr)) puts("E"); printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); pvr = get_pvr(); ver = PVR_VER(pvr); major = PVR_MAJ(pvr); minor = PVR_MIN(pvr); printf("Core: "); switch(ver) { case PVR_VER_E500_V1: case PVR_VER_E500_V2: puts("e500"); break; case PVR_VER_E500MC: puts("e500mc"); break; case PVR_VER_E5500: puts("e5500"); break; case PVR_VER_E6500: puts("e6500"); break; default: puts("Unknown"); break; } printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); if (nr_cores > CONFIG_MAX_CPUS) { panic("\nUnexpected number of cores: %d, max is %d\n", nr_cores, CONFIG_MAX_CPUS); } get_sys_info(&sysinfo); #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK if (sysinfo.diff_sysclk == 1) puts("Single Source Clock Configuration\n"); #endif puts("Clock Configuration:"); for_each_cpu(i, core, nr_cores, mask) { if (!(i & 3)) printf ("\n "); printf("CPU%d:%-4s MHz, ", core, strmhz(buf1, sysinfo.freq_processor[core])); } #ifdef CONFIG_HETROGENOUS_CLUSTERS for_each_cpu(j, dsp_core, dsp_numcores, dsp_mask) { if (!(j & 3)) printf("\n "); printf("DSP CPU%d:%-4s MHz, ", j, strmhz(buf1, sysinfo.freq_processor_dsp[dsp_core])); } #endif printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus)); printf("\n"); #ifdef CONFIG_FSL_CORENET if (ddr_sync == 1) { printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Synchronous), ", strmhz(buf1, sysinfo.freq_ddrbus/2), strmhz(buf2, sysinfo.freq_ddrbus)); } else { printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Asynchronous), ", strmhz(buf1, sysinfo.freq_ddrbus/2), strmhz(buf2, sysinfo.freq_ddrbus)); } #else switch (ddr_ratio) { case 0x0: printf(" DDR:%-4s MHz (%s MT/s data rate), ", strmhz(buf1, sysinfo.freq_ddrbus/2), strmhz(buf2, sysinfo.freq_ddrbus)); break; case 0x7: printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Synchronous), ", strmhz(buf1, sysinfo.freq_ddrbus/2), strmhz(buf2, sysinfo.freq_ddrbus)); break; default: printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Asynchronous), ", strmhz(buf1, sysinfo.freq_ddrbus/2), strmhz(buf2, sysinfo.freq_ddrbus)); break; } #endif #if defined(CONFIG_FSL_LBC) if (sysinfo.freq_localbus > LCRR_CLKDIV) { printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus)); } else { printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", sysinfo.freq_localbus); } #endif #if defined(CONFIG_FSL_IFC) printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freq_localbus)); #endif #ifdef CONFIG_CPM2 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freq_systembus)); #endif #ifdef CONFIG_QE printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe)); #endif #if defined(CONFIG_SYS_CPRI) printf(" "); printf("CPRI:%-4s MHz", strmhz(buf1, sysinfo.freq_cpri)); #endif #if defined(CONFIG_SYS_MAPLE) printf("\n "); printf("MAPLE:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple)); printf("MAPLE-ULB:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple_ulb)); printf("MAPLE-eTVPE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_maple_etvpe)); #endif #ifdef CONFIG_SYS_DPAA_FMAN for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { printf(" FMAN%d: %s MHz\n", i + 1, strmhz(buf1, sysinfo.freq_fman[i])); } #endif #ifdef CONFIG_SYS_DPAA_QBMAN printf(" QMAN: %s MHz\n", strmhz(buf1, sysinfo.freq_qman)); #endif #ifdef CONFIG_SYS_DPAA_PME printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freq_pme)); #endif puts("L1: D-cache 32 KiB enabled\n I-cache 32 KiB enabled\n"); #ifdef CONFIG_FSL_CORENET /* Display the RCW, so that no one gets confused as to what RCW * we're actually using for this boot. */ puts("Reset Configuration Word (RCW):"); for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { u32 rcw = in_be32(&gur->rcwsr[i]); if ((i % 4) == 0) printf("\n %08x:", i * 4); printf(" %08x", rcw); } puts("\n"); #endif return 0; }
int checkcpu (void) { sys_info_t sysinfo; uint pvr, svr; uint ver; uint major, minor; struct cpu_type *cpu; char buf1[32], buf2[32]; #if defined(CONFIG_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #endif /* CONFIG_FSL_CORENET */ #ifdef CONFIG_DDR_CLK_FREQ u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO) >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT; #else #ifdef CONFIG_FSL_CORENET u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) >> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT; #else u32 ddr_ratio = 0; #endif /* CONFIG_FSL_CORENET */ #endif /* CONFIG_DDR_CLK_FREQ */ unsigned int i, core, nr_cores = cpu_numcores(); u32 mask = cpu_mask(); svr = get_svr(); major = SVR_MAJ(svr); minor = SVR_MIN(svr); if (cpu_numcores() > 1) { #ifndef CONFIG_MP puts("Unicore software on multiprocessor system!!\n" "To enable mutlticore build define CONFIG_MP\n"); #endif volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); printf("CPU%d: ", pic->whoami); } else { puts("CPU: "); } cpu = gd->cpu; puts(cpu->name); if (IS_E_PROCESSOR(svr)) puts("E"); printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr); pvr = get_pvr(); ver = PVR_VER(pvr); major = PVR_MAJ(pvr); minor = PVR_MIN(pvr); printf("Core: "); switch(ver) { case PVR_VER_E500_V1: case PVR_VER_E500_V2: puts("E500"); break; case PVR_VER_E500MC: puts("E500MC"); break; case PVR_VER_E5500: puts("E5500"); break; default: puts("Unknown"); break; } printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr); get_sys_info(&sysinfo); puts("Clock Configuration:"); for_each_cpu(i, core, nr_cores, mask) { if (!(i & 3)) printf ("\n "); printf("CPU%d:%-4s MHz, ", core, strmhz(buf1, sysinfo.freqProcessor[core])); } printf("\n CCB:%-4s MHz,\n", strmhz(buf1, sysinfo.freqSystemBus)); #ifdef CONFIG_FSL_CORENET if (ddr_sync == 1) { printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Synchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); } else { printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Asynchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); } #else switch (ddr_ratio) { case 0x0: printf(" DDR:%-4s MHz (%s MT/s data rate), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; case 0x7: printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Synchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; default: printf(" DDR:%-4s MHz (%s MT/s data rate) " "(Asynchronous), ", strmhz(buf1, sysinfo.freqDDRBus/2), strmhz(buf2, sysinfo.freqDDRBus)); break; } #endif #if defined(CONFIG_FSL_LBC) if (sysinfo.freqLocalBus > LCRR_CLKDIV) { printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); } else { printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n", sysinfo.freqLocalBus); } #endif #if defined(CONFIG_FSL_IFC) printf("IFC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus)); #endif #ifdef CONFIG_CPM2 printf("CPM: %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus)); #endif #ifdef CONFIG_QE printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freqQE)); #endif #ifdef CONFIG_SYS_DPAA_FMAN for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) { printf(" FMAN%d: %s MHz\n", i + 1, strmhz(buf1, sysinfo.freqFMan[i])); } #endif #ifdef CONFIG_SYS_DPAA_PME printf(" PME: %s MHz\n", strmhz(buf1, sysinfo.freqPME)); #endif puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); return 0; }