static void __init migor_setup(char **cmdline_p) { /* SMC91C111 - Enable IRQ0 */ ctrl_outw(ctrl_inw(PORT_PJCR) & ~0x0003, PORT_PJCR); /* KEYSC */ ctrl_outw(ctrl_inw(PORT_PYCR) & ~0x0fff, PORT_PYCR); ctrl_outw(ctrl_inw(PORT_PZCR) & ~0x0ff0, PORT_PZCR); ctrl_outw(ctrl_inw(PORT_PSELA) & ~0x4100, PORT_PSELA); ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x4000, PORT_HIZCRA); ctrl_outw(ctrl_inw(PORT_HIZCRC) & ~0xc000, PORT_HIZCRC); ctrl_outl(ctrl_inl(MSTPCR2) & ~0x00004000, MSTPCR2); /* NAND Flash */ ctrl_outw(ctrl_inw(PORT_PXCR) & 0x0fff, PORT_PXCR); ctrl_outl((ctrl_inl(BSC_CS6ABCR) & ~0x00000600) | 0x00000200, BSC_CS6ABCR); /* I2C */ ctrl_outl(ctrl_inl(MSTPCR1) & ~0x00000200, MSTPCR1); /* Touch Panel - Enable IRQ6 */ ctrl_outw(ctrl_inw(PORT_PZCR) & ~0xc, PORT_PZCR); ctrl_outw((ctrl_inw(PORT_PSELA) | 0x8000), PORT_PSELA); ctrl_outw((ctrl_inw(PORT_HIZCRC) & ~0x4000), PORT_HIZCRC); }
/* For SH7707, SH7709, SH7709A, SH7729 */ static void sci_init_pins_scif(struct sci_port* port, unsigned int cflag) { unsigned int fcr_val = 0; { unsigned short data; /* We need to set SCPCR to enable RTS/CTS */ data = ctrl_inw(SCPCR); /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/ ctrl_outw(data&0x0fcf, SCPCR); } if (cflag & CRTSCTS) fcr_val |= SCFCR_MCE; else { unsigned short data; /* We need to set SCPCR to enable RTS/CTS */ data = ctrl_inw(SCPCR); /* Clear out SCP7MD1,0, SCP4MD1,0, Set SCP6MD1,0 = {01} (output) */ ctrl_outw((data&0x0fcf)|0x1000, SCPCR); data = ctrl_inb(SCPDR); /* Set /RTS2 (bit6) = 0 */ ctrl_outb(data&0xbf, SCPDR); } sci_out(port, SCFCR, fcr_val); }
/* * Initialize the board */ static void __init highlander_setup(char **cmdline_p) { u16 ver = ctrl_inw(PA_VERREG); int i; printk(KERN_INFO "Renesas Solutions Highlander %s support.\n", mach_is_r7780rp() ? "R7780RP-1" : mach_is_r7780mp() ? "R7780MP" : "R7785RP"); printk(KERN_INFO "Board version: %d (revision %d), " "FPGA version: %d (revision %d)\n", (ver >> 12) & 0xf, (ver >> 8) & 0xf, (ver >> 4) & 0xf, ver & 0xf); /* * Enable the important clocks right away.. */ for (i = 0; i < ARRAY_SIZE(r7780rp_clocks); i++) { struct clk *clk = r7780rp_clocks[i]; clk_register(clk); clk_enable(clk); } ctrl_outw(0x0000, PA_OBLED); /* Clear LED. */ if (mach_is_r7780rp()) ctrl_outw(0x0001, PA_SDPOW); /* SD Power ON */ ctrl_outw(ctrl_inw(PA_IVDRCTL) | 0x01, PA_IVDRCTL); /* Si13112 */ pm_power_off = r7780rp_power_off; }
static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) { unsigned int fcr_val = 0; unsigned short data; if (cflag & CRTSCTS) { /* enable RTS/CTS */ if (port->mapbase == 0xa4430000) { /* SCIF0 */ /* Clear PTCR bit 9-2; enable all scif pins but sck */ data = ctrl_inw(PORT_PTCR); ctrl_outw((data & 0xfc03), PORT_PTCR); } else if (port->mapbase == 0xa4438000) { /* SCIF1 */ /* Clear PVCR bit 9-2 */ data = ctrl_inw(PORT_PVCR); ctrl_outw((data & 0xfc03), PORT_PVCR); } fcr_val |= SCFCR_MCE; } else { if (port->mapbase == 0xa4430000) { /* SCIF0 */ /* Clear PTCR bit 5-2; enable only tx and rx */ data = ctrl_inw(PORT_PTCR); ctrl_outw((data & 0xffc3), PORT_PTCR); } else if (port->mapbase == 0xa4438000) { /* SCIF1 */ /* Clear PVCR bit 5-2 */ data = ctrl_inw(PORT_PVCR); ctrl_outw((data & 0xffc3), PORT_PVCR); } } sci_out(port, SCFCR, fcr_val); }
/* For SH7707, SH7709, SH7709A, SH7729, SH7300*/ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) { unsigned int fcr_val = 0; #if !defined(CONFIG_CPU_SUBTYPE_SH7300) /* SH7300 doesn't use RTS/CTS */ { unsigned short data; /* We need to set SCPCR to enable RTS/CTS */ data = ctrl_inw(SCPCR); /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/ ctrl_outw(data&0x0fcf, SCPCR); } if (cflag & CRTSCTS) fcr_val |= SCFCR_MCE; else { unsigned short data; /* We need to set SCPCR to enable RTS/CTS */ data = ctrl_inw(SCPCR); /* Clear out SCP7MD1,0, SCP4MD1,0, Set SCP6MD1,0 = {01} (output) */ ctrl_outw((data&0x0fcf)|0x1000, SCPCR); data = ctrl_inb(SCPDR); /* Set /RTS2 (bit6) = 0 */ ctrl_outb(data&0xbf, SCPDR); } #endif sci_out(port, SCFCR, fcr_val); }
static int sh7750_perf_counter_start(void) { u16 pmcr; /* Enable counter 1 */ if (ctr[0].enabled) { pmcr = ctrl_inw(PMCR1); WARN_ON(pmcr & PMCR_PMEN); pmcr &= ~PMCR_PMM_MASK; pmcr |= ctr[0].event; ctrl_outw(pmcr | PMCR_ENABLE, PMCR1); } /* Enable counter 2 */ if (ctr[1].enabled) { pmcr = ctrl_inw(PMCR2); WARN_ON(pmcr & PMCR_PMEN); pmcr &= ~PMCR_PMM_MASK; pmcr |= ctr[1].event; ctrl_outw(pmcr | PMCR_ENABLE, PMCR2); } return register_profile_notifier(&sh7750_timer_notifier); }
/* * Initialize IRQ setting */ void __init init_rts7751r2d_IRQ(void) { struct intc_desc *d; switch (ctrl_inw(PA_VERREG) & 0xf0) { #ifdef CONFIG_RTS7751R2D_PLUS case 0x10: printk(KERN_INFO "Using R2D-PLUS interrupt controller.\n"); d = &intc_desc_r2d_plus; memcpy(irl2irq, irl2irq_r2d_plus, R2D_NR_IRL); break; #endif #ifdef CONFIG_RTS7751R2D_1 case 0x00: /* according to manual */ case 0x30: /* in reality */ printk(KERN_INFO "Using R2D-1 interrupt controller.\n"); d = &intc_desc_r2d_1; memcpy(irl2irq, irl2irq_r2d_1, R2D_NR_IRL); break; #endif default: printk(KERN_INFO "Unknown R2D interrupt controller 0x%04x\n", ctrl_inw(PA_VERREG)); return; } register_intc_controller(d); #ifdef CONFIG_MFD_SM501 setup_voyagergx_irq(); #endif }
static void sh7750_perf_counter_stop(void) { ctrl_outw(ctrl_inw(PMCR1) & ~PMCR_PMEN, PMCR1); ctrl_outw(ctrl_inw(PMCR2) & ~PMCR_PMEN, PMCR2); unregister_profile_notifier(&sh7750_timer_notifier); }
unsigned short hs7751rvoip_inw(unsigned long port) { if (PXSEG(port)) return ctrl_inw(port); else if (is_pci_ioaddr(port) || shifted_port(port)) return ctrl_inw(pci_ioaddr(port)); else maybebadio(port); return 0; }
u16 titan_inw(unsigned long port) { if (PXSEG(port)) return ctrl_inw(port); else if (port >= 0x2000) return ctrl_inw(port2adr(port)); else maybebadio(port); return 0; }
static inline void delay(void) { #if defined(CONFIG_PCI) /* System board present, just make a dummy SRAM access. (CS0 will be mapped to PCI memory, probably good to avoid it.) */ ctrl_inw(0xa6800000); #else /* CS0 will be mapped to flash, ROM etc so safe to access it. */ ctrl_inw(0xa0000000); #endif }
u16 landisk_inw(unsigned long port) { if (PXSEG(port)) return ctrl_inw(port); else if (is_pci_ioaddr(port)) return ctrl_inw(pci_ioaddr(port)); else maybebadio(port); return 0; }
static void __init sdk7780_setup(char **cmdline_p) { u16 ver = ctrl_inw(FPGA_FPVERR); u16 dateStamp = ctrl_inw(FPGA_FPDATER); printk(KERN_INFO "Renesas Technology Europe SDK7780 support.\n"); printk(KERN_INFO "Board version: %d (revision %d), " "FPGA version: %d (revision %d), datestamp : %d\n", (ver >> 12) & 0xf, (ver >> 8) & 0xf, (ver >> 4) & 0xf, ver & 0xf, dateStamp); /* Setup pin mux'ing for PCIC */ ctrl_outw(0x0000, GPIO_PECR); }
static int camera_power(struct device *dev, int mode) { int ret; if (mode) { long rate; camera_clk = clk_get(NULL, "video_clk"); if (IS_ERR(camera_clk)) return PTR_ERR(camera_clk); rate = clk_round_rate(camera_clk, CEU_MCLK_FREQ); ret = clk_set_rate(camera_clk, rate); if (ret < 0) goto eclkrate; /* set DRVCRB * * use 1.8 V for VccQ_VIO * use 2.85V for VccQ_SR */ ctrl_outw((ctrl_inw(DRVCRB) & ~0x0003) | 0x0001, DRVCRB); /* reset clear */ ret = gpio_request(GPIO_PTB4, NULL); if (ret < 0) goto eptb4; ret = gpio_request(GPIO_PTB7, NULL); if (ret < 0) goto eptb7; ret = gpio_direction_output(GPIO_PTB4, 1); if (!ret) ret = gpio_direction_output(GPIO_PTB7, 1); if (ret < 0) goto egpioout; msleep(1); ret = clk_enable(camera_clk); /* start VIO_CKO */ if (ret < 0) goto eclkon; return 0; } ret = 0; clk_disable(camera_clk); eclkon: gpio_set_value(GPIO_PTB7, 0); egpioout: gpio_set_value(GPIO_PTB4, 0); gpio_free(GPIO_PTB7); eptb7: gpio_free(GPIO_PTB4); eptb4: eclkrate: clk_put(camera_clk); return ret; }
static void cpu_clk_recalc(struct clk *clk) { int frqcr = ctrl_inw(FRQCR); int idx = (frqcr & 0x0030) >> 4; clk->rate = clk->parent->rate / divisors[idx]; }
static void __init se7780_setup(char **cmdline_p) { /* "SH-Linux" on LED Display */ ctrl_outw( 'S' , PA_LED_DISP + (DISP_SEL0_ADDR << 1) ); ctrl_outw( 'H' , PA_LED_DISP + (DISP_SEL1_ADDR << 1) ); ctrl_outw( '-' , PA_LED_DISP + (DISP_SEL2_ADDR << 1) ); ctrl_outw( 'L' , PA_LED_DISP + (DISP_SEL3_ADDR << 1) ); ctrl_outw( 'i' , PA_LED_DISP + (DISP_SEL4_ADDR << 1) ); ctrl_outw( 'n' , PA_LED_DISP + (DISP_SEL5_ADDR << 1) ); ctrl_outw( 'u' , PA_LED_DISP + (DISP_SEL6_ADDR << 1) ); ctrl_outw( 'x' , PA_LED_DISP + (DISP_SEL7_ADDR << 1) ); printk(KERN_INFO "Hitachi UL Solutions Engine 7780SE03 support.\n"); /* * PCI REQ/GNT setting * REQ0/GNT0 -> USB * REQ1/GNT1 -> PC Card * REQ2/GNT2 -> Serial ATA * REQ3/GNT3 -> PCI slot */ ctrl_outw(0x0213, FPGA_REQSEL); /* GPIO setting */ ctrl_outw(0x0000, GPIO_PECR); ctrl_outw(ctrl_inw(GPIO_PHCR)&0xfff3, GPIO_PHCR); ctrl_outw(0x0c00, GPIO_PMSELR); /* iVDR Power ON */ ctrl_outw(0x0001, FPGA_IVDRPW); }
static int exm7760_i2s_init(void) { int ret; unsigned short ipsel; printk(KERN_INFO "EXM32 Motherboard I2S Audio support\n"); /* switch PFC to I2S on both audio paths */ ipsel = ctrl_inw(IPSEL); ipsel &= ~(3<<10); ctrl_outw(ipsel, IPSEL); ret = -ENOMEM; exm7760_i2s_snd_device = platform_device_alloc("soc-audio", -1); if (!exm7760_i2s_snd_device) goto out; platform_set_drvdata(exm7760_i2s_snd_device, &exm7760_i2s_snd_devdata); exm7760_i2s_snd_devdata.dev = &exm7760_i2s_snd_device->dev; ret = platform_device_add(exm7760_i2s_snd_device); if (ret) platform_device_put(exm7760_i2s_snd_device); out: MSG("module_init() exit (ret %d)\n", ret); return ret; }
/* * Initialize the board */ static void __init rts7751r2d_setup(char **cmdline_p) { void __iomem *sm501_reg; u16 ver = ctrl_inw(PA_VERREG); printk(KERN_INFO "Renesas Technology Sales RTS7751R2D support.\n"); printk(KERN_INFO "FPGA version:%d (revision:%d)\n", (ver >> 4) & 0xf, ver & 0xf); ctrl_outw(0x0000, PA_OUTPORT); pm_power_off = rts7751r2d_power_off; /* sm501 dram configuration: * ColSizeX = 11 - External Memory Column Size: 256 words. * APX = 1 - External Memory Active to Pre-Charge Delay: 7 clocks. * RstX = 1 - External Memory Reset: Normal. * Rfsh = 1 - Local Memory Refresh to Command Delay: 12 clocks. * BwC = 1 - Local Memory Block Write Cycle Time: 2 clocks. * BwP = 1 - Local Memory Block Write to Pre-Charge Delay: 1 clock. * AP = 1 - Internal Memory Active to Pre-Charge Delay: 7 clocks. * Rst = 1 - Internal Memory Reset: Normal. * RA = 1 - Internal Memory Remain in Active State: Do not remain. */ sm501_reg = (void __iomem *)0xb3e00000 + SM501_DRAM_CONTROL; writel(readl(sm501_reg) | 0x00f107c0, sm501_reg); }
static void module_clk_recalc(struct clk *clk) { int frqcr = ctrl_inw(FRQCR); int idx = frqcr & 0x0007; clk->rate = clk->parent->rate / divisors[idx]; }
static inline void handle_syscall_restart(unsigned long save_r0, struct pt_regs *regs, struct sigaction *sa) { /* If we're not from a syscall, bail out */ if (regs->tra < 0) return; /* check for system call restart.. */ switch (regs->regs[0]) { case -ERESTART_RESTARTBLOCK: case -ERESTARTNOHAND: no_system_call_restart: regs->regs[0] = -EINTR; break; case -ERESTARTSYS: if (!(sa->sa_flags & SA_RESTART)) goto no_system_call_restart; /* fallthrough */ case -ERESTARTNOINTR: regs->regs[0] = save_r0; regs->pc -= instruction_size(ctrl_inw(regs->pc - 4)); break; } }
/* * Initialize IRQ setting */ void __init init_se7780_IRQ(void) { /* enable all interrupt at FPGA */ ctrl_outw(0, FPGA_INTMSK1); /* mask SM501 interrupt */ ctrl_outw((ctrl_inw(FPGA_INTMSK1) | 0x0002), FPGA_INTMSK1); /* enable all interrupt at FPGA */ ctrl_outw(0, FPGA_INTMSK2); /* set FPGA INTSEL register */ /* FPGA + 0x06 */ ctrl_outw( ((IRQPIN_SM501 << IRQPOS_SM501) | (IRQPIN_SMC91CX << IRQPOS_SMC91CX)), FPGA_INTSEL1); /* FPGA + 0x08 */ ctrl_outw(((IRQPIN_EXTINT4 << IRQPOS_EXTINT4) | (IRQPIN_EXTINT3 << IRQPOS_EXTINT3) | (IRQPIN_EXTINT2 << IRQPOS_EXTINT2) | (IRQPIN_EXTINT1 << IRQPOS_EXTINT1)), FPGA_INTSEL2); /* FPGA + 0x0A */ ctrl_outw((IRQPIN_PCCPW << IRQPOS_PCCPW), FPGA_INTSEL3); plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-7 */ }
static void disable_ipr_irq(unsigned int irq) { struct ipr_data *p = get_irq_chip_data(irq); unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx]; /* Set the priority in IPR to 0 */ ctrl_outw(ctrl_inw(addr) & (0xffff ^ (0xf << p->shift)), addr); }
static void enable_ipr_irq(unsigned int irq) { struct ipr_data *p = get_irq_chip_data(irq); unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx]; /* Set priority in IPR back to original value */ ctrl_outw(ctrl_inw(addr) | (p->priority << p->shift), addr); }
static void fast_timer_irq(int irq, void *dev_instance, struct pt_regs *regs) { unsigned long timer_status; timer_status = ctrl_inw(TMU1_TCR); timer_status &= ~0x100; ctrl_outw(timer_status, TMU1_TCR); }
static int __init sh7760_ac97_init(void) { int ret; unsigned short ipsel; /* enable both AC97 controllers in pinmux reg */ ipsel = ctrl_inw(IPSEL); ctrl_outw(ipsel | (3 << 10), IPSEL); ret = -ENOMEM; sh7760_ac97_snd_device = platform_device_alloc("soc-audio", -1); if (!sh7760_ac97_snd_device) goto out; platform_set_drvdata(sh7760_ac97_snd_device, &sh7760_ac97_snd_devdata); sh7760_ac97_snd_devdata.dev = &sh7760_ac97_snd_device->dev; ret = platform_device_add(sh7760_ac97_snd_device); if (ret) platform_device_put(sh7760_ac97_snd_device); out: return ret; }
static irqreturn_t psw_irq_handler(int irq, void *arg) { struct platform_device *pdev = arg; struct push_switch *psw = platform_get_drvdata(pdev); struct push_switch_platform_info *psw_info = pdev->dev.platform_data; unsigned int l, mask; int ret = 0; l = ctrl_inw(PA_DBSW); /* Nothing to do if there's no state change */ if (psw->state) { ret = 1; goto out; } mask = l & 0x70; /* Figure out who raised it */ if (mask & (1 << psw_info->bit)) { psw->state = !!(mask & (1 << psw_info->bit)); if (psw->state) /* debounce */ mod_timer(&psw->debounce, jiffies + 50); ret = 1; } out: /* Clear the switch IRQs */ l |= (0x7 << 12); ctrl_outw(l, PA_DBSW); return IRQ_RETVAL(ret); }
static void master_clk_init(struct clk *clk) { int frqcr = ctrl_inw(FRQCR); int idx = (frqcr & 0x0300) >> 8; clk->rate *= multipliers[idx]; }
int __init oprofile_arch_init(struct oprofile_operations **ops) { if (!(current_cpu_data.flags & CPU_HAS_PERF_COUNTER)) return -ENODEV; sh7750_perf_counter_ops.cpu_type = (char *)get_cpu_subtype(); *ops = &sh7750_perf_counter_ops; printk(KERN_INFO "oprofile: using SH-4 (%s) performance monitoring.\n", sh7750_perf_counter_ops.cpu_type); /* Clear the counters */ ctrl_outw(ctrl_inw(PMCR1) | PMCR_PMCLR, PMCR1); ctrl_outw(ctrl_inw(PMCR2) | PMCR_PMCLR, PMCR2); return 0; }
static void cmt_clk_init(struct clk *clk) { u8 divisor = CMT_CMCSR_INIT & 0x3; ctrl_inw(CMT_CMCSR_0); ctrl_outw(CMT_CMCSR_INIT, CMT_CMCSR_0); clk->parent = clk_get(NULL, "module_clk"); clk->rate = clk->parent->rate / (8 << (divisor << 1)); }
static int __init cf_init_se(void) { if ((ctrl_inw(MRSHPC_CSR) & 0x000c) != 0) return 0; /* Not detected */ if ((ctrl_inw(MRSHPC_CSR) & 0x0080) == 0) { ctrl_outw(0x0674, MRSHPC_CPWCR); /* Card Vcc is 3.3v? */ } else { ctrl_outw(0x0678, MRSHPC_CPWCR); /* Card Vcc is 5V */ } /* * PC-Card window open * flag == COMMON/ATTRIBUTE/IO */ /* common window open */ ctrl_outw(0x8a84, MRSHPC_MW0CR1);/* window 0xb8400000 */ if((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0) /* common mode & bus width 16bit SWAP = 1*/ ctrl_outw(0x0b00, MRSHPC_MW0CR2); else /* common mode & bus width 16bit SWAP = 0*/ ctrl_outw(0x0300, MRSHPC_MW0CR2); /* attribute window open */ ctrl_outw(0x8a85, MRSHPC_MW1CR1);/* window 0xb8500000 */ if ((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0) /* attribute mode & bus width 16bit SWAP = 1*/ ctrl_outw(0x0a00, MRSHPC_MW1CR2); else /* attribute mode & bus width 16bit SWAP = 0*/ ctrl_outw(0x0200, MRSHPC_MW1CR2); /* I/O window open */ ctrl_outw(0x8a86, MRSHPC_IOWCR1);/* I/O window 0xb8600000 */ ctrl_outw(0x0008, MRSHPC_CDCR); /* I/O card mode */ if ((ctrl_inw(MRSHPC_CSR) & 0x4000) != 0) ctrl_outw(0x0a00, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 1*/ else ctrl_outw(0x0200, MRSHPC_IOWCR2); /* bus width 16bit SWAP = 0*/ ctrl_outw(0x2000, MRSHPC_ICR); ctrl_outb(0x00, PA_MRSHPC_MW2 + 0x206); ctrl_outb(0x42, PA_MRSHPC_MW2 + 0x200); return 0; }