void start_armboot(void) { ENTRY entry = (ENTRY)IMAGE_ENTRY; unsigned char *pdst = (unsigned char *)IMAGE_ENTRY; unsigned int image_data_len = input_data_end - input_data; malloc_start = (char *)(_armboot_start - CONFIG_SYS_MALLOC_LEN); uart_early_puts("\r\n\r\nCompressed-boot v1.0.0\r\n"); /* DDR should larger than 16M */ mmu_init((MEM_BASE_DDR + 0x4000), MEM_BASE_DDR, 0x1000000); dcache_enable(0); if (input_data[0] == 0x5D) { uart_early_puts("Uncompress"); decompress(input_data, image_data_len, pdst); uart_early_puts("Ok\r\n"); } else { int *s = (int *)input_data; int *d = (int *)pdst; unsigned int len = ((image_data_len + 3) >> 2); while (len--) *d++ = *s++; } dcache_disable(); entry(); }
int do_dcache ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { switch (argc) { case 2: /* on / off */ switch (on_off(argv[1])) { #if 0 /* prevented by varargs handling; FALLTROUGH is harmless, too */ default: printf ("Usage:\n%s\n", cmdtp->usage); return; #endif case 0: dcache_disable(); break; case 1: dcache_enable (); break; } /* FALL TROUGH */ case 1: /* get status */ printf ("Data (writethrough) Cache is %s\n", dcache_status() ? "ON" : "OFF"); return 0; default: printf ("Usage:\n%s\n", cmdtp->usage); return 1; } return 0; }
/* ************************************************************************************************************ * * function * * name : * * parmeters : * * return : * * note : * * ************************************************************************************************************ */ void sunxi_flush_allcaches(void) { icache_disable(); flush_dcache_all(); dcache_disable(); }
/* * initialize higher level parts of CPU like time base and timers */ int cpu_init_r (void) { #if defined(CONFIG_405GP) || defined(CONFIG_405EP) DECLARE_GLOBAL_DATA_PTR; bd_t *bd = gd->bd; unsigned long reg; #if defined(CONFIG_405GP) uint pvr = get_pvr(); #endif #ifdef CFG_INIT_DCACHE_CS /* * Flush and invalidate dcache, then disable CS for temporary stack. * Afterwards, this CS can be used for other purposes */ dcache_disable(); /* flush and invalidate dcache */ mtebc(PBxAP, 0); mtebc(PBxCR, 0); /* disable CS for temporary stack */ #if (defined(PBxAP_VAL) && defined(PBxCR_VAL)) /* * Write new value into CS register */ mtebc(PBxAP, PBxAP_VAL); mtebc(PBxCR, PBxCR_VAL); #endif #endif /* CFG_INIT_DCACHE_CS */ /* * Write Ethernetaddress into on-chip register */ reg = 0x00000000; reg |= bd->bi_enetaddr[0]; /* set high address */ reg = reg << 8; reg |= bd->bi_enetaddr[1]; out32 (EMAC_IAH, reg); reg = 0x00000000; reg |= bd->bi_enetaddr[2]; /* set low address */ reg = reg << 8; reg |= bd->bi_enetaddr[3]; reg = reg << 8; reg |= bd->bi_enetaddr[4]; reg = reg << 8; reg |= bd->bi_enetaddr[5]; out32 (EMAC_IAL, reg); #if defined(CONFIG_405GP) /* * Set edge conditioning circuitry on PPC405GPr * for compatibility to existing PPC405GP designs. */ if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) { mtdcr(ecr, 0x60606000); } #endif /* defined(CONFIG_405GP) */ #endif /* defined(CONFIG_405GP) || defined(CONFIG_405EP) */ return (0); }
int cleanup_before_linux (void) { /* * this function is called just before we call linux * it prepares the processor for linux * * we turn off caches etc ... * and we set the CPU-speed to 73 MHz - see start.S for details */ #if defined(CONFIG_IMPA7) || defined(CONFIG_EP7312) || defined(CONFIG_ARMADILLO) disable_interrupts (); /* turn off I-cache */ icache_disable(); dcache_disable(); /* flush I-cache */ cache_flush(); #ifdef CONFIG_ARM7_REVD /* go to high speed */ IO_SYSCON3 = (IO_SYSCON3 & ~CLKCTL) | CLKCTL_73; #endif #elif defined(CONFIG_NETARM) || defined(CONFIG_S3C4510B) || defined(CONFIG_LPC2292) disable_interrupts (); /* Nothing more needed */ #elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR) /* No cleanup before linux for IntegratorAP/CM720T as yet */ #else #error No cleanup_before_linux() defined for this CPU type #endif return 0; }
static bool_t mach_cleanup(void) { /* stop timer 0 ~ 4 */ writel(S5PV210_TCON, 0x0); /* stop system timer */ writel(S5PV210_SYSTIMER_TCON, 0x0); /* disable irq */ irq_disable(); /* disable fiq */ fiq_disable(); /* disable icache */ icache_disable(); /* disable dcache */ dcache_disable(); /* disable mmu */ mmu_disable(); /* disable vic */ vic_disable(); return TRUE; }
unsigned long do_bootelf_exec(ulong (*entry)(int, char * const[]), int argc, char * const argv[]) { unsigned long ret; int i; /* * QNX images require the data cache is disabled. * Data cache is already flushed, so just turn it off. */ int dcache = dcache_status(); if (dcache) dcache_disable(); /* * pass address parameter as argv[0] (aka command name), * and all remaining args */ for(i=0;i<argc;i++) { printf("%d : %s\n",argc,argv); } ret = entry(argc, argv); if (dcache) dcache_enable(); return ret; }
void board_init_f(ulong dummy) { dcache_disable(); socfpga_init_security_policies(); socfpga_sdram_remap_zero(); /* Assert reset to all except L4WD0 and L4TIMER0 */ socfpga_per_reset_all(); socfpga_watchdog_disable(); spl_early_init(); /* Configure the clock based on handoff */ cm_basic_init(gd->fdt_blob); #ifdef CONFIG_HW_WATCHDOG /* release osc1 watchdog timer 0 from reset */ socfpga_reset_deassert_osc1wd0(); /* reconfigure and enable the watchdog */ hw_watchdog_init(); WATCHDOG_RESET(); #endif /* CONFIG_HW_WATCHDOG */ config_dedicated_pins(gd->fdt_blob); WATCHDOG_RESET(); }
int do_bootldr(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { void *addr; uint32_t *data; /* Get the address */ if (argc < 2) addr = (void *)load_addr; else addr = (void *)simple_strtoul(argv[1], NULL, 16); /* Check if it is a LDR file */ data = addr; #if defined(__ADSPBF54x__) || defined(__ADSPBF52x__) if ((*data & 0xFF000000) == 0xAD000000 && data[2] == 0x00000000) { #else if (*data == 0xFF800060 || *data == 0xFF800040 || *data == 0xFF800020) { #endif /* We want to boot from FLASH or SDRAM */ printf("## Booting ldr image at 0x%p ...\n", addr); icache_disable(); dcache_disable(); __asm__( "jump (%1);" : : "q7" (addr), "a" (_BOOTROM_MEMBOOT)); } else
int cleanup_before_linux (void) { /* * this function is called just before we call linux * it prepares the processor for linux * * we turn off caches etc ... */ disable_interrupts (); #ifdef CONFIG_LCD { extern void lcd_disable(void); extern void lcd_panel_disable(void); lcd_disable(); /* proper disable of lcd & panel */ lcd_panel_disable(); } #endif /* turn off I/D-cache */ icache_disable(); dcache_disable(); /* flush I/D-cache */ cache_flush(); /*Workaround to enable L2CC during kernel decompressing*/ #ifdef fixup_before_linux fixup_before_linux; #endif return 0; }
int cleanup_before_linux(void) { unsigned int i; /* * this function is called just before we call linux * it prepares the processor for linux * * we turn off caches etc ... */ disable_interrupts(); /* turn off I/D-cache */ icache_disable(); dcache_disable(); /* invalidate I-cache */ cache_flush(); #ifndef CONFIG_L2_OFF /* turn off L2 cache */ l2_cache_disable(); /* invalidate L2 cache also */ v7_flush_dcache_all(get_device_type()); #endif i = 0; /* mem barrier to sync up things */ asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i)); #ifndef CONFIG_L2_OFF l2_cache_enable(); #endif return 0; }
int /**********************************************************/ board_init (void) /**********************************************************/ { /* We have RAM, disable cache */ dcache_disable(); icache_disable(); led_code (0xf, YELLOW); /* arch number of HHP Cradle */ gd->bd->bi_arch_number = MACH_TYPE_HHP_CRADLE; /* adress of boot parameters */ gd->bd->bi_boot_params = 0xa0000100; /* Init SIOs to enable SCC2 */ udelay (100000); /* delay makes it look neat */ init_sio (0, CRADLE_SIO1_PHYS); udelay (100000); init_sio (1, CRADLE_SIO2_PHYS); udelay (100000); init_sio (2, CRADLE_SIO3_PHYS); udelay (100000); set_led (3, GREEN); return 1; }
int cleanup_before_linux(void) { /* * this function is called just before we call linux * it prepares the processor for linux * * disable interrupt and turn off caches etc ... */ disable_interrupts(); /* * Turn off I-cache and invalidate it */ icache_disable(); invalidate_icache_all(); /* * turn off D-cache * dcache_disable() in turn flushes the d-cache and disables MMU */ dcache_disable(); invalidate_dcache_all(); return 0; }
int cleanup_before_linux (void) { /* * this function is called just before we call linux * it prepares the processor for linux * * we turn off caches etc ... */ disable_interrupts (); /* * this function is called just before we call linux * it prepares the processor for linux */ #ifdef CONFIG_BOARD_CLEANUP_BEFORE_LINUX board_cleanup_before_linux(); #endif /* turn off I/D-cache */ icache_disable(); dcache_disable(); /* flush I/D-cache */ cache_flush(); return 0; }
static inline void dcache_noop(void) { if (dcache_status()) { puts("WARNING: cache operations are not implemented!\n" "WARNING: disabling D-Cache now, you can re-enable it" "later with 'dcache on' command\n"); dcache_disable(); } }
int cleanup_before_linux(void) { unsigned int i; /* * this function is called just before we call linux * it prepares the processor for linux * * we turn off caches etc ... */ disable_interrupts(); #ifndef CONFIG_ICACHE_OFF /* turn off I/D-cache */ icache_disable(); icache_invalid(); asm("isb"); #endif #ifndef CONFIG_DCACHE_OFF dcache_disable(); asm("dsb"); #endif //#ifndef CONFIG_ICAHCE_OFF // /* invalidate I-cache */ // cache_flush(); //#else //#ifndef CONFIG_DCACHE_OFF // cache_flush(); //#endif //#endif //#ifndef CONFIG_L2_OFF // /* turn off L2 cache */ // l2_cache_disable(); // /* invalidate L2 cache also */ // invalidate_l2_cache(); //#endif #ifndef CONFIG_L2_OFF l2_cache_disable(); l2x0_clean_inv_all(); #endif i = 0; /* mem barrier to sync up things */ asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i)); /*#ifndef CONFIG_L2_OFF l2_cache_enable(); #endif */ asm("dsb"); asm("isb"); return 0; }
void kgdb_flush_cache_all(void) { if (dcache_status()) { dcache_disable(); dcache_enable(); } if (icache_status()) { icache_disable(); icache_enable(); } }
int board_init (void) { /* We have RAM, disable cache */ dcache_disable(); icache_disable(); gd->bd->bi_arch_number = MACH_TYPE_INNOKOM; gd->bd->bi_boot_params = 0xa0000100; gd->bd->bi_baudrate = CONFIG_BAUDRATE; return 0; }
int cleanup_before_linux(void) { /* * this function is called just before we call linux * it prepares the processor for linux * * we turn off caches etc ... */ #ifndef CONFIG_SPL_BUILD disable_interrupts(); #ifdef CONFIG_LCD { /* switch off LCD panel */ lcd_panel_disable(); /* disable LCD controller */ lcd_disable(); } #endif /* CONFIG_LCD */ #endif /* CONFIG_SPL_BUILD */ /* * Turn off I-cache and invalidate it */ icache_disable(); invalidate_icache_all(); /* * turn off D-cache * dcache_disable() in turn flushes the d-cache and disables MMU */ dcache_disable(); v7_outer_cache_disable(); /* * After D-cache is flushed and before it is disabled there may * be some new valid entries brought into the cache. We are sure * that these lines are not dirty and will not affect our execution. * (because unwinding the call-stack and setting a bit in CP15 SCTRL * is all we did during this. We have not pushed anything on to the * stack. Neither have we affected any static data) * So just invalidate the entire d-cache again to avoid coherency * problems for kernel */ invalidate_dcache_all(); /* * Some CPU need more cache attention before starting the kernel. */ cpu_cache_initialization(); return 0; }
//============================================================== unsigned test_w_l1cache(unsigned fill_value, unsigned modify_value) { unsigned *addr; unsigned size, err_addr, val; int i; // current dcache is disable // clear no-cache memory block addr = (unsigned*)no_cache_mem_start; size = (cache_size)/sizeof(unsigned); for(i=0; i<size; i++, addr++) *addr = fill_value; // asm("dmb"); // asm("isb"); // map cache-memory data to cache addr = (unsigned*)cache_mem_start; size = cache_size/CONFIG_SYS_CACHE_LINE_SIZE; dcache_enable(); // asm("dmb"); // asm("isb"); for(i=0; i<size; i++, addr+=CONFIG_SYS_CACHE_LINE_SIZE) val = *addr; // write to cache addr = (unsigned*)cache_mem_start; size = cache_size/sizeof(unsigned); for(i=0; i<size; i++, addr++){ *addr = modify_value; } dcache_flush(); dcache_clean(); dcache_disable(); dcache_invalid(); asm("mov r0, r0"); asm("mov r0, r0"); asm("mov r0, r0"); err_addr = 0; addr = (unsigned*)no_cache_mem_start; for(i=0; i<size; i++, addr++){ if(*addr != modify_value){ err_addr = (unsigned)addr; break; } } return err_addr; }
int jpeg_decode(void) { enable_mmu(); dcache_enable(); printf("mmu_enable\n"); LoadJpegFile((void *)VIDEO_DATA_BASE); dcache_disable(); stop_mmu(); return 0; }
int cleanup_before_linux(void) { unsigned int i; #ifdef CONFIG_CMD_IMX_DOWNLOAD_MODE extern void clear_mfgmode_mem(void); clear_mfgmode_mem(); #endif #ifdef CONFIG_VIDEO_MX5 ipu_disable_channel(MEM_BG_SYNC); ipu_uninit_channel(MEM_BG_SYNC); #endif /* * this function is called just before we call linux * it prepares the processor for linux * * we turn off caches etc ... */ disable_interrupts(); /* flush cache */ cache_flush(); /* turn off I/D-cache */ icache_disable(); /* invalidate D-cache */ dcache_disable(); #ifndef CONFIG_L2_OFF /* turn off L2 cache */ l2_cache_disable(); /* invalidate L2 cache also */ v7_flush_dcache_all(get_device_type()); #endif i = 0; /* mem barrier to sync up things */ asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i)); /* turn off MMU */ MMU_OFF(); #ifndef CONFIG_L2_OFF l2_cache_enable(); #endif return 0; }
int board_init (void) { /* We have RAM, disable cache */ dcache_disable(); icache_disable(); /* arch number of ConXS Board */ gd->bd->bi_arch_number = 776; /* adress of boot parameters */ gd->bd->bi_boot_params = 0xa000003c; return 0; }
int board_init(void) { /* We have RAM, disable cache */ dcache_disable(); icache_disable(); /* arch number of vpac270 */ gd->bd->bi_arch_number = MACH_TYPE_COLIBRI; /* adress of boot parameters */ gd->bd->bi_boot_params = 0xa0000100; return 0; }
int board_init (void) { /* We have RAM, disable cache */ dcache_disable(); icache_disable(); /* arch number of Lubbock-Board */ gd->bd->bi_arch_number = MACH_TYPE_LUBBOCK; /* adress of boot parameters */ gd->bd->bi_boot_params = 0xa0000100; return 0; }
/* * Miscelaneous platform dependent initialisations */ int board_init(void) { /* We have RAM, disable cache */ dcache_disable(); icache_disable(); /* memory and cpu-speed are setup before relocation */ /* so we do _nothing_ here */ /* adress of boot parameters */ gd->bd->bi_boot_params = 0xa0000100; return 0; }
/* * do_reset() * * Shell command to reset the board. */ void do_reset( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] ) { printf( "Resetting...\n" ); /* Disabe and invalidate cache */ icache_disable(); dcache_disable(); /* Jump to warm start (in RAM) */ _start_warm(); /* Should never get here */ while(1); }
void pxa_wakeup(void) { uint32_t rcsr; rcsr = readl(RCSR); writel(rcsr & (RCSR_GPR | RCSR_SMR | RCSR_WDR | RCSR_HWR), RCSR); /* Wakeup */ if (rcsr & RCSR_SMR) { writel(PSSR_PH, PSSR); pxa_dram_init(); icache_disable(); dcache_disable(); asm volatile("mov pc, %0"::"r"(readl(PSSR))); }
int cleanup_before_linux(void) { #ifdef CONFIG_BOOTSTAGE_REPORT bootstage_report(); #endif #ifdef CONFIG_BOOTSTAGE_STASH bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH, CONFIG_BOOTSTAGE_STASH_SIZE); #endif /* * this function is called just before we call linux * it prepares the processor for linux * * we turn off caches etc ... */ disable_interrupts(); #ifdef CONFIG_EXYNOS_LCD exynos_fimd_disable(); #endif /* * Turn off I-cache and invalidate it */ icache_disable(); invalidate_icache_all(); /* * turn off D-cache * dcache_disable() in turn flushes the d-cache and disables MMU */ dcache_disable(); v7_outer_cache_disable(); /* * After D-cache is flushed and before it is disabled there may * be some new valid entries brought into the cache. We are sure * that these lines are not dirty and will not affect our execution. * (because unwinding the call-stack and setting a bit in CP15 SCTRL * is all we did during this. We have not pushed anything on to the * stack. Neither have we affected any static data) * So just invalidate the entire d-cache again to avoid coherency * problems for kernel */ invalidate_dcache_all(); return 0; }
/* * cleanup_before_linux() is called just before we call linux * it prepares the processor for linux * * we disable interrupt and caches. */ int cleanup_before_linux(void) { disable_interrupts(); #ifdef CONFIG_MMU /* turn off I/D-cache */ icache_disable(); dcache_disable(); /* flush I/D-cache */ invalidate_icac(); invalidate_dcac(); #endif return 0; }