static struct android_display *
android_display_create(const struct native_event_handler *event_handler,
boolean use_sw)
{
struct android_display *adpy;
char value[PROPERTY_VALUE_MAX];
boolean force_sw;
/* check if SW renderer is forced */
if (property_get("debug.mesa.software", value, NULL))
force_sw = (atoi(value) != 0);
else
force_sw = debug_get_bool_option("EGL_SOFTWARE", FALSE);
if (force_sw)
use_sw = TRUE;
adpy = CALLOC_STRUCT(android_display);
if (!adpy)
return NULL;
adpy->event_handler = event_handler;
adpy->use_drm = !use_sw;
adpy->base.init_screen = android_display_init_screen;
adpy->base.destroy = android_display_destroy;
adpy->base.get_param = android_display_get_param;
adpy->base.get_configs = android_display_get_configs;
adpy->base.create_window_surface = android_display_create_window_surface;
adpy->base.buffer = &android_display_buffer;
return adpy;
}
struct brw_winsys_screen *
i965_drm_winsys_screen_create(int drmFD)
{
struct i965_libdrm_winsys *idws;
debug_printf("%s\n", __FUNCTION__);
idws = CALLOC_STRUCT(i965_libdrm_winsys);
if (!idws)
return NULL;
i965_libdrm_get_device_id(&idws->base.pci_id);
i965_libdrm_winsys_init_buffer_functions(idws);
idws->fd = drmFD;
idws->base.destroy = i965_libdrm_winsys_destroy;
idws->gem = drm_intel_bufmgr_gem_init(idws->fd, BRW_BATCH_SIZE);
drm_intel_bufmgr_gem_enable_reuse(idws->gem);
idws->send_cmd = !debug_get_bool_option("BRW_NO_HW", FALSE);
return &idws->base;
}
static void
init_logging(struct pipe_screen *screen)
{
static const char *log_prefix = "Mesa: ";
char host_log[1000];
/* Log Version to Host */
util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
"%s%s", log_prefix, svga_get_name(screen));
svga_host_log(host_log);
util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
"%s%s"
#ifdef MESA_GIT_SHA1
" (" MESA_GIT_SHA1 ")"
#endif
, log_prefix, PACKAGE_VERSION);
svga_host_log(host_log);
/* If the SVGA_EXTRA_LOGGING env var is set, log the process's command
* line (program name and arguments).
*/
if (debug_get_bool_option("SVGA_EXTRA_LOGGING", FALSE)) {
char cmdline[1000];
if (os_get_command_line(cmdline, sizeof(cmdline))) {
util_snprintf(host_log, sizeof(host_log) - strlen(log_prefix),
"%s%s", log_prefix, cmdline);
svga_host_log(host_log);
}
}
}
void radeon_drm_cs_emit_ioctl_oneshot(struct radeon_drm_cs *cs, struct radeon_cs_context *csc)
{
unsigned i;
if (drmCommandWriteRead(csc->fd, DRM_RADEON_CS,
&csc->cs, sizeof(struct drm_radeon_cs))) {
if (debug_get_bool_option("RADEON_DUMP_CS", FALSE)) {
unsigned i;
fprintf(stderr, "radeon: The kernel rejected CS, dumping...\n");
for (i = 0; i < csc->chunks[0].length_dw; i++) {
fprintf(stderr, "0x%08X\n", csc->buf[i]);
}
} else {
fprintf(stderr, "radeon: The kernel rejected CS, "
"see dmesg for more information.\n");
}
}
if (cs->trace_buf) {
radeon_dump_cs_on_lockup(cs, csc);
}
for (i = 0; i < csc->crelocs; i++)
p_atomic_dec(&csc->relocs_bo[i]->num_active_ioctls);
radeon_cs_context_cleanup(csc);
}
struct i915_winsys *
i915_sw_winsys_create()
{
struct i915_sw_winsys *isws;
unsigned int deviceID;
isws = CALLOC_STRUCT(i915_sw_winsys);
if (!isws)
return NULL;
i915_sw_get_device_id(&deviceID);
i915_sw_winsys_init_batchbuffer_functions(isws);
i915_sw_winsys_init_buffer_functions(isws);
i915_sw_winsys_init_fence_functions(isws);
isws->base.destroy = i915_sw_destroy;
isws->base.pci_id = deviceID;
isws->max_batch_size = 16 * 4096;
isws->dump_cmd = debug_get_bool_option("I915_DUMP_CMD", FALSE);
return &isws->base;
}
static struct native_display *
native_create_display(void *dpy, boolean use_sw)
{
struct wayland_display *display = NULL;
boolean own_dpy = FALSE;
use_sw = use_sw || debug_get_bool_option("EGL_SOFTWARE", FALSE);
if (dpy == NULL) {
dpy = wl_display_connect(NULL);
if (dpy == NULL)
return NULL;
own_dpy = TRUE;
}
if (use_sw) {
_eglLog(_EGL_INFO, "use software fallback");
display = wayland_create_shm_display((struct wl_display *) dpy,
wayland_event_handler);
} else {
display = wayland_create_drm_display((struct wl_display *) dpy,
wayland_event_handler);
}
if (!display)
return NULL;
display->base.get_param = wayland_display_get_param;
display->base.get_configs = wayland_display_get_configs;
display->base.create_window_surface = wayland_create_window_surface;
display->own_dpy = own_dpy;
return &display->base;
}
struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
{
struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
if (sscreen == NULL) {
return NULL;
}
/* Set functions first. */
sscreen->b.b.context_create = si_create_context;
sscreen->b.b.destroy = si_destroy_screen;
sscreen->b.b.get_param = si_get_param;
sscreen->b.b.get_shader_param = si_get_shader_param;
sscreen->b.b.is_format_supported = si_is_format_supported;
sscreen->b.b.resource_create = r600_resource_create_common;
if (!r600_common_screen_init(&sscreen->b, ws)) {
FREE(sscreen);
return NULL;
}
sscreen->b.has_cp_dma = true;
sscreen->b.has_streamout = HAVE_LLVM >= 0x0304;
if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
/* Create the auxiliary context. This must be done last. */
sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL);
return &sscreen->b.b;
}
void radeon_drm_cs_emit_ioctl_oneshot(void *job, int thread_index)
{
struct radeon_cs_context *csc = ((struct radeon_drm_cs*)job)->cst;
unsigned i;
int r;
r = drmCommandWriteRead(csc->fd, DRM_RADEON_CS,
&csc->cs, sizeof(struct drm_radeon_cs));
if (r) {
if (r == -ENOMEM)
fprintf(stderr, "radeon: Not enough memory for command submission.\n");
else if (debug_get_bool_option("RADEON_DUMP_CS", false)) {
unsigned i;
fprintf(stderr, "radeon: The kernel rejected CS, dumping...\n");
for (i = 0; i < csc->chunks[0].length_dw; i++) {
fprintf(stderr, "0x%08X\n", csc->buf[i]);
}
} else {
fprintf(stderr, "radeon: The kernel rejected CS, "
"see dmesg for more information (%i).\n", r);
}
}
for (i = 0; i < csc->num_relocs; i++)
p_atomic_dec(&csc->relocs_bo[i].bo->num_active_ioctls);
for (i = 0; i < csc->num_slab_buffers; i++)
p_atomic_dec(&csc->slab_buffers[i].bo->num_active_ioctls);
radeon_cs_context_cleanup(csc);
}
static int
llvmpipe_get_shader_param(struct pipe_screen *screen, unsigned shader, enum pipe_shader_cap param)
{
switch(shader)
{
case PIPE_SHADER_FRAGMENT:
switch (param) {
default:
return gallivm_get_shader_param(param);
}
case PIPE_SHADER_VERTEX:
case PIPE_SHADER_GEOMETRY:
switch (param) {
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
/* At this time, the draw module and llvmpipe driver only
* support vertex shader texture lookups when LLVM is enabled in
* the draw module.
*/
if (debug_get_bool_option("DRAW_USE_LLVM", TRUE))
return PIPE_MAX_SAMPLERS;
else
return 0;
default:
return draw_get_shader_param(shader, param);
}
default:
return 0;
}
}
struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
{
struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
if (!sscreen) {
return NULL;
}
/* Set functions first. */
sscreen->b.b.context_create = si_create_context;
sscreen->b.b.destroy = si_destroy_screen;
sscreen->b.b.get_param = si_get_param;
sscreen->b.b.get_shader_param = si_get_shader_param;
sscreen->b.b.is_format_supported = si_is_format_supported;
sscreen->b.b.resource_create = r600_resource_create_common;
si_init_screen_state_functions(sscreen);
if (!r600_common_screen_init(&sscreen->b, ws) ||
!si_init_gs_info(sscreen) ||
!si_init_shader_cache(sscreen)) {
FREE(sscreen);
return NULL;
}
if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", FALSE))
si_init_perfcounters(sscreen);
sscreen->b.has_cp_dma = true;
sscreen->b.has_streamout = true;
pipe_mutex_init(sscreen->shader_parts_mutex);
sscreen->use_monolithic_shaders =
HAVE_LLVM < 0x0308 ||
(sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
/* Create the auxiliary context. This must be done last. */
sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL, 0);
if (sscreen->b.debug_flags & DBG_TEST_DMA)
r600_test_dma(&sscreen->b);
return &sscreen->b.b;
}
void xmesa_set_driver( const struct xm_driver *templ )
{
driver = *templ;
stapi = driver.create_st_api();
xmesa_strict_invalidate =
debug_get_bool_option("XMESA_STRICT_INVALIDATE", FALSE);
}
struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
{
struct r600_screen *rscreen = CALLOC_STRUCT(r600_screen);
if (rscreen == NULL) {
return NULL;
}
ws->query_info(ws, &rscreen->b.info);
/* Set functions first. */
rscreen->b.b.context_create = r600_create_context;
rscreen->b.b.destroy = r600_destroy_screen;
rscreen->b.b.get_name = r600_get_name;
rscreen->b.b.get_vendor = r600_get_vendor;
rscreen->b.b.get_param = r600_get_param;
rscreen->b.b.get_shader_param = r600_get_shader_param;
rscreen->b.b.get_paramf = r600_get_paramf;
rscreen->b.b.get_compute_param = r600_get_compute_param;
rscreen->b.b.get_timestamp = r600_get_timestamp;
rscreen->b.b.is_format_supported = si_is_format_supported;
if (rscreen->b.info.has_uvd) {
rscreen->b.b.get_video_param = ruvd_get_video_param;
rscreen->b.b.is_video_format_supported = ruvd_is_format_supported;
} else {
rscreen->b.b.get_video_param = r600_get_video_param;
rscreen->b.b.is_video_format_supported = vl_video_buffer_is_format_supported;
}
r600_init_screen_resource_functions(&rscreen->b.b);
if (!r600_common_screen_init(&rscreen->b, ws)) {
FREE(rscreen);
return NULL;
}
if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
#if R600_TRACE_CS
rscreen->cs_count = 0;
if (rscreen->info.drm_minor >= 28) {
rscreen->trace_bo = (struct r600_resource*)pipe_buffer_create(&rscreen->screen,
PIPE_BIND_CUSTOM,
PIPE_USAGE_STAGING,
4096);
if (rscreen->trace_bo) {
rscreen->trace_ptr = rscreen->ws->buffer_map(rscreen->trace_bo->cs_buf, NULL,
PIPE_TRANSFER_UNSYNCHRONIZED);
}
}
#endif
/* Create the auxiliary context. This must be done last. */
rscreen->b.aux_context = rscreen->b.b.context_create(&rscreen->b.b, NULL);
return &rscreen->b.b;
}
/* Create a pipe_context. */
struct pipe_context* radeon_create_context(struct drm_api* api,
struct pipe_screen* screen)
{
if (debug_get_bool_option("RADEON_SOFTPIPE", FALSE)) {
return radeon_create_softpipe(screen->winsys);
} else {
return r300_create_context(screen,
(struct r300_winsys*)screen->winsys);
}
}
/**
* Create new lp_rasterizer. If num_threads is zero, don't create any
* new threads, do rendering synchronously.
* \param num_threads number of rasterizer threads to create
*/
struct lp_rasterizer *
lp_rast_create( unsigned num_threads )
{
struct lp_rasterizer *rast;
unsigned i;
rast = CALLOC_STRUCT(lp_rasterizer);
if (!rast) {
goto no_rast;
}
rast->full_scenes = lp_scene_queue_create();
if (!rast->full_scenes) {
goto no_full_scenes;
}
for (i = 0; i < MAX2(1, num_threads); i++) {
struct lp_rasterizer_task *task = &rast->tasks[i];
task->rast = rast;
task->thread_index = i;
task->thread_data.cache = align_malloc(sizeof(struct lp_build_format_cache),
16);
if (!task->thread_data.cache) {
goto no_thread_data_cache;
}
}
rast->num_threads = num_threads;
rast->no_rast = debug_get_bool_option("LP_NO_RAST", FALSE);
create_rast_threads(rast);
/* for synchronizing rasterization threads */
if (rast->num_threads > 0) {
pipe_barrier_init( &rast->barrier, rast->num_threads );
}
memset(lp_dummy_tile, 0, sizeof lp_dummy_tile);
return rast;
no_thread_data_cache:
for (i = 0; i < MAX2(1, rast->num_threads); i++) {
if (rast->tasks[i].thread_data.cache) {
align_free(rast->tasks[i].thread_data.cache);
}
}
lp_scene_queue_destroy(rast->full_scenes);
no_full_scenes:
FREE(rast);
no_rast:
return NULL;
}
void _debug_assert_fail(const char *expr,
const char *file,
unsigned line,
const char *function)
{
_debug_printf("%s:%u:%s: Assertion `%s' failed.\n", file, line, function, expr);
if (debug_get_bool_option("GALLIUM_ABORT_ON_ASSERT", TRUE))
os_abort();
else
_debug_printf("continuing...\n");
}
/** Internal debug function. Should be available to final users. */
void
pp_debug(const char *fmt, ...)
{
va_list ap;
if (!debug_get_bool_option("PP_DEBUG", FALSE))
return;
va_start(ap, fmt);
_debug_vprintf(fmt, ap);
va_end(ap);
}
static struct llvmpipe_displaytarget *
xm_displaytarget_create(struct llvmpipe_winsys *winsys,
enum pipe_format format,
unsigned width, unsigned height,
unsigned alignment,
unsigned *stride)
{
struct xm_displaytarget *xm_dt = CALLOC_STRUCT(xm_displaytarget);
unsigned nblocksx, nblocksy, size;
xm_dt = CALLOC_STRUCT(xm_displaytarget);
if(!xm_dt)
goto no_xm_dt;
xm_dt->format = format;
xm_dt->width = width;
xm_dt->height = height;
pf_get_block(format, &xm_dt->block);
nblocksx = pf_get_nblocksx(&xm_dt->block, width);
nblocksy = pf_get_nblocksy(&xm_dt->block, height);
xm_dt->stride = align(nblocksx * xm_dt->block.size, alignment);
size = xm_dt->stride * nblocksy;
#ifdef USE_XSHM
if (!debug_get_bool_option("XLIB_NO_SHM", FALSE))
{
xm_dt->shminfo.shmid = -1;
xm_dt->shminfo.shmaddr = (char *) -1;
xm_dt->shm = TRUE;
xm_dt->data = alloc_shm(xm_dt, size);
if(!xm_dt->data)
goto no_data;
}
#endif
if(!xm_dt->data) {
xm_dt->data = align_malloc(size, alignment);
if(!xm_dt->data)
goto no_data;
}
*stride = xm_dt->stride;
return (struct llvmpipe_displaytarget *)xm_dt;
no_data:
FREE(xm_dt);
no_xm_dt:
return NULL;
}
struct pipe_context *
i915_create_context(struct pipe_screen *screen)
{
struct i915_context *i915;
i915 = CALLOC_STRUCT(i915_context);
if (i915 == NULL)
return NULL;
i915->iws = i915_screen(screen)->iws;
i915->base.winsys = NULL;
i915->base.screen = screen;
i915->base.destroy = i915_destroy;
i915->base.clear = i915_clear;
i915->base.draw_arrays = i915_draw_arrays;
i915->base.draw_elements = i915_draw_elements;
i915->base.draw_range_elements = i915_draw_range_elements;
i915->base.is_texture_referenced = i915_is_texture_referenced;
i915->base.is_buffer_referenced = i915_is_buffer_referenced;
/*
* Create drawing context and plug our rendering stage into it.
*/
i915->draw = draw_create();
assert(i915->draw);
if (!debug_get_bool_option("I915_NO_VBUF", FALSE)) {
draw_set_rasterize_stage(i915->draw, i915_draw_vbuf_stage(i915));
} else {
draw_set_rasterize_stage(i915->draw, i915_draw_render_stage(i915));
}
i915_init_surface_functions(i915);
i915_init_state_functions(i915);
i915_init_flush_functions(i915);
draw_install_aaline_stage(i915->draw, &i915->base);
draw_install_aapoint_stage(i915->draw, &i915->base);
i915->dirty = ~0;
i915->hardware_dirty = ~0;
/* Batch stream debugging is a bit hacked up at the moment:
*/
i915->batch = i915->iws->batchbuffer_create(i915->iws);
return &i915->base;
}
/* Create a pipe_screen. */
struct pipe_screen* radeon_create_screen(struct drm_api* api,
int drmFB,
struct drm_create_screen_arg *arg)
{
struct radeon_winsys* winsys = radeon_pipe_winsys(drmFB);
if (debug_get_bool_option("RADEON_SOFTPIPE", FALSE)) {
return softpipe_create_screen((struct pipe_winsys*)winsys);
} else {
struct r300_winsys* r300 = radeon_create_r300_winsys(drmFB, winsys);
FREE(winsys);
return r300_create_screen(r300);
}
}
static struct pipe_buffer *
xm_surface_buffer_create(struct pipe_winsys *winsys,
unsigned width, unsigned height,
enum pipe_format format,
unsigned usage,
unsigned tex_usage,
unsigned *stride)
{
const unsigned alignment = 64;
struct pipe_format_block block;
unsigned nblocksx, nblocksy, size;
pf_get_block(format, &block);
nblocksx = pf_get_nblocksx(&block, width);
nblocksy = pf_get_nblocksy(&block, height);
*stride = align(nblocksx * block.size, alignment);
size = *stride * nblocksy;
#ifdef USE_XSHM
if (!debug_get_bool_option("XLIB_NO_SHM", FALSE))
{
struct xm_buffer *buffer = CALLOC_STRUCT(xm_buffer);
pipe_reference_init(&buffer->base.reference, 1);
buffer->base.alignment = alignment;
buffer->base.usage = usage;
buffer->base.size = size;
buffer->userBuffer = FALSE;
buffer->shminfo.shmid = -1;
buffer->shminfo.shmaddr = (char *) -1;
buffer->shm = TRUE;
buffer->data = alloc_shm(buffer, size);
if (!buffer->data)
goto out;
return &buffer->base;
out:
if (buffer)
FREE(buffer);
}
#endif
return winsys->buffer_create(winsys, alignment,
usage,
size);
}
static void
nvfx_miptree_choose_format(struct nvfx_miptree *mt)
{
struct pipe_resource *pt = &mt->base.base;
unsigned uniform_pitch = 0;
static int no_swizzle = -1;
if(no_swizzle < 0)
no_swizzle = debug_get_bool_option("NV40_NO_SWIZZLE", FALSE); /* this will break things on nv30 */
if (!util_is_power_of_two(pt->width0) ||
!util_is_power_of_two(pt->height0) ||
!util_is_power_of_two(pt->depth0) ||
(!nvfx_screen(pt->screen)->is_nv4x && pt->target == PIPE_TEXTURE_RECT)
)
uniform_pitch = 1;
if (
(pt->bind & (PIPE_BIND_SCANOUT | PIPE_BIND_DISPLAY_TARGET))
|| (pt->usage & PIPE_USAGE_DYNAMIC) || (pt->usage & PIPE_USAGE_STAGING)
|| util_format_is_compressed(pt->format)
|| no_swizzle
)
mt->base.base.flags |= NVFX_RESOURCE_FLAG_LINEAR;
/* non compressed formats with uniform pitch must be linear, and vice versa */
if(!util_format_is_s3tc(pt->format)
&& (uniform_pitch || mt->base.base.flags & NVFX_RESOURCE_FLAG_LINEAR))
{
mt->base.base.flags |= NVFX_RESOURCE_FLAG_LINEAR;
uniform_pitch = 1;
}
if(uniform_pitch)
{
mt->linear_pitch = util_format_get_stride(pt->format, pt->width0);
// TODO: this is only a constraint for rendering and not sampling, apparently
// we may also want this unconditionally
if(pt->bind & (PIPE_BIND_SAMPLER_VIEW |
PIPE_BIND_DEPTH_STENCIL |
PIPE_BIND_RENDER_TARGET |
PIPE_BIND_DISPLAY_TARGET |
PIPE_BIND_SCANOUT))
mt->linear_pitch = align(mt->linear_pitch, 64);
}
else
mt->linear_pitch = 0;
}
static unsigned
nvfx_screen_get_vertex_buffer_flags(struct nvfx_screen* screen)
{
int vram_hack_default = 0;
int vram_hack;
// TODO: this is a bit of a guess; also add other cards that may need this hack.
// It may also depend on the specific card or the AGP/PCIe chipset.
if(screen->base.device->chipset == 0x47 /* G70 */
|| screen->base.device->chipset == 0x49 /* G71 */
|| screen->base.device->chipset == 0x46 /* G72 */
)
vram_hack_default = 1;
vram_hack = debug_get_bool_option("NOUVEAU_VTXIDX_IN_VRAM", vram_hack_default);
return vram_hack ? NOUVEAU_BO_VRAM : NOUVEAU_BO_GART;
}
boolean svga_init_swtnl( struct svga_context *svga )
{
svga->swtnl.backend = svga_vbuf_render_create(svga);
if(!svga->swtnl.backend)
goto fail;
/*
* Create drawing context and plug our rendering stage into it.
*/
svga->swtnl.draw = draw_create(&svga->pipe);
if (svga->swtnl.draw == NULL)
goto fail;
draw_set_rasterize_stage(svga->swtnl.draw,
draw_vbuf_stage( svga->swtnl.draw, svga->swtnl.backend ));
draw_set_render(svga->swtnl.draw, svga->swtnl.backend);
svga->blitter = util_blitter_create(&svga->pipe);
if (!svga->blitter)
goto fail;
/* must be done before installing Draw stages */
util_blitter_cache_all_shaders(svga->blitter);
draw_install_aaline_stage(svga->swtnl.draw, &svga->pipe);
draw_install_aapoint_stage(svga->swtnl.draw, &svga->pipe);
draw_install_pstipple_stage(svga->swtnl.draw, &svga->pipe);
if (debug_get_bool_option("SVGA_SWTNL_FSE", FALSE))
draw_set_driver_clipping(svga->swtnl.draw, TRUE, TRUE, TRUE);
return TRUE;
fail:
if (svga->blitter)
util_blitter_destroy(svga->blitter);
if (svga->swtnl.backend)
svga->swtnl.backend->destroy( svga->swtnl.backend );
if (svga->swtnl.draw)
draw_destroy( svga->swtnl.draw );
return FALSE;
}
static boolean
debug_get_option_should_print(void)
{
static boolean first = TRUE;
static boolean value = FALSE;
if (!first)
return value;
/* Oh hey this will call into this function,
* but its cool since we set first to false
*/
first = FALSE;
value = debug_get_bool_option("GALLIUM_PRINT_OPTIONS", FALSE);
/* XXX should we print this option? Currently it wont */
return value;
}
static struct native_display *
native_create_display(void *dpy, boolean use_sw)
{
struct native_display *ndpy = NULL;
boolean force_sw;
force_sw = debug_get_bool_option("EGL_SOFTWARE", FALSE);
if (force_sw || use_sw) {
_eglLog(_EGL_INFO, "use software fallback");
ndpy = x11_create_ximage_display((Display *) dpy, x11_event_handler);
}
else {
ndpy = x11_create_dri2_display((Display *) dpy, x11_event_handler);
}
return ndpy;
}
static boolean
draw_get_option_use_llvm(void)
{
static boolean first = TRUE;
static boolean value;
if (first) {
first = FALSE;
value = debug_get_bool_option("DRAW_USE_LLVM", TRUE);
#ifdef PIPE_ARCH_X86
util_cpu_detect();
/* require SSE2 due to LLVM PR6960. */
if (!util_cpu_caps.has_sse2)
value = FALSE;
#endif
}
return value;
}
/**
* Create new lp_rasterizer. If num_threads is zero, don't create any
* new threads, do rendering synchronously.
* \param num_threads number of rasterizer threads to create
*/
struct lp_rasterizer *
lp_rast_create( unsigned num_threads )
{
struct lp_rasterizer *rast;
unsigned i;
rast = CALLOC_STRUCT(lp_rasterizer);
if (!rast) {
goto no_rast;
}
rast->full_scenes = lp_scene_queue_create();
if (!rast->full_scenes) {
goto no_full_scenes;
}
for (i = 0; i < Elements(rast->tasks); i++) {
struct lp_rasterizer_task *task = &rast->tasks[i];
task->rast = rast;
task->thread_index = i;
}
rast->num_threads = num_threads;
rast->no_rast = debug_get_bool_option("LP_NO_RAST", FALSE);
create_rast_threads(rast);
/* for synchronizing rasterization threads */
pipe_barrier_init( &rast->barrier, rast->num_threads );
memset(lp_swizzled_cbuf, 0, sizeof lp_swizzled_cbuf);
memset(lp_dummy_tile, 0, sizeof lp_dummy_tile);
return rast;
no_full_scenes:
FREE(rast);
no_rast:
return NULL;
}
static struct pipe_screen *
create_screen(int fd)
{
struct brw_winsys_screen *bws;
struct pipe_screen *screen;
bws = i965_drm_winsys_screen_create(fd);
if (!bws)
return NULL;
screen = brw_screen_create(bws);
if (!screen)
return NULL;
if (debug_get_bool_option("BRW_SOFTPIPE", FALSE))
screen = sw_screen_wrap(screen);
screen = debug_screen_wrap(screen);
return screen;
}
static struct pipe_screen *
intel_drm_create_screen(struct drm_api *api, int drmFD,
struct drm_create_screen_arg *arg)
{
struct intel_drm_winsys *idws;
unsigned int deviceID;
if (arg != NULL) {
switch(arg->mode) {
case DRM_CREATE_NORMAL:
break;
default:
return NULL;
}
}
idws = CALLOC_STRUCT(intel_drm_winsys);
if (!idws)
return NULL;
intel_drm_get_device_id(&deviceID);
intel_drm_winsys_init_batchbuffer_functions(idws);
intel_drm_winsys_init_buffer_functions(idws);
intel_drm_winsys_init_fence_functions(idws);
idws->fd = drmFD;
idws->id = deviceID;
idws->max_batch_size = 16 * 4096;
idws->base.destroy = intel_drm_winsys_destroy;
idws->pools.gem = drm_intel_bufmgr_gem_init(idws->fd, idws->max_batch_size);
drm_intel_bufmgr_gem_enable_reuse(idws->pools.gem);
idws->dump_cmd = debug_get_bool_option("INTEL_DUMP_CMD", FALSE);
return i915_create_screen(&idws->base, deviceID);
}
/* Helper function to do the ioctls needed for setup and init. */
static boolean do_winsys_init(struct radeon_drm_winsys *ws)
{
struct drm_radeon_gem_info gem_info;
int retval;
drmVersionPtr version;
memset(&gem_info, 0, sizeof(gem_info));
/* We do things in a specific order here.
*
* DRM version first. We need to be sure we're running on a KMS chipset.
* This is also for some features.
*
* Then, the PCI ID. This is essential and should return usable numbers
* for all Radeons. If this fails, we probably got handed an FD for some
* non-Radeon card.
*
* The GEM info is actually bogus on the kernel side, as well as our side
* (see radeon_gem_info_ioctl in radeon_gem.c) but that's alright because
* we don't actually use the info for anything yet.
*
* The GB and Z pipe requests should always succeed, but they might not
* return sensical values for all chipsets, but that's alright because
* the pipe drivers already know that.
*/
/* Get DRM version. */
version = drmGetVersion(ws->fd);
if (version->version_major != 2 ||
version->version_minor < 3) {
fprintf(stderr, "%s: DRM version is %d.%d.%d but this driver is "
"only compatible with 2.3.x (kernel 2.6.34) or later.\n",
__FUNCTION__,
version->version_major,
version->version_minor,
version->version_patchlevel);
drmFreeVersion(version);
return FALSE;
}
ws->info.drm_major = version->version_major;
ws->info.drm_minor = version->version_minor;
ws->info.drm_patchlevel = version->version_patchlevel;
drmFreeVersion(version);
/* Get PCI ID. */
if (!radeon_get_drm_value(ws->fd, RADEON_INFO_DEVICE_ID, "PCI ID",
&ws->info.pci_id))
return FALSE;
/* Check PCI ID. */
switch (ws->info.pci_id) {
#define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R300; break;
#include "pci_ids/r300_pci_ids.h"
#undef CHIPSET
#define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_R600; break;
#include "pci_ids/r600_pci_ids.h"
#undef CHIPSET
#define CHIPSET(pci_id, name, cfamily) case pci_id: ws->info.family = CHIP_##cfamily; ws->gen = DRV_SI; break;
#include "pci_ids/radeonsi_pci_ids.h"
#undef CHIPSET
default:
fprintf(stderr, "radeon: Invalid PCI ID.\n");
return FALSE;
}
switch (ws->info.family) {
default:
case CHIP_UNKNOWN:
fprintf(stderr, "radeon: Unknown family.\n");
return FALSE;
case CHIP_R300:
case CHIP_R350:
case CHIP_RV350:
case CHIP_RV370:
case CHIP_RV380:
case CHIP_RS400:
case CHIP_RC410:
case CHIP_RS480:
ws->info.chip_class = R300;
break;
case CHIP_R420: /* R4xx-based cores. */
case CHIP_R423:
case CHIP_R430:
case CHIP_R480:
case CHIP_R481:
case CHIP_RV410:
case CHIP_RS600:
case CHIP_RS690:
case CHIP_RS740:
ws->info.chip_class = R400;
break;
case CHIP_RV515: /* R5xx-based cores. */
case CHIP_R520:
case CHIP_RV530:
case CHIP_R580:
case CHIP_RV560:
case CHIP_RV570:
ws->info.chip_class = R500;
break;
case CHIP_R600:
case CHIP_RV610:
case CHIP_RV630:
case CHIP_RV670:
case CHIP_RV620:
case CHIP_RV635:
case CHIP_RS780:
case CHIP_RS880:
ws->info.chip_class = R600;
break;
case CHIP_RV770:
case CHIP_RV730:
case CHIP_RV710:
case CHIP_RV740:
ws->info.chip_class = R700;
break;
case CHIP_CEDAR:
case CHIP_REDWOOD:
case CHIP_JUNIPER:
case CHIP_CYPRESS:
case CHIP_HEMLOCK:
case CHIP_PALM:
case CHIP_SUMO:
case CHIP_SUMO2:
case CHIP_BARTS:
case CHIP_TURKS:
case CHIP_CAICOS:
ws->info.chip_class = EVERGREEN;
break;
case CHIP_CAYMAN:
case CHIP_ARUBA:
ws->info.chip_class = CAYMAN;
break;
case CHIP_TAHITI:
case CHIP_PITCAIRN:
case CHIP_VERDE:
case CHIP_OLAND:
case CHIP_HAINAN:
ws->info.chip_class = SI;
break;
case CHIP_BONAIRE:
case CHIP_KAVERI:
case CHIP_KABINI:
case CHIP_HAWAII:
case CHIP_MULLINS:
ws->info.chip_class = CIK;
break;
}
/* Check for dma */
ws->info.r600_has_dma = FALSE;
/* DMA is disabled on R700. There is IB corruption and hangs. */
if (ws->info.chip_class >= EVERGREEN && ws->info.drm_minor >= 27) {
ws->info.r600_has_dma = TRUE;
}
/* Check for UVD and VCE */
ws->info.has_uvd = FALSE;
ws->info.vce_fw_version = 0x00000000;
if (ws->info.drm_minor >= 32) {
uint32_t value = RADEON_CS_RING_UVD;
if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
"UVD Ring working", &value))
ws->info.has_uvd = value;
value = RADEON_CS_RING_VCE;
if (radeon_get_drm_value(ws->fd, RADEON_INFO_RING_WORKING,
NULL, &value) && value) {
if (radeon_get_drm_value(ws->fd, RADEON_INFO_VCE_FW_VERSION,
"VCE FW version", &value))
ws->info.vce_fw_version = value;
}
}
/* Check for userptr support. */
{
struct drm_radeon_gem_userptr args = {0};
/* If the ioctl doesn't exist, -EINVAL is returned.
*
* If the ioctl exists, it should return -EACCES
* if RADEON_GEM_USERPTR_READONLY or RADEON_GEM_USERPTR_REGISTER
* aren't set.
*/
ws->info.has_userptr =
drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_USERPTR,
&args, sizeof(args)) == -EACCES;
}
/* Get GEM info. */
retval = drmCommandWriteRead(ws->fd, DRM_RADEON_GEM_INFO,
&gem_info, sizeof(gem_info));
if (retval) {
fprintf(stderr, "radeon: Failed to get MM info, error number %d\n",
retval);
return FALSE;
}
ws->info.gart_size = gem_info.gart_size;
ws->info.vram_size = gem_info.vram_size;
/* Get max clock frequency info and convert it to MHz */
radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SCLK, NULL,
&ws->info.max_sclk);
ws->info.max_sclk /= 1000;
radeon_get_drm_value(ws->fd, RADEON_INFO_SI_BACKEND_ENABLED_MASK, NULL,
&ws->info.si_backend_enabled_mask);
ws->num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
/* Generation-specific queries. */
if (ws->gen == DRV_R300) {
if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_GB_PIPES,
"GB pipe count",
&ws->info.r300_num_gb_pipes))
return FALSE;
if (!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_Z_PIPES,
"Z pipe count",
&ws->info.r300_num_z_pipes))
return FALSE;
}
else if (ws->gen >= DRV_R600) {
if (ws->info.drm_minor >= 9 &&
!radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_BACKENDS,
"num backends",
&ws->info.r600_num_backends))
return FALSE;
/* get the GPU counter frequency, failure is not fatal */
radeon_get_drm_value(ws->fd, RADEON_INFO_CLOCK_CRYSTAL_FREQ, NULL,
&ws->info.r600_clock_crystal_freq);
radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
&ws->info.r600_tiling_config);
if (ws->info.drm_minor >= 11) {
radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
&ws->info.r600_num_tile_pipes);
if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL,
&ws->info.r600_backend_map))
ws->info.r600_backend_map_valid = TRUE;
}
ws->info.r600_virtual_address = FALSE;
if (ws->info.drm_minor >= 13) {
uint32_t ib_vm_max_size;
ws->info.r600_virtual_address = TRUE;
if (!radeon_get_drm_value(ws->fd, RADEON_INFO_VA_START, NULL,
&ws->va_start))
ws->info.r600_virtual_address = FALSE;
if (!radeon_get_drm_value(ws->fd, RADEON_INFO_IB_VM_MAX_SIZE, NULL,
&ib_vm_max_size))
ws->info.r600_virtual_address = FALSE;
radeon_get_drm_value(ws->fd, RADEON_INFO_VA_UNMAP_WORKING, NULL,
&ws->va_unmap_working);
}
if (ws->gen == DRV_R600 && !debug_get_bool_option("RADEON_VA", FALSE))
ws->info.r600_virtual_address = FALSE;
}
/* Get max pipes, this is only needed for compute shaders. All evergreen+
* chips have at least 2 pipes, so we use 2 as a default. */
ws->info.r600_max_pipes = 2;
radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_PIPES, NULL,
&ws->info.r600_max_pipes);
/* All GPUs have at least one compute unit */
ws->info.max_compute_units = 1;
radeon_get_drm_value(ws->fd, RADEON_INFO_ACTIVE_CU_COUNT, NULL,
&ws->info.max_compute_units);
radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SE, NULL,
&ws->info.max_se);
if (!ws->info.max_se) {
switch (ws->info.family) {
default:
ws->info.max_se = 1;
break;
case CHIP_CYPRESS:
case CHIP_HEMLOCK:
case CHIP_BARTS:
case CHIP_CAYMAN:
case CHIP_TAHITI:
case CHIP_PITCAIRN:
case CHIP_BONAIRE:
ws->info.max_se = 2;
break;
case CHIP_HAWAII:
ws->info.max_se = 4;
break;
}
}
radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SH_PER_SE, NULL,
&ws->info.max_sh_per_se);
radeon_get_drm_value(ws->fd, RADEON_INFO_ACCEL_WORKING2, NULL,
&ws->accel_working2);
if (ws->info.family == CHIP_HAWAII && ws->accel_working2 < 2) {
fprintf(stderr, "radeon: GPU acceleration for Hawaii disabled, "
"returned accel_working2 value %u is smaller than 2. "
"Please install a newer kernel.\n",
ws->accel_working2);
return FALSE;
}
if (radeon_get_drm_value(ws->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, NULL,
ws->info.si_tile_mode_array)) {
ws->info.si_tile_mode_array_valid = TRUE;
}
if (radeon_get_drm_value(ws->fd, RADEON_INFO_CIK_MACROTILE_MODE_ARRAY, NULL,
ws->info.cik_macrotile_mode_array)) {
ws->info.cik_macrotile_mode_array_valid = TRUE;
}
return TRUE;
}
