/* \brief Start RC120M, switch main clock to RC120M.
*/
static void local_set_main_clock_to_rc120m(void)
{
// Start the 120MHz internal RCosc (RC120M) clock
scif_start_rc120M();
#if UC3D
// Set one wait-state (WS) for flash controller. 0 WS access is up to 30MHz for HSB/CPU clock.
// As we want to have 48MHz on HSB/CPU clock, we need to set 1 WS on flash controller.
flashcdw_set_wait_state(1);
#else
// Since our target is to set the CPU&HSB frequency domains to 30MHz, set the
// appropriate wait-state and speed read mode on the flash controller.
flashcdw_set_flash_waitstate_and_readmode(EXAMPLE_CPUCLK_HZ);
#endif
// Set the CPU clock domain to 30MHz (by applying a division ratio = 4).
pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_CPU, PM_CKSEL_DIVRATIO_4);
// Set the PBA clock domain to 30MHz (by applying a division ratio = 4).
pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBA, PM_CKSEL_DIVRATIO_4);
// Set the PBB clock domain to 30MHz (by applying a division ratio = 4).
pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBB, PM_CKSEL_DIVRATIO_4);
// Set the main clock source to be the RC120M.
pm_set_mclk_source(PM_CLK_SRC_RC120M);
}
void flashcdw_set_flash_waitstate_and_readmode(unsigned long cpu_f_hz)
{
if (cpu_f_hz > AVR32_FLASHCDW_FWS_0_MAX_FREQ) { // > 15MHz
if (cpu_f_hz <= AVR32_FLASHCDW_FWS_1_MAX_FREQ) { // <= 30MHz
// Set a wait-state, disable the high-speed read mode.
flashcdw_set_wait_state(1);
flashcdw_issue_command(AVR32_FLASHCDW_FCMD_CMD_HSDIS, -1);
} else {
// Set a wait-state, enable the high-speed read mode.
flashcdw_set_wait_state(1);
flashcdw_issue_command(AVR32_FLASHCDW_FCMD_CMD_HSEN, -1);
}
} else { // <= 15MHz
// No wait-state, disable the high-speed read mode
flashcdw_set_wait_state(0);
flashcdw_issue_command(AVR32_FLASHCDW_FCMD_CMD_HSDIS, -1);
}
}
/* \brief Start PLL0, switch main clock to PLL0 output.
*
*
*/
static void local_start_highfreq_clock(void)
{
#if BOARD == STK600_RCUC3L0 || BOARD == UC3L_EK
scif_dfll_openloop_conf_t dfllconfig = {EXAMPLE_DFLL_FINE_FDFLL96, EXAMPLE_DFLL_COARSE_FDFLL96};
// Configure and start the DFLL0 in open loop mode to generate a frequency of 96MHz.
scif_dfll0_openloop_start(&dfllconfig);
// Since our target is to set the CPU&HSB frequency domains to 48MHz, we must
// set one wait-state and enable the High-speed read mode on the flash controller.
flashcdw_set_flash_waitstate_and_readmode(EXAMPLE_CPUCLK_HZ);
// Set the CPU clock domain to 48MHz (by applying a division ratio = 2).
pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_CPU, PM_CKSEL_DIVRATIO_2);
// Set the PBA clock domain to 24MHz (by applying a division ratio = 4).
pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBA, PM_CKSEL_DIVRATIO_4);
// Set the PBB clock domain to 48MHz (by applying a division ratio = 2).
pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBB, PM_CKSEL_DIVRATIO_2);
// Set the main clock source to be DFLL0.
pm_set_mclk_source(PM_CLK_SRC_DFLL0);
#elif BOARD == UC3C_EK || BOARD == STK600_RCUC3D
scif_pll_opt_t opt;
// Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency.
scif_configure_osc_crystalmode(SCIF_OSC0, FOSC0);
// Enable the OSC0
scif_enable_osc(SCIF_OSC0, OSC0_STARTUP, true);
// Set the main clock source as being OSC0.
pm_set_mclk_source(PM_CLK_SRC_OSC0);
opt.osc = SCIF_OSC0; // Sel Osc0 or Osc1
opt.lockcount = 16; // lockcount in main clock for the PLL wait lock
opt.div = 1; // DIV=1 in the formula
opt.mul = 5; // MUL=6 in the formula
opt.pll_div2 = 1; // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
opt.pll_wbwdisable = 0; //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
opt.pll_freq = 1; // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
scif_pll_setup(SCIF_PLL0, &opt); // lockcount in main clock for the PLL wait lock
/* Enable PLL0 */
scif_pll_enable(SCIF_PLL0);
/* Wait for PLL0 locked */
scif_wait_for_pll_locked(SCIF_PLL0) ;
/* Divide PBA clock by 2 from main clock (PBA clock = 48MHz/2 = 24MHz).
Peripheral Bus A clock divisor enable = 1
Peripheral Bus A select = 0
Peripheral Bus B clock divisor enable = 0
Peripheral Bus B select = 0
High Speed Bus clock divisor enable = 0
High Speed Bus select = 0
*/
pm_set_clk_domain_div(PM_CLK_DOMAIN_2, (pm_divratio_t) 0); // PBA
// Set one wait-state (WS) for flash controller. 0 WS access is up to 30MHz for HSB/CPU clock.
// As we want to have 48MHz on HSB/CPU clock, we need to set 1 WS on flash controller.
#if UC3D
flashcdw_set_wait_state(1);
#else
flashc_set_wait_state(1);
#endif
// Set the main clock source as being PLL0.
pm_set_mclk_source(PM_CLK_SRC_PLL0);
#else
volatile avr32_pm_t* pm = &AVR32_PM;
/* \note All calculations here suppose that the Osc0 frequency is 12MHz. */
pm_switch_to_osc0(pm, FOSC0, OSC0_STARTUP); // Switch main clock to Osc0.
/* Setup PLL0 on Osc0, mul=7 ,no divisor, lockcount=16, ie. 12Mhzx8 = 96MHz output */
/*void pm_pll_setup(volatile avr32_pm_t* pm,
unsigned int pll,
unsigned int mul,
unsigned int div,
unsigned int osc,
unsigned int lockcount) {
*/
pm_pll_setup(pm,
0, // use PLL0
7, // MUL=7 in the formula
1, // DIV=1 in the formula
0, // Sel Osc0/PLL0 or Osc1/PLL1
16); // lockcount in main clock for the PLL wait lock
/*
This function will set a PLL option.
*pm Base address of the Power Manager (i.e. &AVR32_PM)
pll PLL number 0
pll_freq Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
*/
/* PLL output VCO frequency is 96MHz. We divide it by 2 with the pll_div2=1. This enable to get later main clock to 48MHz */
pm_pll_set_option(pm, 0, 1, 1, 0);
/* Enable PLL0 */
/*
void pm_pll_enable(volatile avr32_pm_t* pm,
unsigned int pll) {
*/
pm_pll_enable(pm,0);
/* Wait for PLL0 locked */
pm_wait_for_pll0_locked(pm) ;
/* Divide PBA clock by 2 from main clock (PBA clock = 48MHz/2 = 24MHz).
Peripheral Bus A clock divisor enable = 1
Peripheral Bus A select = 0
Peripheral Bus B clock divisor enable = 0
Peripheral Bus B select = 0
High Speed Bus clock divisor enable = 0
High Speed Bus select = 0
*/
pm_cksel(pm, 1, 0, 0, 0, 0, 0);
// Set one wait-state (WS) for flash controller. 0 WS access is up to 30MHz for HSB/CPU clock.
// As we want to have 48MHz on HSB/CPU clock, we need to set 1 WS on flash controller.
flashc_set_wait_state(1);
pm_switch_to_clock(pm, AVR32_PM_MCSEL_PLL0); /* Switch main clock to 48MHz */
#endif
}
/**
* \brief Detects extern OSC frequency and initialize system clocks on it
*/
void sysclk_auto_init(void)
{
int mul;
// Switch to OSC ISP
// Set max startup time to make sure any crystal will be supported
// We cannot use a TC to measure this OSC frequency
// because the master clock must be faster than the clock selected by the TC
// Configure OSC0 in crystal mode, external crystal
// with a fcrystal Hz frequency.
scif_configure_osc_crystalmode(SCIF_OSC0, 12000000);
// Enable the OSC0
scif_enable_osc(SCIF_OSC0, AVR32_SCIF_OSCCTRL0_STARTUP_16384_RCOSC,
true);
flashcdw_set_flash_waitstate_and_readmode(12000000);
pm_set_mclk_source(PM_CLK_SRC_OSC0);
// Initialize the AST with the internal RC oscillator
// AST will count at the frequency of 115KHz/2
if (!ast_init_counter(&AVR32_AST, AST_OSC_RC, 0, 0)) {
while (1);
}
// Enable the AST
ast_enable(&AVR32_AST);
// Detect the frequency
switch (freq_detect_start()) {
case 8000000:
mul = 5;
break;
case 16000000:
mul = 2;
break;
case 12000000:
default:
mul = 3;
break;
}
scif_pll_opt_t opt;
// Set PLL0 VCO @ 96 MHz
// Set PLL0 @ 48 MHz
opt.osc = SCIF_OSC0;
opt.lockcount = 63;
opt.div = 0;
opt.mul = mul;
opt.pll_div2 = 1;
opt.pll_wbwdisable = 0;
opt.pll_freq = 1;
// lockcount in main clock for the PLL wait lock
scif_pll_setup(SCIF_PLL0, &opt);
/* Enable PLL0 */
scif_pll_enable(SCIF_PLL0);
/* Wait for PLL0 locked */
scif_wait_for_pll_locked(SCIF_PLL0);
// Use 1 flash wait state
flashcdw_set_wait_state(1);
// Switch the main clock to PLL0
pm_set_mclk_source(PM_CLK_SRC_PLL0);
// fCPU: 48 MHz // USBC request a CPU clock >25MHz
// fHSB: 48 MHz
// fPBA: 48 MHz
// fPBB: 48 MHz
pm_disable_clk_domain_div(PM_CLK_DOMAIN_0); // CPU
pm_disable_clk_domain_div(PM_CLK_DOMAIN_1); // HSB
pm_disable_clk_domain_div(PM_CLK_DOMAIN_2); // PBA
pm_disable_clk_domain_div(PM_CLK_DOMAIN_3); // PBB
// Use 0 flash wait state
flashcdw_set_wait_state(1);
}
