HYT271_ERROR_t hyt271_get_measurements(double* humidity, double* temperature) { uint8_t buffer[HYT271_BUFFER_LEN]; // 1. Request measurement. // start communication with HYT271 if (i2c_start(HYT271_ADDR + I2C_WRITE)) { uart_puts_P("I2C: Failed to write-access hyt271 device.\r\n"); i2c_stop(); return HYT271_BUS_ERROR; } else { i2c_write(0x00); } i2c_stop(); // 2. Wayt for some time _delay_ms(HYT271_CONV_DELAY); // 3. Gather measurement. if (i2c_start(HYT271_ADDR+I2C_READ) ) { uart_puts_P("I2C: Failed to read-access hyt271 device.\r\n"); i2c_stop(); return HYT271_BUS_ERROR; } else { for(uint8_t i=0; i<HYT271_BUFFER_LEN-1; i++) { buffer[i]=i2c_readAck(); } buffer[HYT271_BUFFER_LEN-1] = i2c_readNak(); } i2c_stop(); // 4. convert data. From the reference implementation of hygrosens: /*++++++++++++++++++++++++++++++++++++++++++++++++++++++ * GENERAL SENSOR INFORMATION *------------------------------- * * sensor abilities: * / humidity * > 0x0000 - 0x3FFF hex * > 0 - 16383 dec * > 0 - 100 % relative humidity * * / temperature * > 0x0000 - 0x3FFF hex * > 0 - 16383 dec * > -40 - +125 °C * > -40 - +257 °F * > +233.15 - +398.15 K * * raw value format: * * | 1.byte | 2.byte | 3.byte | 4.byte | * |-----------------------|-----------------------| * | Humidity | Temperature | * |-----------------------|-----------------------| * | 2 bit | 14 bit | 14 bit | 2 bit | * |-----------|-----------|-----------|-----------| * | state | data | data | state | * * *++++++++++++++++++++++++++++++++++++++++++++++++++++++*/ uint16_t rawhum = ((buffer[0]<<8 | buffer[1]) & 0x3FFF); *humidity = (100.0/16384.0*rawhum); uint16_t rawtemp = buffer[2]<<6 | (buffer[3]&0x3F); *temperature = (165.0/16384.0*rawtemp)-40.0; return HYT271_ERROR_NONE; }
static inline void isp1301_vbus_on(void) { i2c_write(OTG1_VBUS_DRV, ISP1301_I2C_OTG_CONTROL_1); }
void pci_mpc83xx_init(volatile struct pci_controller *hose) { volatile immap_t * immr; volatile clk8349_t * clk; volatile law8349_t * pci_law; volatile pot8349_t * pci_pot; volatile pcictrl8349_t * pci_ctrl; volatile pciconf8349_t * pci_conf; u8 val8,tmp8,ret; u16 reg16,tmp16; u32 val32,tmp32; immr = (immap_t *)CFG_IMMRBAR; clk = (clk8349_t *)&immr->clk; pci_law = immr->sysconf.pcilaw; pci_pot = immr->ios.pot; pci_ctrl = immr->pci_ctrl; pci_conf = immr->pci_conf; /* * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode */ val32 = clk->occr; udelay(2000); clk->occr = 0xff000000; udelay(2000); /* * Configure PCI Local Access Windows */ pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR; pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G; pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M; /* * Configure PCI Outbound Translation Windows */ pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK); /* mapped to PCI1 IO space 0x0 to local 0xe2000000 */ pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK); pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK; pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK; pci_pot[3].pocmr = POCMR_EN | POCMR_DST | (POCMR_CM_512M & POCMR_CM_MASK); /* mapped to PCI2 IO space 0x0 to local 0xe3000000 */ pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK; pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK; pci_pot[4].pocmr = POCMR_EN | POCMR_DST | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK); /* * Configure PCI Inbound Translation Windows */ pci_ctrl[0].pitar1 = 0x0; pci_ctrl[0].pibar1 = 0x0; pci_ctrl[0].piebar1 = 0x0; pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G; pci_ctrl[1].pitar1 = 0x0; pci_ctrl[1].pibar1 = 0x0; pci_ctrl[1].piebar1 = 0x0; pci_ctrl[1].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_2G; /* * Assign PIB PMC slot to desired PCI bus */ #ifdef CONFIG_MPC8349ADS mpc8349_i2c = (i2c_t*)(CFG_IMMRBAR + CFG_I2C2_OFFSET); i2c_init(CFG_I2C_SPEED,CFG_I2C_SLAVE); #endif val8 = 0; ret = i2c_write(0x23,0x6,1,&val8,1); ret = i2c_write(0x23,0x7,1,&val8,1); val8 = 0xff; ret = i2c_write(0x23,0x2,1,&val8,1); ret = i2c_write(0x23,0x3,1,&val8,1); val8 = 0; ret = i2c_write(0x26,0x6,1,&val8,1); val8 = 0x34; ret = i2c_write(0x26,0x7,1,&val8,1); #if defined(PCI_64BIT) val8 = 0xf4; /* PMC2<->PCI1 64bit */ #elif defined(PCI_ALL_PCI1) val8 = 0xf3; /* PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI1 32bit */ #elif defined(PCI_ONE_PCI1) val8 = 0xf9; /* PMC1<->PCI1,PMC2<->PCI2,PMC3<->PCI2 32bit */ #elif defined(PCI_TWO_PCI1) val8 = 0xf5; /* PMC1<->PCI1,PMC2<->PCI1,PMC3<->PCI2 32bit */ #else val8 = 0xf5; #endif ret = i2c_write(0x26,0x2,1,&val8,1); val8 = 0xff; ret = i2c_write(0x26,0x3,1,&val8,1); val8 = 0; ret = i2c_write(0x27,0x6,1,&val8,1); ret = i2c_write(0x27,0x7,1,&val8,1); val8 = 0xff; ret = i2c_write(0x27,0x2,1,&val8,1); val8 = 0xef; ret = i2c_write(0x27,0x3,1,&val8,1); asm("eieio"); /* * Release PCI RST Output signal */ udelay(2000); pci_ctrl[0].gcr = 1; #ifndef PCI_64BIT pci_ctrl[1].gcr = 1; #endif udelay(2000); hose[0].first_busno = 0; hose[0].last_busno = 0xff; pci_set_region(hose[0].regions + 0, CFG_PCI1_MEM_BASE, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_SIZE, PCI_REGION_MEM); pci_set_region(hose[0].regions + 1, CFG_PCI1_IO_BASE, CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO); hose[0].region_count = 2; pci_setup_indirect(&hose[0], (CFG_IMMRBAR+0x8300), (CFG_IMMRBAR+0x8304)); #define PCI_CLASS_BRIDGE 0x06 reg16 = 0xff; tmp32 = 0xffff; pci_hose_write_config_byte(&hose[0],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE); pci_hose_read_config_word (&hose[0],PCI_BDF(0,0,0),PCI_COMMAND, ®16); reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_hose_write_config_word(&hose[0],PCI_BDF(0,0,0), PCI_COMMAND, reg16); /* * Clear non-reserved bits in status register. */ pci_hose_write_config_word(&hose[0],PCI_BDF(0,0,0), PCI_STATUS, 0xffff); pci_hose_write_config_byte(&hose[0],PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80); #ifndef PCI_64BIT hose[1].first_busno = 0; hose[1].last_busno = 0xff; pci_set_region(hose[1].regions + 0, CFG_PCI2_MEM_BASE, CFG_PCI2_MEM_PHYS, CFG_PCI2_MEM_SIZE, PCI_REGION_MEM); pci_set_region(hose[1].regions + 1, CFG_PCI2_IO_BASE, CFG_PCI2_IO_PHYS, CFG_PCI2_IO_SIZE, PCI_REGION_IO); hose[1].region_count = 2; pci_setup_indirect(&hose[1], (CFG_IMMRBAR+0x8380), (CFG_IMMRBAR+0x8384)); pci_hose_write_config_byte(&hose[1],PCI_BDF(0,0,0),PCI_CLASS_CODE,PCI_CLASS_BRIDGE); pci_hose_read_config_word (&hose[1],PCI_BDF(0,0,0), PCI_COMMAND, ®16); reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_hose_write_config_word(&hose[1],PCI_BDF(0,0,0), PCI_COMMAND, reg16); /* * Clear non-reserved bits in status register. */ pci_hose_write_config_word(&hose[1],PCI_BDF(0,0,0), PCI_STATUS, 0xffff); pci_hose_write_config_byte(&hose[1],PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80); #endif #if defined(PCI_64BIT) printf("PCI1 64bit on PMC2\n"); #elif defined(PCI_ALL_PCI1) printf("PCI1 32bit on PMC1 & PMC2 & PMC3\n"); #elif defined(PCI_ONE_PCI1) printf("PCI1 32bit on PMC1,PCI2 32bit on PMC2 & PMC3\n"); #else printf("PCI1 32bit on PMC1 & PMC2 & PMC3 in default\n"); #endif #if 1 /* * Hose scan. */ pci_register_hose(hose); hose->last_busno = pci_hose_scan(hose); #endif }
int sy8106a_set_vout1(unsigned int mvolt) { u8 data = sy8106a_mvolt_to_cfg(mvolt, 680, 1950, 10) | SY8106A_VOUT1_SEL_ENABLE; return i2c_write(SY8106A_I2C_ADDR, SY8106A_VOUT1_SEL, 1, &data, 1); }
void display_init() { i2c_start(0x4E, 0x00, TW_WRITE); i2c_write(0x30); i2c_write(0x30); i2c_write(0x30); i2c_write(0x20); i2c_write(0x20); i2c_write(0xF0); i2c_write(0x00); i2c_write(0xF0); i2c_write(0x00); i2c_write(0x10); i2c_write(0x00); i2c_write(0x60); i2c_stop(); }
i2c_ack i2c_read_2byte(int bus_id, char chip_addr, unsigned int sub_addr, char *buf, unsigned int size) { #ifdef FLY_VIDEO_BOARD_V3 int ret_rec = 0; ret_rec = SOC_I2C_Rec_2B_SubAddr(3, TC358746_I2C_ChipAdd, sub_addr, buf, size); //lidbg("\n************i2c_read_2byte ret_rec=%d *****************\n",ret_rec); if(ret_rec > 0) { return ACK; } else { return NACK; } #else u8 i; mutex_lock(&io_i2c_lock); i2c_init(); // start transmite i2c_begin();//msg 0>> i2c_write_chip_addr(chip_addr, hkj_WRITE) ; if (i2c_read_ack () == NACK) { i2c_stop(); i2c_free(); lidbg(" chip_addr devices is not ACK------i2c_write_chip_addr----r--\r\n"); mutex_unlock(&io_i2c_lock); return NACK; } //i2c_stop(); // restart transmite // send message to mm_i2c device to transmite data i2c_write(sub_addr >> 8) ; if (i2c_read_ack () == NACK) { i2c_stop(); i2c_free(); lidbg(" chip_addr devices is not ACK-----subadder1-------\r\n"); mutex_unlock(&io_i2c_lock); return NACK; } i2c_write(sub_addr) ; if (i2c_read_ack () == NACK) { i2c_stop(); i2c_free(); lidbg(" chip_addr devices is not ACK------subadder0------\r\n"); mutex_unlock(&io_i2c_lock); return NACK; } i2c_stop();//msg 0<< // start transmite i2c_begin();//msg 1>> i2c_write_chip_addr(chip_addr, hkj_READ) ; if (i2c_read_ack () == NACK) { i2c_stop(); i2c_free(); lidbg(" chip_addr devices is not ACK----- i2c_write_chip_addr-------\r\n"); mutex_unlock(&io_i2c_lock); return NACK; } // transmite data for(i = 0; i < size; i++) { buf[i] = i2c_read(); ( i == (size - 1) ) ? i2c_write_ask(NACK) : i2c_write_ask(ACK); } // stop transmite i2c_stop();//msg 1<< i2c_free(); mutex_unlock(&io_i2c_lock); return ACK; #endif }
uint8_t getSRF(void) { uint8_t lsb_srf = 0; uint8_t msb_srf = 0; switch(srf[srf_sm_manage].state) { case 0: if((i2c_start(pgm_read_byte(&srf_i2c_addresses[srf_sm_manage])) == 0) && (i2c_write(0x00) == 0) && (i2c_write(I2C_REG_SRF10_MEASERUEMENT_S) == 0) && (i2c_stop() == 0)) { srf[srf_sm_manage].state = 1; //Messung ok, nächster Schritt getSRF_returnvar &= ~(1<<srf_sm_manage); } else { srf[srf_sm_manage].state = 0; //Beim nächsten Durchlauf nochmal getSRF_returnvar |= (1<<srf_sm_manage); //etwas hat nicht funktioniert srf_sm_manage ++; //nächster Sensor if(srf_sm_manage >= NUMBER_OF_SRF) srf_sm_manage = 0; } break; case 1: if((i2c_start(pgm_read_byte(&srf_i2c_addresses[srf_sm_manage])) != 0) || //Abfragen: Ist die Messung beendet? (i2c_write(0x00) != 0) || (i2c_rep_start(pgm_read_byte(&srf_i2c_addresses[srf_sm_manage])+I2C_READ) != 0) || (i2c_readNak() == 255) || (i2c_stop() != 0)) { srf[srf_sm_manage].state = 0; getSRF_returnvar |= (1<<srf_sm_manage); srf_sm_manage ++; //nächster Sensor if(srf_sm_manage >= NUMBER_OF_SRF) srf_sm_manage = 0; } else { srf[srf_sm_manage].state = 2; } break; case 2: if((i2c_start(pgm_read_byte(&srf_i2c_addresses[srf_sm_manage])) == 0) && //Auslesen der ENtfernung (i2c_write(0x02) == 0) && (i2c_rep_start(pgm_read_byte(&srf_i2c_addresses[srf_sm_manage])+I2C_READ) == 0)) { lsb_srf = i2c_readAck(); msb_srf = i2c_readNak(); srf[srf_sm_manage].dist = (((uint16_t)lsb_srf << 8) | msb_srf);// * SRF10_US_TO_MM; if(i2c_stop() != 0) getSRF_returnvar |= (1<<srf_sm_manage); } else { getSRF_returnvar |= (1<<srf_sm_manage); } srf[srf_sm_manage].state = 0; srf_sm_manage ++; //nächster Sensor if(srf_sm_manage >= NUMBER_OF_SRF) srf_sm_manage = 0; break; } return getSRF_returnvar; }
int drv_l2_audiocodec_wm8988_rx_init(void) { INT32U R, boost = 0x3, mic_pga_l = 0x20, mic_pga_r = 0x7; INT32U alc_max = 0x7, alc_target = 0xB; // RX Register pack.info = i2c_wolfson_WM8988(67,0x0); i2c_write(&i2c_handle,pack.data[0] ,pack.data[1]); pack.info = i2c_wolfson_WM8988(24,0x0); i2c_write(&i2c_handle,pack.data[0] ,pack.data[1]); pack.info = i2c_wolfson_WM8988(25,0xEC); i2c_write(&i2c_handle,pack.data[0] ,pack.data[1]); pack.info = i2c_wolfson_WM8988(26,0x1F8); i2c_write(&i2c_handle,pack.data[0] ,pack.data[1]); pack.info = i2c_wolfson_WM8988(7,0x2); i2c_write(&i2c_handle,pack.data[0] ,pack.data[1]); pack.info = i2c_wolfson_WM8988(8,0x18); i2c_write(&i2c_handle,pack.data[0] ,pack.data[1]); pack.info = i2c_wolfson_WM8988(31,0x100); i2c_write(&i2c_handle,pack.data[0] ,pack.data[1]); pack.info = i2c_wolfson_WM8988(32,0xC0|(boost<<4)); i2c_write(&i2c_handle,pack.data[0] ,pack.data[1]); pack.info = i2c_wolfson_WM8988(33,0xC0|(boost<<4)); i2c_write(&i2c_handle,pack.data[0] ,pack.data[1]); { R = 0x97; R &= ~0x3F; R &= ~0x80; //Disable Mute R |= 0x100; R |= mic_pga_l; pack.info = i2c_wolfson_WM8988(0,R); i2c_write(&i2c_handle,pack.data[0] ,pack.data[1]); } { R = 0x97; R &= ~0x3F; R &= ~0x80; //Disable Mute R |= 0x100; R |= mic_pga_r; pack.info = i2c_wolfson_WM8988(1,R); i2c_write(&i2c_handle,pack.data[0] ,pack.data[1]); } { R = 0x7B; R &= ~0x7; R |= alc_max << 4; R |= alc_target; //R |= 0x180; //turn on ALC pack.info = i2c_wolfson_WM8988(17,R); i2c_write(&i2c_handle,pack.data[0] ,pack.data[1]); } pack.info = i2c_wolfson_WM8988(21,0x1D0); i2c_write(&i2c_handle,pack.data[0] ,pack.data[1]); pack.info = i2c_wolfson_WM8988(22,0x1D0); i2c_write(&i2c_handle,pack.data[0] ,pack.data[1]); return 0; }
int drv_l2_audiocodec_wm8988_tx_init(void) { // TX register pack.info = i2c_wolfson_WM8988(67,0x0); i2c_write(&i2c_handle,pack.data[0] ,pack.data[1]); pack.info = i2c_wolfson_WM8988(24,0x0); i2c_write(&i2c_handle,pack.data[0] ,pack.data[1]); pack.info = i2c_wolfson_WM8988(25,0xEC); i2c_write(&i2c_handle,pack.data[0] ,pack.data[1]); pack.info = i2c_wolfson_WM8988(26,0x1F8); i2c_write(&i2c_handle,pack.data[0] ,pack.data[1]); pack.info = i2c_wolfson_WM8988(2,0x179); i2c_write(&i2c_handle,pack.data[0] ,pack.data[1]); pack.info = i2c_wolfson_WM8988(3,0x179); i2c_write(&i2c_handle,pack.data[0] ,pack.data[1]); pack.info = i2c_wolfson_WM8988(40,0x179); i2c_write(&i2c_handle,pack.data[0] ,pack.data[1]); pack.info = i2c_wolfson_WM8988(41,0x179); i2c_write(&i2c_handle,pack.data[0] ,pack.data[1]); pack.info = i2c_wolfson_WM8988(5,0x0); i2c_write(&i2c_handle,pack.data[0] ,pack.data[1]); pack.info = i2c_wolfson_WM8988(7,0x2); i2c_write(&i2c_handle,pack.data[0] ,pack.data[1]); pack.info = i2c_wolfson_WM8988(34,0x150); i2c_write(&i2c_handle,pack.data[0] ,pack.data[1]); pack.info = i2c_wolfson_WM8988(35,0x50); i2c_write(&i2c_handle,pack.data[0] ,pack.data[1]); pack.info = i2c_wolfson_WM8988(36,0x50); i2c_write(&i2c_handle,pack.data[0] ,pack.data[1]); pack.info = i2c_wolfson_WM8988(37,0x150); i2c_write(&i2c_handle,pack.data[0] ,pack.data[1]); return 0; }
/* Write (fill) memory * * Syntax: * imw {i2c_chip} {addr}{.0, .1, .2} {data} [{count}] */ int do_i2c_mw ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { uchar chip; ulong addr; uint alen; uchar byte; int count; int j; if ((argc < 4) || (argc > 5)) { printf ("Usage:\n%s\n", cmdtp->usage); return 1; } /* * Chip is always specified. */ chip = simple_strtoul(argv[1], NULL, 16); /* * Address is always specified. */ addr = simple_strtoul(argv[2], NULL, 16); alen = 1; for(j = 0; j < 8; j++) { if (argv[2][j] == '.') { alen = argv[2][j+1] - '0'; if(alen > 4) { printf ("Usage:\n%s\n", cmdtp->usage); return 1; } break; } else if (argv[2][j] == '\0') { break; } } /* * Value to write is always specified. */ byte = simple_strtoul(argv[3], NULL, 16); /* * Optional count */ if(argc == 5) { count = simple_strtoul(argv[4], NULL, 16); } else { count = 1; } while (count-- > 0) { if(i2c_write(chip, addr++, alen, &byte, 1) != 0) { puts ("Error writing the chip.\n"); } /* * Wait for the write to complete. The write can take * up to 10mSec (we allow a little more time). * * On some chips, while the write is in progress, the * chip doesn't respond. This apparently isn't a * universal feature so we don't take advantage of it. */ /* * No write delay with FRAM devices. */ #if !defined(CFG_I2C_FRAM) udelay(11000); #endif #if 0 for(timeout = 0; timeout < 10; timeout++) { udelay(2000); if(i2c_probe(chip) == 0) break; } #endif } return (0); }
void mcp4651_init(void) { i2c_start_wait(MCP4651+I2C_WRITE); // set device address and write mode i2c_write(0x40); // write pointer address to TCON, disable general call i2c_write(0xFF); i2c_stop(); }
void main (void) { io_init(); servo_init(); timers_init(); i2c_init(); wdt_enable(WDTO_15MS); sei(); start_timers(); flags.new_buf_ready = 0; flags.i2c_first_byte = 0; flags.servo_pd_changed = 0; flags.servo_minmaxpd_cnahged = 0; #ifdef MEGADEBUG struct { uint8_t sw1 : 1; uint8_t sw2 : 1; } ss; UTILS_DDR_CLR(I2CSCL_PORT, I2CSCL_PIN); UTILS_DDR_CLR(I2CSDA_PORT, I2CSDA_PIN); UTILS_PORT_SET(I2CSCL_PORT, I2CSCL_PIN); UTILS_PORT_SET(I2CSDA_PORT, I2CSDA_PIN); #endif for (;;) { #ifdef MEGADEBUG if (!UTILS_PIN_VALUE(I2CSCL_PORT, I2CSCL_PIN)) { if (!ss.sw1) { servo[0].target += 16; } ss.sw1 = 1; } else { ss.sw1 = 0; } if (!UTILS_PIN_VALUE(I2CSDA_PORT, I2CSDA_PIN)) { if (!ss.sw2) { servo[0].target -= 16; } ss.sw2 = 1; } else { ss.sw2 = 0; } #endif #ifndef MEGADEBUG // i2c if (TWCR & _BV(TWINT)) { // i2c switch (TWSR) { case TW_SR_SLA_ACK: // i2c start flags.i2c_first_byte = 1; break; case TW_SR_DATA_ACK: // i2c byte received if (flags.i2c_first_byte) { i2cMemAddr = TWDR; flags.i2c_first_byte = 0; } else { i2c_read(); i2cMemAddr ++; } break; case TW_ST_DATA_ACK: i2c_write(); i2cMemAddr ++; break; } TWCR |= _BV(TWINT); } #endif // servo.position if (UTILS_AGGL(TIFR, ITIMER) & _BV(UTILS_AGGL2(OCF, ITIMER, A))) { // Timer ITIMER compare match A UTILS_AGGL(TIFR, ITIMER) |= _BV(UTILS_AGGL2(OCF, ITIMER, A)); for (uint8_t i = 0; i < SERVO_NUM; i ++) { if (servo[i].position != servo[i].target) { UTILS_PORT_SET(LED_PORT, LED_PIN); if (servo[i].speed == 0) { // Change position immediately servo[i].position = servo[i].target; servo_find_pd(i); flags.servo_pd_changed = 1; } else { if (servo[i].speed_counter == servo[i].speed) { // Change position if (servo[i].position < servo[i].target) servo[i].position ++; else servo[i].position --; servo_find_pd(i); flags.servo_pd_changed = 1; servo[i].speed_counter = 0; } else servo[i].speed_counter ++; } } else { UTILS_PORT_CLR(LED_PORT, LED_PIN); } } if (flags.servo_minmaxpd_cnahged) { for (uint8_t i = 0; i < SERVO_NUM; i ++) { servo_find_pd(i); } flags.servo_pd_changed = 1; flags.servo_minmaxpd_cnahged = 0; } if (flags.servo_pd_changed) { servo_sort(); outstate_gen(); flags.servo_pd_changed = 0; } } wdt_reset(); } }
void setup_i2c(){ // Init sequence for 128x64 OLED module i2c_write(0xAE); // Display Off i2c_write(0x00 | 0x0); // low col = 0 i2c_write(0x10 | 0x0); // hi col = 0 i2c_write(0x40 | 0x0); // line #0 i2c_write(0x81); // Set Contrast 0x81 i2c_write(0xCF); // flips display i2c_write(0xA1); // Segremap - 0xA1 i2c_write(0xC8); // COMSCAN DEC 0xC8 C0 i2c_write(0xA6); // Normal Display 0xA6 (Invert A7) i2c_write(0xA4); // DISPLAY ALL ON RESUME - 0xA4 i2c_write(0xA8); // Set Multiplex 0xA8 i2c_write(0x3F); // 1/64 Duty Cycle i2c_write(0xD3); // Set Display Offset 0xD3 i2c_write(0x0); // no offset i2c_write(0xD5); // Set Display Clk Div 0xD5 i2c_write(0x80); // Recommneded resistor ratio 0x80 i2c_write(0xD9); // Set Precharge 0xd9 i2c_write(0xF1); i2c_write(0xDA); // Set COM Pins0xDA i2c_write(0x12); i2c_write(0xDB); // Set VCOM Detect - 0xDB i2c_write(0x40); i2c_write(0x20); // Set Memory Addressing Mode i2c_write(0x00); // 0x00 - Horizontal i2c_write(0x40 | 0x0); // Set start line at line 0 - 0x40 i2c_write(0x8D); // Charge Pump -0x8D i2c_write(0x14); i2c_write(0xA4); //--turn on all pixels - A5. Regular mode A4 i2c_write(0xAF); //--turn on oled panel - AF }
/** * @brief IRQ handler for I2C master. Handles transmission/reception. * @param dev I2C device */ static void i2c_irq_handler(i2c_dev *dev) { i2c_msg *msg = dev->msg; uint8 read = msg->flags & I2C_MSG_READ; uint32 sr1 = dev->regs->SR1; uint32 sr2 = dev->regs->SR2; I2C_CRUMB(IRQ_ENTRY, sr1, sr2); /* * Reset timeout counter */ dev->timestamp = systick_uptime(); /* * EV5: Start condition sent */ if (sr1 & I2C_SR1_SB) { msg->xferred = 0; i2c_enable_irq(dev, I2C_IRQ_BUFFER); /* * Master receiver */ if (read) { i2c_enable_ack(dev); } i2c_send_slave_addr(dev, msg->addr, read); sr1 = sr2 = 0; } /* * EV6: Slave address sent */ if (sr1 & I2C_SR1_ADDR) { /* * Special case event EV6_1 for master receiver. * Generate NACK and restart/stop condition after ADDR * is cleared. */ if (read) { if (msg->length == 1) { i2c_disable_ack(dev); if (dev->msgs_left > 1) { i2c_start_condition(dev); I2C_CRUMB(RX_ADDR_START, 0, 0); } else { i2c_stop_condition(dev); I2C_CRUMB(RX_ADDR_STOP, 0, 0); } } } else { /* * Master transmitter: write first byte to fill shift * register. We should get another TXE interrupt * immediately to fill DR again. */ if (msg->length != 1) { i2c_write(dev, msg->data[msg->xferred++]); } } sr1 = sr2 = 0; } /* * EV8: Master transmitter * Transmit buffer empty, but we haven't finished transmitting the last * byte written. */ if ((sr1 & I2C_SR1_TXE) && !(sr1 & I2C_SR1_BTF)) { I2C_CRUMB(TXE_ONLY, 0, 0); if (dev->msgs_left) { i2c_write(dev, msg->data[msg->xferred++]); if (msg->xferred == msg->length) { /* * End of this message. Turn off TXE/RXNE and wait for * BTF to send repeated start or stop condition. */ i2c_disable_irq(dev, I2C_IRQ_BUFFER); dev->msgs_left--; } } else { /* * This should be impossible... */ throb(); } sr1 = sr2 = 0; } /* * EV8_2: Master transmitter * Last byte sent, program repeated start/stop */ if ((sr1 & I2C_SR1_TXE) && (sr1 & I2C_SR1_BTF)) { I2C_CRUMB(TXE_BTF, 0, 0); if (dev->msgs_left) { I2C_CRUMB(TEST, 0, 0); /* * Repeated start insanity: We can't disable ITEVTEN or else SB * won't interrupt, but if we don't disable ITEVTEN, BTF will * continually interrupt us. What the f**k ST? */ i2c_start_condition(dev); while (!(dev->regs->SR1 & I2C_SR1_SB)) ; dev->msg++; } else { i2c_stop_condition(dev); /* * Turn off event interrupts to keep BTF from firing until * the end of the stop condition. Why on earth they didn't * have a start/stop condition request clear BTF is beyond * me. */ i2c_disable_irq(dev, I2C_IRQ_EVENT); I2C_CRUMB(STOP_SENT, 0, 0); dev->state = I2C_STATE_XFER_DONE; } sr1 = sr2 = 0; } /* * EV7: Master Receiver */ if (sr1 & I2C_SR1_RXNE) { I2C_CRUMB(RXNE_ONLY, 0, 0); msg->data[msg->xferred++] = dev->regs->DR; /* * EV7_1: Second to last byte in the reception? Set NACK and generate * stop/restart condition in time for the last byte. We'll get one more * RXNE interrupt before shutting things down. */ if (msg->xferred == (msg->length - 1)) { i2c_disable_ack(dev); if (dev->msgs_left > 2) { i2c_start_condition(dev); I2C_CRUMB(RXNE_START_SENT, 0, 0); } else { i2c_stop_condition(dev); I2C_CRUMB(RXNE_STOP_SENT, 0, 0); } } else if (msg->xferred == msg->length) { dev->msgs_left--; if (dev->msgs_left == 0) { /* * We're done. */ I2C_CRUMB(RXNE_DONE, 0, 0); dev->state = I2C_STATE_XFER_DONE; } else { dev->msg++; } } } }
i2c_ack i2c_read_byte(int bus_id, char chip_addr, unsigned int sub_addr, char *buf, unsigned int size) { #ifdef FLY_VIDEO_BOARD_V3 int ret = 0; //ret=i2c_api_do_recv(3,chip_addr, sub_addr , buf, size); ret = SOC_I2C_Rec(3, chip_addr, sub_addr , buf, size); //lidbg("\n************ i2c_read_byte =%d*******\n",ret); //if(ret==size){ if(ret > 0) { #ifdef DEBUG_ACK return NACK; #else return ACK; #endif } else { return NACK; } #else u8 i; mutex_lock(&io_i2c_lock); i2c_init(); // start transmite i2c_begin(); i2c_write_chip_addr(chip_addr, hkj_WRITE) ; if (i2c_read_ack () == NACK) { i2c_stop(); i2c_free(); lidbg("at read funtion :i2c_write_chip_addr(%.2x, %d) ; is not ACK\n", chip_addr, hkj_WRITE); mutex_unlock(&io_i2c_lock); return NACK; } //i2c_stop(); // restart transmite //i2c_begin(); // send message to mm_i2c device to transmite data i2c_write(sub_addr) ; if (i2c_read_ack () == NACK) { i2c_stop(); i2c_free(); lidbg("at read funtion :i2c_write (%.2x) is not ACK\n", sub_addr & 0xff); mutex_unlock(&io_i2c_lock); return NACK; } i2c_stop(); // start transmite i2c_begin(); i2c_write_chip_addr(chip_addr, hkj_READ) ; if (i2c_read_ack() == NACK) { i2c_stop(); i2c_free(); lidbg("at read funtion :i2c_write_chip_addr(%.2x, %d) ; is not ACK\n", sub_addr, hkj_READ); mutex_unlock(&io_i2c_lock); return NACK; } // transmite data for(i = 0; i < size; i++) { buf[i] = i2c_read(); ( i == (size - 1) ) ? i2c_write_ask(NACK) : i2c_write_ask(ACK); } // stop transmite i2c_stop(); i2c_free(); mutex_unlock(&io_i2c_lock); return ACK; #endif }
int read_mac_sn(char *buf, ushort len) { int i; uchar num; ushort addr = 0xE000; rrb_data_t dat; uchar i2c_addr = 0x59; while(1) { if (len >= 0x10) num = 0x10; else num = len; dat.bytes = 2; dat.reg = 2; dat.data[0] = addr & 0xff; dat.data[1] = (addr >> 8) & 0xff; for(i = 0; i < dat.bytes; i++) { if(i2c_write(i2c_addr, dat.reg + i, 1, &dat.data[i], 1)) { printf("error sending address\n"); goto out; } } dat.bytes = 1; dat.reg = 1; dat.data[0] = num; for(i = 0; i < dat.bytes; i++) { if(i2c_write(i2c_addr, dat.reg + i, 1, &dat.data[i], 1)) { printf("Error sending byte count\n"); goto out; } } dat.bytes = 1; dat.reg = 0; dat.data[0] = 0x0C; for(i = 0; i < dat.bytes; i++) { if(i2c_write(i2c_addr, dat.reg + i, 1, &dat.data[i], 1)) { printf("Error sending command\n"); goto out; } } dat.bytes = num; dat.reg = 6; for(i = 0; i < dat.bytes; i++) { i2c_read(i2c_addr, dat.reg + i, 1, &dat.data[i], 1); } memcpy(buf, &dat.data[0], num); buf += num; addr += num; len -= num; if (!len) return 0; } out: return -1; }
i2c_ack i2c_write_byte(int bus_id, char chip_addr, char *buf, unsigned int size) { #ifdef FLY_VIDEO_BOARD_V3 int ret_send = 0; ret_send = SOC_I2C_Send(3, chip_addr, buf, size); // lidbg("\n************i2c_write_byte =%d*******\n",ret_send); if(ret_send > 0) { #ifdef DEBUG_ACK return NACK; #else return ACK; #endif } else { return NACK; } #else u8 i; mutex_lock(&io_i2c_lock); //lidbg("i2c:write byte:addr =0x%.2x value=0x%.2x ",buf[0],buf[1]); i2c_init(); // start transmite i2c_begin(); i2c_write_chip_addr(chip_addr, hkj_WRITE) ; if (i2c_read_ack() == NACK) { i2c_stop(); i2c_free(); lidbg(" at write funtion: i2c_write_chip_addr(%.2x, %d) ; is not ACK\n", chip_addr, hkj_WRITE); mutex_unlock(&io_i2c_lock); return NACK; } //i2c_stop(); // restart transmite //i2c_begin(); // send message to mm_i2c device to transmite data i2c_write(buf[0]) ; if (i2c_read_ack() == NACK) { i2c_stop(); i2c_free(); lidbg(" at write funtion:i2c_write(%.2x) ;is not ACK\n", buf[0]); mutex_unlock(&io_i2c_lock); return NACK; } // transmite data for(i = 1; i < size; i++) { i2c_write(buf[i]); if( i2c_read_ack() == NACK) { i2c_stop(); i2c_free(); lidbg(" at write funtion:i2c_write(%.2x) ;is not ACK\n", buf[i]); mutex_unlock(&io_i2c_lock); return NACK; } } // stop transmite i2c_stop(); i2c_free(); mutex_unlock(&io_i2c_lock); return ACK; #endif }
/** * rmii_hw_init * * DA850/OMAP-L138 EVM can interface to a daughter card for * additional features. This card has an I2C GPIO Expander TCA6416 * to select the required functions like camera, RMII Ethernet, * character LCD, video. * * Initialization of the expander involves configuring the * polarity and direction of the ports. P07-P05 are used here. * These ports are connected to a Mux chip which enables only one * functionality at a time. * * For RMII phy to respond, the MII MDIO clock has to be disabled * since both the PHY devices have address as zero. The MII MDIO * clock is controlled via GPIO2[6]. * * This code is valid for Beta version of the hardware */ int rmii_hw_init(void) { const struct pinmux_config gpio_pins[] = { { pinmux(6), 8, 1 } }; u_int8_t buf[2]; unsigned int temp; int ret; /* PinMux for GPIO */ if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0) return 1; /* I2C Exapnder configuration */ /* Set polarity to non-inverted */ buf[0] = 0x0; buf[1] = 0x0; ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2); if (ret) { printf("\nExpander @ 0x%02x write FAILED!!!\n", CONFIG_SYS_I2C_EXPANDER_ADDR); return ret; } /* Configure P07-P05 as outputs */ buf[0] = 0x1f; buf[1] = 0xff; ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2); if (ret) { printf("\nExpander @ 0x%02x write FAILED!!!\n", CONFIG_SYS_I2C_EXPANDER_ADDR); } /* For Ethernet RMII selection * P07(SelA)=0 * P06(SelB)=1 * P05(SelC)=1 */ if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { printf("\nExpander @ 0x%02x read FAILED!!!\n", CONFIG_SYS_I2C_EXPANDER_ADDR); } buf[0] &= 0x1f; buf[0] |= (0 << 7) | (1 << 6) | (1 << 5); if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) { printf("\nExpander @ 0x%02x write FAILED!!!\n", CONFIG_SYS_I2C_EXPANDER_ADDR); } /* Set the output as high */ temp = REG(GPIO_BANK2_REG_SET_ADDR); temp |= (0x01 << 6); REG(GPIO_BANK2_REG_SET_ADDR) = temp; /* Set the GPIO direction as output */ temp = REG(GPIO_BANK2_REG_DIR_ADDR); temp &= ~(0x01 << 6); REG(GPIO_BANK2_REG_DIR_ADDR) = temp; return 0; }
i2c_ack i2c_write_2byte(int bus_id, char chip_addr, char *buf, unsigned int size) { #ifdef FLY_VIDEO_BOARD_V3 int ret_send = 0; ret_send = SOC_I2C_Send(3, chip_addr, buf, size); //lidbg("\n*************i2c_write_2byt ret_send=%d**************\n",ret_send); if(ret_send > 0) { return ACK; } else { return NACK; } #else u8 i; mutex_lock(&io_i2c_lock); i2c_init(); // start transmite i2c_begin();//msg 0>> i2c_write_chip_addr(chip_addr, hkj_WRITE) ; if (i2c_read_ack() == NACK) { i2c_stop(); i2c_free(); lidbg(" chip_addr devices is not ACK--in-i2c_write_chip_addr(%.2x)----w-----\r\n", chip_addr); mutex_unlock(&io_i2c_lock); return NACK; } // send message to mm_i2c device to transmite data i2c_write(buf[0]) ;//subaddr MSB if (i2c_read_ack () == NACK) { i2c_stop(); i2c_free(); lidbg(" chip_addr devices is not ACK--in-i2c_write(sub[%d])=%.2x-----w----\r\n", 0, buf[0]); mutex_unlock(&io_i2c_lock); return NACK; } i2c_write(buf[1]) ;//subaddr if (i2c_read_ack () == NACK) { i2c_stop(); i2c_free(); lidbg("chip_addr devices is not ACK--in-i2c_write(sub[%d])=%.2x--w", 1, buf[1]); mutex_unlock(&io_i2c_lock); return NACK; } // transmite data for(i = 2; i < size; i++) { i2c_write(buf[i]); if( i2c_read_ack() == NACK) { i2c_stop(); i2c_free(); lidbg(" chip_addr devices is not ACK--in-i2c_write(buf[%d])=%.2x--w----\r\n", (i - 2), buf[i]); mutex_unlock(&io_i2c_lock); return NACK; } } // stop transmite i2c_stop();//msg 0<< i2c_free(); mutex_unlock(&io_i2c_lock); return ACK; #endif }
INT32 tun_dbcte702f1_control(UINT32 tuner_id, UINT32 freq, UINT32 sym, UINT8 AGC_Time_Const, UINT8 _i2c_cmd) { INT32 result; UINT16 Npro; UINT32 OscFreq; UINT8 StepFreq,RefDivRatio,TunCrystal; UINT8 RS, ATP, BS; UINT8 data[5]; struct QAM_TUNER_CONFIG_EXT * tuner_dev_ptr = NULL; if ((tuner_id>=dbcte702f1_tuner_cnt) || (tuner_id>=MAX_TUNER_SUPPORT_NUM)) return ERR_FAILUE; tuner_dev_ptr = dbcte702f1_dev_id[tuner_id]; DBCTE702F1_PRINTF("%s: feq, sym: %d, %d !\n", __FUNCTION__, freq, sym); //==========Calculate control bytes============= OscFreq = freq + tuner_dev_ptr->wTuner_IF_Freq; StepFreq = tuner_dev_ptr->cTuner_Step_Freq; RefDivRatio = tuner_dev_ptr->cTuner_Ref_DivRatio; TunCrystal = tuner_dev_ptr->cTuner_Crystal; Npro=OscFreq * RefDivRatio / (TunCrystal * 1000); if (RefDivRatio == 24) //166.667 RS = 0x00; else if (RefDivRatio == 28)//142.857 RS = 0x01; else if (RefDivRatio == 50) //80 RS = 0x02; else if (RefDivRatio == 64) // 62.5 RS = 0x03; else if (RefDivRatio == 128) // 31.25 RS = 0x04; else if (RefDivRatio == 80) //50 RS = 0x05; else RS = 0x03; //ATP = 0x01; //Normal op //ATP = 0x07; //Dual AGC ATP = tuner_dev_ptr->cTuner_AGC_TOP; if ((OscFreq >= 85000) && (OscFreq < 185000)) BS = 0x01; else if ((OscFreq >= 185000) && (OscFreq < 465000)) BS = 0x06; else if ((OscFreq >= 465000) && (OscFreq < 896000)) BS = 0x0C; else BS = 0x0C; //==========Evaluated to control bytes============= data[0] = (UINT8)((Npro>>8)&0x7F); data[1] = (UINT8)(Npro&0xFF); data[2] = 0x80 | ((ATP<<3)&0x38) | (RS&0x07); data[3] = BS&0x0f; data[4] = 0xc3; //==========Write to tuner register=============== if(AGC_Time_Const == SLOW_TIMECST_AGC) osal_task_sleep(50); result = ERR_FAILUE; if(_i2c_cmd==_1st_i2c_cmd) { result = i2c_write(tuner_dev_ptr->i2c_type_id, tuner_dev_ptr->cTuner_Base_Addr, data,5); } return result; }
int main() { file = i2c_open("/dev/i2c-4"); if (file == -1) { printf("Unable to open i2c bus.\n"); exit(1); } printf("Opened i2c bus\n"); __u8 tmp; /* * Accel configuration */ /* CTRL_REG1_A: low power disabled, 400Hz update rate, all axes enabled */ tmp = 0x97; if(i2c_write(file, ACCEL_ADDRESS, ACCEL_CTRL_REG1_A, 1, &tmp) != 1) { printf("Unable to write CTRL_REG1A\n"); } /* CTRL_REG4_A: scale, high res update mode */ tmp = 0x08; if(i2c_write(file, ACCEL_ADDRESS, ACCEL_CTRL_REG4_A, 1, &tmp) != 1) { printf("Unable to write CTRL_REG4A\n"); } /* * Compass configuration */ /* CRA_REG_M: temp sensor on, update rate set to 220Hz */ tmp = 0x9C; if(i2c_write(file, MAGNET_ADDRESS, MAGNET_CRA_REG_M, 1, &tmp) != 1) { printf("Unable to write CRA_REG_M\n"); } /* CRB_REG_M: gain setting */ tmp = 0xE0; if(i2c_write(file, MAGNET_ADDRESS, MAGNET_CRB_REG_M, 1, &tmp) != 1) { printf("Unable to write CRB_REG_M\n"); } /* MR_REG_M continous-conversion mode */ tmp = 0x00; if(i2c_write(file, MAGNET_ADDRESS, MAGNET_MR_REG_M, 1, &tmp) != 1) { printf("Unable to write MR_REG_M\n"); } /* * Gyro configuration */ /* CTRL_REG1 ODR, bandwidth, power down off, all axes enabled */ tmp = 0xEF; if(i2c_write(file, GYRO_ADDRESS, GYRO_CTRL_REG1, 1, &tmp) != 1) { printf("Unable to write CTRL_REG1_A\n"); } /* CTRL_REG4 ODR, full scale */ tmp = 0x10; if(i2c_write(file, GYRO_ADDRESS, GYRO_CTRL_REG4, 1, &tmp) != 1) { printf("Unable to write CTRL_REG1_A\n"); } __u8 accel_axes[6]; __u8 magnet_axes[6]; __u8 gyro_axes[6]; __s16 accel_values[3]; __s16 magnet_values[3]; __s16 gyro_values[3]; while(1) { if(i2c_read(file, ACCEL_ADDRESS, ACCEL_AXES_REG, 6, accel_axes) != 6) { printf("Unable to read from accel device\n"); } accel_values[0] = (__s16)(accel_axes[1]<<8 | accel_axes[0]); accel_values[1] = (__s16)(accel_axes[3]<<8 | accel_axes[2]); accel_values[2] = (__s16)(accel_axes[5]<<8 | accel_axes[4]); if(i2c_read(file, MAGNET_ADDRESS, MAGNET_AXES_REG, 6, magnet_axes) != 6) { printf("Unable to read from magnet device\n"); } magnet_values[0] = (__s16)(magnet_axes[1]<<8 | magnet_axes[0]); magnet_values[2] = (__s16)(magnet_axes[3]<<8 | magnet_axes[2]); magnet_values[1] = (__s16)(magnet_axes[5]<<8 | magnet_axes[4]); if(i2c_read(file, GYRO_ADDRESS, GYRO_AXES_REG, 6, gyro_axes) != 6) { printf("Unable to read from gyro device\n"); } gyro_values[0] = (__s16)(gyro_axes[1]<<8 | gyro_axes[0]); gyro_values[1] = (__s16)(gyro_axes[3]<<8 | gyro_axes[2]); gyro_values[2] = (__s16)(gyro_axes[5]<<8 | gyro_axes[4]); printf("a: %06hi, %06hi, %06hi m: %06hi, %06hi, %06hi g:%06hi, %06hi, %06hi \n", accel_values[0], accel_values[1], accel_values[2], magnet_values[0], magnet_values[1], magnet_values[2], gyro_values[0], gyro_values[1], gyro_values[2]); } if (i2c_close(file) != 0) { printf("Unable to close i2c bus.\n"); } return 0; }
int main(int argc, char *argv[]) { int fd, i; unsigned char value; unsigned char wbuf[] = { 0x11, 0x22, 0x33, 0x44, 0x55 }; unsigned char rbuf[sizeof(wbuf)]; // 打开i2c总线1,需要根据具体情况来的打开 fd = i2c_open_dev(1); if (fd < 0) { // 打开失败,可能是没有该i2c总线 printf("open i2c fail %d\n", fd); exit(1); } // 设置i2c从设备地址为0x22 if(i2c_change_slave(fd, 0x22)<0){ printf("set slave failed\n"); close(fd); exit(2); } printf("byte test...\n"); // 单字节写入 printf("write..\n"); for(i=0; i<256; ++i){ value = i; if(i2c_write(fd, i, value)==1){ // 写入成功 printf("[%02x]=%02x ", i, value); } else{ // 写入失败 printf("[%02x]=XX ", i); } if(i%8==7) printf("\n"); } // 读取 printf("read..\n"); for(i=0; i<256; ++i){ if(i2c_read(fd, i, &value)==1){ // 读取成功 printf("[%02x]=%02x ", i, value); } else{ // 读取失败 printf("[%02x]=XX ", i); } if(i%8==7) printf("\n"); } printf("block test...\n"); // 块写入 if(i2c_write_block(fd, 0, wbuf, sizeof(wbuf))!=sizeof(wbuf)){ printf("i2c_write_block failed\n"); } // 块读出 if(i2c_read_block(fd, 0, rbuf, sizeof(rbuf))!=sizeof(rbuf)){ printf("i2c_read_block failed\n"); } else{ for(i=0; i<sizeof(rbuf); ++i){ printf("r[%02x]=%02x\n", i, rbuf[i]); } } // 最后关闭文件 close(fd); return 0; }
void r360_i2c_lcd_write (uchar data0, uchar data1) { if (i2c_write (CONFIG_SYS_I2C_LCD_ADDR, data0, 1, &data1, 1)) { printf("Can't write lcd data 0x%02X 0x%02X.\n", data0, data1); } }
//Write 8bit data to register with 8bit address void Gyroscope::cmr_write(byte address, byte data) { i2c_start_wait( (ADDR << 1) | I2C_WRITE ); // Start / Device address and Write (0) i2c_write(address); // 8bit register address i2c_write(data); // 8 bit data i2c_stop(); // End condition }
int cros_ec_i2c_command(struct cros_ec_dev *dev, uint8_t cmd, int cmd_version, const uint8_t *dout, int dout_len, uint8_t **dinp, int din_len) { int old_bus = 0; /* version8, cmd8, arglen8, out8[dout_len], csum8 */ int out_bytes = dout_len + 4; /* response8, arglen8, in8[din_len], checksum8 */ int in_bytes = din_len + 3; uint8_t *ptr; /* Receive input data, so that args will be dword aligned */ uint8_t *in_ptr; int ret; old_bus = i2c_get_bus_num(); /* * Sanity-check I/O sizes given transaction overhead in internal * buffers. */ if (out_bytes > sizeof(dev->dout)) { debug("%s: Cannot send %d bytes\n", __func__, dout_len); return -1; } if (in_bytes > sizeof(dev->din)) { debug("%s: Cannot receive %d bytes\n", __func__, din_len); return -1; } assert(dout_len >= 0); assert(dinp); /* * Copy command and data into output buffer so we can do a single I2C * burst transaction. */ ptr = dev->dout; /* * in_ptr starts of pointing to a dword-aligned input data buffer. * We decrement it back by the number of header bytes we expect to * receive, so that the first parameter of the resulting input data * will be dword aligned. */ in_ptr = dev->din + sizeof(int64_t); if (!dev->cmd_version_is_supported) { /* Send an old-style command */ *ptr++ = cmd; out_bytes = dout_len + 1; in_bytes = din_len + 2; in_ptr--; /* Expect just a status byte */ } else { *ptr++ = EC_CMD_VERSION0 + cmd_version; *ptr++ = cmd; *ptr++ = dout_len; in_ptr -= 2; /* Expect status, length bytes */ } memcpy(ptr, dout, dout_len); ptr += dout_len; if (dev->cmd_version_is_supported) *ptr++ = (uint8_t) cros_ec_calc_checksum(dev->dout, dout_len + 3); /* Set to the proper i2c bus */ if (i2c_set_bus_num(dev->bus_num)) { debug("%s: Cannot change to I2C bus %d\n", __func__, dev->bus_num); return -1; } /* Send output data */ cros_ec_dump_data("out", -1, dev->dout, out_bytes); ret = i2c_write(dev->addr, 0, 0, dev->dout, out_bytes); if (ret) { debug("%s: Cannot complete I2C write to 0x%x\n", __func__, dev->addr); ret = -1; } if (!ret) { ret = i2c_read(dev->addr, 0, 0, in_ptr, in_bytes); if (ret) { debug("%s: Cannot complete I2C read from 0x%x\n", __func__, dev->addr); ret = -1; } } /* Return to original bus number */ i2c_set_bus_num(old_bus); if (ret) return ret; if (*in_ptr != EC_RES_SUCCESS) { debug("%s: Received bad result code %d\n", __func__, *in_ptr); return -(int)*in_ptr; } if (dev->cmd_version_is_supported) { int len, csum; len = in_ptr[1]; if (len + 3 > sizeof(dev->din)) { debug("%s: Received length %#02x too large\n", __func__, len); return -1; } csum = cros_ec_calc_checksum(in_ptr, 2 + len); if (csum != in_ptr[2 + len]) { debug("%s: Invalid checksum rx %#02x, calced %#02x\n", __func__, in_ptr[2 + din_len], csum); return -1; } din_len = min(din_len, len); cros_ec_dump_data("in", -1, in_ptr, din_len + 3); } else { cros_ec_dump_data("in (old)", -1, in_ptr, in_bytes); } /* Return pointer to dword-aligned input data, if any */ *dinp = dev->din + sizeof(int64_t); return din_len; }
/* * Handle our "Vendor Extension" commands on endpoint 0. * If we handle this one, return non-zero. */ unsigned char app_vendor_cmd (void) { if (bRequestType == VRT_VENDOR_IN) { ///////////////////////////////// // handle the IN requests ///////////////////////////////// switch (bRequest) { case VRQ_GET_STATUS: //this is no longer done via FX2 -- the FPGA will be queried instead return 0; break; case VRQ_I2C_READ: if (!i2c_read (wValueL, EP0BUF, wLengthL)) return 0; EP0BCH = 0; EP0BCL = wLengthL; break; case VRQ_SPI_READ: return 0; case VRQ_FW_COMPAT: EP0BCH = 0; EP0BCL = 3; break; default: return 0; } } else if (bRequestType == VRT_VENDOR_OUT) { ///////////////////////////////// // handle the OUT requests ///////////////////////////////// switch (bRequest) { case VRQ_SET_LED: switch (wIndexL) { case 0: set_led_0 (wValueL); break; case 1: set_led_1 (wValueL); break; default: return 0; } break; case VRQ_FPGA_LOAD: switch (wIndexL) { // sub-command case FL_BEGIN: return fpga_load_begin (); case FL_XFER: get_ep0_data (); return fpga_load_xfer (EP0BUF, EP0BCL); case FL_END: return fpga_load_end (); default: return 0; } break; case VRQ_FPGA_SET_RESET: fpga_reset(wValueL); break; case VRQ_I2C_WRITE: get_ep0_data (); if (!i2c_write (wValueL, EP0BUF, EP0BCL)) return 0; //SMINI_LED_REG ^= bmLED1; break; case VRQ_RESET_GPIF: clear_fifo(wValueL); break; case VRQ_ENABLE_GPIF: enable_xfers(wValueL); break; case VRQ_CLEAR_FPGA_FIFO: //clear_fpga_data_fifo(); break; default: return 0; } } else return 0; // invalid bRequestType return 1; }
static inline void isp1301_vbus_off(void) { i2c_write(OTG1_VBUS_DRV, ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR); }
/******************************************************************************* * Function: nunchuck_send_request() * Description: From how this function is used in the code I stole it from * it appears that this function simply resets the "read" register to 0. ******************************************************************************/ void nunchuck_send_request(void) { i2c_start(NUNCHUCK_ADDR+I2C_WRITE); i2c_write(0x00); i2c_stop(); }
int pmu_write_multiple(int address, int count, unsigned char* buffer) { return i2c_write(0xe6, address, count, buffer); }
void board_retimer_init(void) { u8 reg; /* Retimer is connected to I2C1_CH7_CH5 */ select_i2c_ch_pca9547(I2C_MUX_CH7); reg = I2C_MUX_CH5; i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, ®, 1); /* Access to Control/Shared register */ reg = 0x0; i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); /* Read device revision and ID */ i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1); debug("Retimer version id = 0x%x\n", reg); /* Enable Broadcast. All writes target all channel register sets */ reg = 0x0c; i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1); /* Reset Channel Registers */ i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1); reg |= 0x4; i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1); /* Enable override divider select and Enable Override Output Mux */ i2c_read(I2C_RETIMER_ADDR, 9, 1, ®, 1); reg |= 0x24; i2c_write(I2C_RETIMER_ADDR, 9, 1, ®, 1); /* Select VCO Divider to full rate (000) */ i2c_read(I2C_RETIMER_ADDR, 0x18, 1, ®, 1); reg &= 0x8f; i2c_write(I2C_RETIMER_ADDR, 0x18, 1, ®, 1); /* Selects active PFD MUX Input as Re-timed Data (001) */ i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1); reg &= 0x3f; reg |= 0x20; i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, ®, 1); /* Set data rate as 10.3125 Gbps */ reg = 0x0; i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1); reg = 0xb2; i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1); reg = 0x90; i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1); reg = 0xb3; i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1); reg = 0xcd; i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1); /* Return the default channel */ select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT); }