/* Write ide CRU interface */ static void ide_cru_w(int offset, int data) { offset &= 7; switch (offset) { case 0: /* turn card on: handled by core */ break; case 1: /* enable SRAM or registers in 0x4000-0x40ff */ sram_enable = data; break; case 2: /* enable SRAM page switching */ case 3: /* force SRAM page 0 */ case 4: /* enable SRAM in 0x6000-0x7000 ("RAMBO" mode) */ case 5: /* write-protect RAM */ case 6: /* irq and reset enable */ case 7: /* reset drive */ if (data) cru_register |= 1 << offset; else cru_register &= ~ (1 << offset); if (offset == 6) ti99_peb_set_ila_bit(inta_ide_bit, (cru_register & cru_reg_int_en) && ide_irq); if ((offset == 6) || (offset == 7)) if ((cru_register & cru_reg_int_en) && !(cru_register & cru_reg_reset)) ide_controller_reset(0); break; } }
static MACHINE_RESET( kinst ) { /* set the fastest DRC options */ cpunum_set_info_int(0, CPUINFO_INT_MIPS3_DRC_OPTIONS, MIPS3DRC_FASTEST_OPTIONS); /* configure fast RAM regions for DRC */ cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_SELECT, 0); cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_START, 0x08000000); cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_END, 0x087fffff); cpunum_set_info_ptr(0, CPUINFO_PTR_MIPS3_FASTRAM_BASE, rambase2); cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_READONLY, 0); cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_SELECT, 1); cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_START, 0x00000000); cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_END, 0x0007ffff); cpunum_set_info_ptr(0, CPUINFO_PTR_MIPS3_FASTRAM_BASE, rambase); cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_READONLY, 0); cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_SELECT, 2); cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_START, 0x1fc00000); cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_END, 0x1fc7ffff); cpunum_set_info_ptr(0, CPUINFO_PTR_MIPS3_FASTRAM_BASE, rombase); cpunum_set_info_int(0, CPUINFO_INT_MIPS3_FASTRAM_READONLY, 1); /* keep the DCS held in reset at startup */ dcs_reset_w(1); /* reset the IDE controller */ ide_controller_reset(0); /* set a safe base location for video */ video_base = &rambase[0x30000/4]; }
/* ide_hd_unload() Unload an IDE hard disk image img: parameter passed by the MESS image code to the load function which_bus: IDE bus the drive is attached to (only bus 0 is supported now) which_address: address of the drive on the bus (0->master, 1->slave, only master is supported now) intf: ide_interface required by the idectrl.c core */ void ide_hd_unload(mess_image *img, int which_bus, int which_address, struct ide_interface *intf) { assert(which_address == 0); device_unload_mess_hd(img); ide_controller_init_custom(which_bus, intf, NULL); ide_controller_reset(which_bus); }
/* ide_hd_init() Init an IDE hard disk device img: parameter passed by the MESS image code to the init function which_bus: IDE bus the drive is attached to (only bus 0 is supported now) which_address: address of the drive on the bus (0->master, 1->slave, only master is supported now) intf: ide_interface required by the idectrl.c core */ int ide_hd_init(mess_image *img, int which_bus, int which_address, struct ide_interface *intf) { assert(which_address == 0); if (device_init_mess_hd(img) == INIT_PASS) { ide_controller_init_custom(which_bus, intf, NULL); ide_controller_reset(which_bus); } return INIT_PASS; }
/* ide_hd_load() Load an IDE hard disk image img: parameter passed by the MESS image code to the load function which_bus: IDE bus the drive is attached to (only bus 0 is supported now) which_address: address of the drive on the bus (0->master, 1->slave, only master is supported now) intf: ide_interface required by the idectrl.c core */ int ide_hd_load(mess_image *img, int which_bus, int which_address, struct ide_interface *intf) { assert(which_address == 0); if (device_load_mess_hd(img, image_fp(img)) == INIT_PASS) { ide_controller_init_custom(which_bus, intf, mess_hd_get_chd_file(img)); ide_controller_reset(which_bus); return INIT_PASS; } return INIT_FAIL; }
static MACHINE_INIT( kinst ) { /* set the fastest DRC options */ cpunum_set_info_int(0, CPUINFO_INT_MIPS3_DRC_OPTIONS, MIPS3DRC_FASTEST_OPTIONS); /* both games map one logical 4k page at address 0 to physical address 0x8090000 */ memory_install_read32_handler(0, ADDRESS_SPACE_PROGRAM, 0x00000000, 0x00000fff, 0, 0, MRA32_BANK1); memory_install_write32_handler(0, ADDRESS_SPACE_PROGRAM, 0x00000000, 0x00000fff, 0, 0, MWA32_BANK1); cpu_setbank(1, &rambase2[0x90000/4]); /* keep the DCS held in reset at startup */ dcs_reset_w(1); /* reset the IDE controller */ ide_controller_reset(0); /* set a safe base location for video */ video_base = &rambase[0x30000/4]; }
static void reset_callback(int param) { ide_controller_reset(param); }
/* ide_machine_init() Perform machine initialization for an IDE hard disk device which_bus: IDE bus the drive is attached to (only bus 0 is supported now) which_address: address of the drive on the bus (0->master, 1->slave, only master is supported now) intf: ide_interface required by the idectrl.c core */ void ide_hd_machine_init(int which_bus, int which_address, struct ide_interface *intf) { assert(which_address == 0); ide_controller_reset(which_bus); }