/* Tell the PIXIS where to find the COREPLL, MPXPLL, SYSCLK values * * The PIXIS can be programmed to look at either the on-board dip switches * or various other PIXIS registers to determine the values for COREPLL, * MPXPLL, and SYSCLK. * * CONFIG_SYS_PIXIS_VCFGEN0_ENABLE is the value to write to the PIXIS_VCFGEN0 * register that tells the pixis to use the various PIXIS register. */ static void read_from_px_regs(int set) { u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0); if (set) tmp = tmp | CONFIG_SYS_PIXIS_VCFGEN0_ENABLE; else tmp = tmp & ~CONFIG_SYS_PIXIS_VCFGEN0_ENABLE; out_8(pixis_base + PIXIS_VCFGEN0, tmp); }
int serial_getc_dev(unsigned int idx) { volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx]; /* Wait for a character to arrive. */ while (in_be32(&psc->rfstat) & PSC_FIFO_EMPTY) ; return in_8(&psc->rfdata_8); }
static void dump_iic_regs(const char* header, struct ibm_iic_private* dev) { volatile struct iic_regs __iomem *iic = dev->vaddr; printk(KERN_DEBUG "ibm-iic%d: %s\n", dev->idx, header); printk(KERN_DEBUG " cntl = 0x%02x, mdcntl = 0x%02x\n" " sts = 0x%02x, extsts = 0x%02x\n" " clkdiv = 0x%02x, xfrcnt = 0x%02x\n" " xtcntlss = 0x%02x, directcntl = 0x%02x\n", in_8(&iic->cntl), in_8(&iic->mdcntl), in_8(&iic->sts), in_8(&iic->extsts), in_8(&iic->clkdiv), in_8(&iic->xfrcnt), in_8(&iic->xtcntlss), in_8(&iic->directcntl)); }
void pq2_restart(char *cmd) { local_irq_disable(); setbits32(&cpm2_immr->im_clkrst.car_rmr, RMR_CSRE); /* Clear the ME,EE,IR & DR bits in MSR to cause checkstop */ mtmsr(mfmsr() & ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR)); in_8(&cpm2_immr->im_clkrst.res[0]); panic("Restart failed\n"); }
int readb(volatile unsigned char *addr) { u8 val; unsigned long pa = iopa((unsigned long) addr); if (!is_pci_mem(pa)) return in_8(addr); idma_pci9_read((u8 *)&val, (u8 *)pa, sizeof(val), sizeof(val), 0); return val; }
static int mpc5121_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) { struct mpc5121_rtc_data *rtc = dev_get_drvdata(dev); struct mpc5121_rtc_regs __iomem *regs = rtc->regs; *alarm = rtc->wkalarm; alarm->pending = in_8(®s->alm_status); return 0; }
int mpc52xx_set_wakeup_gpio(u8 pin, u8 level) { u16 tmp; /* enable gpio */ out_8(&gpiow->wkup_gpioe, in_8(&gpiow->wkup_gpioe) | (1 << pin)); /* set as input */ out_8(&gpiow->wkup_ddr, in_8(&gpiow->wkup_ddr) & ~(1 << pin)); /* enable deep sleep interrupt */ out_8(&gpiow->wkup_inten, in_8(&gpiow->wkup_inten) | (1 << pin)); /* low/high level creates wakeup interrupt */ tmp = in_be16(&gpiow->wkup_itype); tmp &= ~(0x3 << (pin * 2)); tmp |= (!level + 1) << (pin * 2); out_be16(&gpiow->wkup_itype, tmp); /* master enable */ out_8(&gpiow->wkup_maste, 1); return 0; }
/* Configure the source of the boot location * * The PIXIS can be programmed to look at either the on-board dip switches * or the PX_VBOOT[LBMAP] register to determine where we should boot. * * If we want to boot from the alternate boot bank, we need to tell the PIXIS * to ignore the on-board dip switches and use the PX_VBOOT[LBMAP] instead. */ static void read_from_px_regs_altbank(int set) { u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1); if (set) tmp = tmp | CONFIG_SYS_PIXIS_VBOOT_ENABLE; else tmp = tmp & ~CONFIG_SYS_PIXIS_VBOOT_ENABLE; out_8(pixis_base + PIXIS_VCFGEN1, tmp); }
static int macio_adb_reset_bus(void) { unsigned long flags; int timeout = 1000000; /* Hrm... we may want to not lock interrupts for so * long ... oh well, who uses that chip anyway ? :) * That function will be seldomly used during boot * on rare machines, so... */ spin_lock_irqsave(&macio_lock, flags); out_8(&adb->ctrl.r, in_8(&adb->ctrl.r) | ADB_RST); while ((in_8(&adb->ctrl.r) & ADB_RST) != 0) { if (--timeout == 0) { out_8(&adb->ctrl.r, in_8(&adb->ctrl.r) & ~ADB_RST); return -1; } } spin_unlock_irqrestore(&macio_lock, flags); return 0; }
void read_from_px_regs_altbank(int set) { u8 *pixis_base = (u8 *)PIXIS_BASE; u8 mask = 0x04; /* FLASHBANK and FLASHMAP controlled by PIXIS */ u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1); if (set) tmp = tmp | mask; else tmp = tmp & ~mask; out_8(pixis_base + PIXIS_VCFGEN1, tmp); }
void read_from_px_regs(int set) { u8 *pixis_base = (u8 *)PIXIS_BASE; u8 mask = 0x1C; /* COREPLL, MPXPLL, SYSCLK controlled by PIXIS */ u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0); if (set) tmp = tmp | mask; else tmp = tmp & ~mask; out_8(pixis_base + PIXIS_VCFGEN0, tmp); }
static int spi_ppc4xx_setupxfer(struct spi_device *spi, struct spi_transfer *t) { struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master); struct spi_ppc4xx_cs *cs = spi->controller_state; int scr; u8 cdm = 0; u32 speed; u8 bits_per_word; /* Start with the generic configuration for this device. */ bits_per_word = spi->bits_per_word; speed = spi->max_speed_hz; /* * Modify the configuration if the transfer overrides it. Do not allow * the transfer to overwrite the generic configuration with zeros. */ if (t) { if (t->bits_per_word) bits_per_word = t->bits_per_word; if (t->speed_hz) speed = min(t->speed_hz, spi->max_speed_hz); } if (!speed || (speed > spi->max_speed_hz)) { dev_err(&spi->dev, "invalid speed_hz (%d)\n", speed); return -EINVAL; } /* Write new configuration */ out_8(&hw->regs->mode, cs->mode); /* Set the clock */ /* opb_freq was already divided by 4 */ scr = (hw->opb_freq / speed) - 1; if (scr > 0) cdm = min(scr, 0xff); dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", cdm, speed); if (in_8(&hw->regs->cdm) != cdm) out_8(&hw->regs->cdm, cdm); spin_lock(&hw->bitbang.lock); if (!hw->bitbang.busy) { hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE); /* Need to ndelay here? */ } spin_unlock(&hw->bitbang.lock); return 0; }
static int indirect_pci_read_config_byte( unsigned char bus, unsigned char slot, unsigned char function, unsigned char offset, uint8_t *val ) { PCI_CONFIG_SET_ADDR(pci.pci_config_addr, bus, slot, function, offset); *val = in_8(pci.pci_config_data + (offset&3)); return PCIBIOS_SUCCESSFUL; }
static int nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) { int i; struct nand_chip *chip = mtd->priv; for (i = 0; i < len; i++) { if (buf[i] != in_8(chip->IO_ADDR_R)) return -EFAULT; } return 0; }
int checkboard(void) { volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm; u8 *pixis_base = (u8 *)PIXIS_BASE; printf ("Board: MPC8610HPCD, System ID: 0x%02x, " "System Version: 0x%02x, FPGA Version: 0x%02x\n", in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), in_8(pixis_base + PIXIS_PVER)); mcm->abcr |= 0x00010000; /* 0 */ mcm->hpmr3 = 0x80000008; /* 4c */ mcm->hpmr0 = 0; mcm->hpmr1 = 0; mcm->hpmr2 = 0; mcm->hpmr4 = 0; mcm->hpmr5 = 0; return 0; }
static int do_sw_stat(cmd_tbl_t* cmd_tp, int flags, int argc, char * const argv[]) { char stat; int i; stat = in_8((u8 *) CPLD_REG0_ADDR); printf("SW2 status: "); for (i=0; i<4; i++) /* 4-position */ printf("%d:%s ", i, stat & (0x08 >> i)?"on":"off"); printf("\n"); return 0; }
static int fhci_dfs_regs_show(struct seq_file *s, void *v) { struct fhci_hcd *fhci = s->private; struct fhci_regs __iomem *regs = fhci->regs; seq_printf(s, "mode: 0x%x\n" "addr: 0x%x\n" "command: 0x%x\n" "ep0: 0x%x\n" "event: 0x%x\n" "mask: 0x%x\n" "status: 0x%x\n" "SOF timer: %d\n" "frame number: %d\n" "lines status: 0x%x\n", in_8(®s->usb_mod), in_8(®s->usb_addr), in_8(®s->usb_comm), in_be16(®s->usb_ep[0]), in_be16(®s->usb_event), in_be16(®s->usb_mask), in_8(®s->usb_status), in_be16(®s->usb_sof_tmr), in_be16(®s->usb_frame_num), fhci_ioports_check_bus_state(fhci)); return 0; }
static char macscsi_read(struct Scsi_Host *instance, int reg) { int iobase = instance->io_port; int i; int *ctrl = &((struct NCR5380_hostdata *)instance->hostdata)->ctrl; CTRL(iobase, 0); i = in_8(iobase + (reg<<4)); CTRL(iobase, 0x40); return i; }
static int indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) { struct pci_controller *hose = pci_bus_to_host(bus); volatile void __iomem *cfg_data; u8 cfg_type = 0; u32 bus_no, reg; if (hose->indirect_type & INDIRECT_TYPE_NO_PCIE_LINK) { if (bus->number != hose->first_busno) return PCIBIOS_DEVICE_NOT_FOUND; if (devfn != 0) return PCIBIOS_DEVICE_NOT_FOUND; } if (hose->indirect_type & INDIRECT_TYPE_SET_CFG_TYPE) if (bus->number != hose->first_busno) cfg_type = 1; bus_no = (bus->number == hose->first_busno) ? hose->self_busno : bus->number; if (hose->indirect_type & INDIRECT_TYPE_EXT_REG) reg = ((offset & 0xf00) << 16) | (offset & 0xfc); else reg = offset & 0xfc; /* Only 3 bits for function */ if (hose->indirect_type & INDIRECT_TYPE_BIG_ENDIAN) out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | (devfn << 8) | reg | cfg_type)); else out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) | (devfn << 8) | reg | cfg_type)); /* * Note: the caller has already checked that offset is * suitably aligned and that len is 1, 2 or 4. */ cfg_data = hose->cfg_data + (offset & 3); /* Only 3 bits for function */ switch (len) { case 1: *val = in_8(cfg_data); break; case 2: *val = in_le16(cfg_data); break; default: *val = in_le32(cfg_data); break; } return PCIBIOS_SUCCESSFUL; }
static void lcd_puts(char *s) { char *p = s; int i = 100; while (i--) { if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/ udelay(50); break; } udelay(50); } if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) { printf("LCD is busy\n"); return; } while (*p) lcd_putc(*p++); }
static void __init ls_uart_init(void) { local_irq_disable(); #ifndef CONFIG_SERIAL_8250 out_8(avr_addr + UART_FCR, UART_FCR_ENABLE_FIFO); /* enable FIFO */ out_8(avr_addr + UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); /* clear FIFOs */ out_8(avr_addr + UART_FCR, 0); out_8(avr_addr + UART_IER, 0); /* Clear up interrupts */ (void) in_8(avr_addr + UART_LSR); (void) in_8(avr_addr + UART_RX); (void) in_8(avr_addr + UART_IIR); (void) in_8(avr_addr + UART_MSR); #endif avr_uart_configure(); local_irq_enable(); }
static int hpfb_sync(struct fb_info *info) { while (in_8(fb_regs + BUSY) & fb_bitmask) ; out_8(fb_regs + TC_WEN, fb_bitmask); out_8(fb_regs + TC_PRR, RR_COPY); out_8(fb_regs + TC_FBEN, fb_bitmask); return 0; }
int misc_init_r(void) { u8 tmp_val, version; u8 *pixis_base = (u8 *)PIXIS_BASE; /*Do not use 8259PIC*/ tmp_val = in_8(pixis_base + PIXIS_BRDCFG0); out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80); /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/ version = in_8(pixis_base + PIXIS_PVER); if(version >= 0x07) { tmp_val = in_8(pixis_base + PIXIS_BRDCFG0); out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf); } /* Using this for DIU init before the driver in linux takes over * Enable the TFP410 Encoder (I2C address 0x38) */ tmp_val = 0xBF; i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); /* Verify if enabled */ tmp_val = 0; i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val)); debug("DVI Encoder Read: 0x%02lx\n",tmp_val); tmp_val = 0x10; i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); /* Verify if enabled */ tmp_val = 0; i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); debug("DVI Encoder Read: 0x%02lx\n",tmp_val); #ifdef CONFIG_FSL_DIU_FB mpc8610hpcd_diu_init(); #endif return 0; }
int checkboard (void) { u8 sw; struct cpu_type *cpu = gd->cpu; printf("Board: %sDS, ", cpu->name); printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver)); sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH)); sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT; if (sw < 0x8) printf("vBank: %d\n", sw); else if (sw == 0x8) puts("Promjet\n"); else if (sw == 0x9) puts("NAND\n"); else printf("invalid setting of SW%u\n", PIXIS_LBMAP_SWITCH); #ifdef CONFIG_PHYS_64BIT puts("36-bit Addressing\n"); #endif /* Display the actual SERDES reference clocks as configured by the * dip switches on the board. Note that the SWx registers could * technically be set to force the reference clocks to match the * values that the SERDES expects (or vice versa). For now, however, * we just display both values and hope the user notices when they * don't match. */ puts("SERDES Reference Clocks: "); sw = in_8(&PIXIS_SW(3)); printf("Bank1=%uMHz ", (sw & 0x40) ? 125 : 100); printf("Bank2=%sMHz ", (sw & 0x20) ? "156.25" : "125"); printf("Bank3=%sMHz\n", (sw & 0x10) ? "156.25" : "125"); return 0; }
static int uart_post_init (struct NS16550 *com_port) { unsigned long reg = 0; unsigned long udiv; unsigned short bdiv; #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK unsigned long tmp; #endif int i; for (i = 0; i < 3500; i++) { if (in_8(&com_port->lsr) & UART_LSR_THRE) break; udelay (100); } MFREG(UART0_SDR, reg); reg &= ~CR0_MASK; #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK reg |= CR0_EXTCLK_ENA; udiv = 1; tmp = gd->baudrate * 16; bdiv = (CONFIG_SYS_EXT_SERIAL_CLOCK + tmp / 2) / tmp; #else /* For 440, the cpu clock is on divider chain A, UART on divider * chain B ... so cpu clock is irrelevant. Get the "optimized" * values that are subject to the 1/2 opb clock constraint */ serial_divs (gd->baudrate, &udiv, &bdiv); #endif reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */ /* * Configure input clock to baudrate generator for all * available serial ports here */ MTREG(UART0_SDR, reg); #if defined(UART1_SDR) MTREG(UART1_SDR, reg); #endif #if defined(UART2_SDR) MTREG(UART2_SDR, reg); #endif #if defined(UART3_SDR) MTREG(UART3_SDR, reg); #endif uart_post_init_common(com_port, bdiv); return 0; }
int serial_getc () { unsigned char status = 0; while (1) { status = in_8((u8 *)asyncLSRport1); if ((status & asyncLSRDataReady) != 0x0) { break; } if ((status & ( asyncLSRFramingError | asyncLSROverrunError | asyncLSRParityError | asyncLSRBreakInterrupt )) != 0) { (void) out_8((u8 *)asyncLSRport1, asyncLSRFramingError | asyncLSROverrunError | asyncLSRParityError | asyncLSRBreakInterrupt ); } } return (0x000000ff & (int) in_8((u8 *)asyncRxBufferport1)); }
static void uart_post_putc (struct NS16550 *com_port, char c) { int i; out_8(&com_port->thr, c); /* put character out */ /* Wait for transfer completion */ for (i = 0; i < 3500; i++) { if (in_8(&com_port->lsr) & UART_LSR_THRE) break; udelay (100); } }
static void lcd_put_logo(void) { int i = 100; char *p = amcc_logo; while (i--) { if ((in_8((u8 *) LCD_CMD_ADDR) & 0x80) != 0x80) { /*BF = 1 ?*/ udelay(50); break; } udelay(50); } if (in_8((u8 *) LCD_CMD_ADDR) & 0x80) { printf("LCD is busy\n"); return; } out_8((u8 *) LCD_CMD_ADDR, 0x80); while (*p) lcd_putc(*p++); }
int checkboard (void) { u8 vboot; u8 *pixis_base = (u8 *)PIXIS_BASE; puts("Board: MPC8536DS "); #ifdef CONFIG_PHYS_64BIT puts("(36-bit addrmap) "); #endif printf ("Sys ID: 0x%02x, " "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER), in_8(pixis_base + PIXIS_PVER)); vboot = in_8(pixis_base + PIXIS_VBOOT); switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) { case PIXIS_VBOOT_LBMAP_NOR0: puts ("vBank: 0\n"); break; case PIXIS_VBOOT_LBMAP_NOR1: puts ("vBank: 1\n"); break; case PIXIS_VBOOT_LBMAP_NOR2: puts ("vBank: 2\n"); break; case PIXIS_VBOOT_LBMAP_NOR3: puts ("vBank: 3\n"); break; case PIXIS_VBOOT_LBMAP_PJET: puts ("Promjet\n"); break; case PIXIS_VBOOT_LBMAP_NAND: puts ("NAND\n"); break; } return 0; }
void kgdb_serial_init (void) { u8 val; u16 br_reg; get_clocks (); br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) + 5) / 10; /* * Init onboard 16550 UART */ out_8((u8 *)ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */ out_8((u8 *)ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */ out_8((u8 *)ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */ out_8((u8 *)ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */ out_8((u8 *)ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */ out_8((u8 *)ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ val = in_8((u8 *)ACTING_UART1_BASE + UART_LSR); /* clear line status */ val = in_8((u8 *)ACTING_UART1_BASE + UART_RBR); /* read receive buffer */ out_8((u8 *)ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */ out_8((u8 *)ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */ }