static int gpu_get_target_freq(void) { int freq; struct kbase_device *kbdev = pkbdev; struct exynos_context *platform; platform = (struct exynos_context *) kbdev->platform_context; if (!platform) return -ENODEV; #ifdef CONFIG_MALI_T6XX_DVFS gpu_dvfs_decide_next_level(kbdev, platform->utilization); #endif /* CONFIG_MALI_T6XX_DVFS */ freq = platform->table[platform->step].clock; #ifdef CONFIG_CPU_THERMAL_IPA ipa_mali_dvfs_requested(freq); #endif #ifdef CONFIG_MALI_T6XX_DVFS if ((platform->max_lock > 0) && (freq > platform->max_lock)) freq = platform->max_lock; else if ((platform->min_lock > 0) && (freq < platform->min_lock)) freq = platform->min_lock; #endif /* CONFIG_MALI_T6XX_DVFS */ return freq; }
int gpu_dvfs_decide_next_freq(struct kbase_device *kbdev, int utilization) { unsigned long flags; struct exynos_context *platform = (struct exynos_context *) kbdev->platform_context; DVFS_ASSERT(platform); spin_lock_irqsave(&platform->gpu_dvfs_spinlock, flags); gpu_dvfs_decide_next_governor(platform); gpu_dvfs_get_next_level(platform, utilization); spin_unlock_irqrestore(&platform->gpu_dvfs_spinlock, flags); #ifdef CONFIG_CPU_THERMAL_IPA ipa_mali_dvfs_requested(platform->table[platform->step].clock); #endif /* CONFIG_CPU_THERMAL_IPA */ return platform->table[platform->step].clock; }