/* PantherPoint PCH Power Management init */ static void ppt_pm_init(struct device *dev) { printk(BIOS_DEBUG, "PantherPoint PM init\n"); pci_write_config8(dev, 0xa9, 0x47); RCBA32_AND_OR(0x2238, ~0UL, (1 << 0)); RCBA32_AND_OR(0x228c, ~0UL, (1 << 0)); RCBA16_AND_OR(0x1100, ~0UL, (1 << 13)|(1 << 14)); RCBA16_AND_OR(0x0900, ~0UL, (1 << 14)); RCBA32(0x2304) = 0xc03b8400; RCBA32_AND_OR(0x2314, ~0UL, (1 << 5)|(1 << 18)); RCBA32_AND_OR(0x2320, ~0UL, (1 << 15)|(1 << 1)); RCBA32_AND_OR(0x3314, ~0x1f, 0xf); RCBA32(0x3318) = 0x054f0000; RCBA32(0x3324) = 0x04000000; RCBA32_AND_OR(0x3340, ~0UL, 0xfffff); RCBA32_AND_OR(0x3344, ~0UL, (1 << 1)|(1 << 0)); RCBA32(0x3360) = 0x0001c000; RCBA32(0x3368) = 0x00061100; RCBA32(0x3378) = 0x7f8fdfff; RCBA32(0x337c) = 0x000003fd; RCBA32(0x3388) = 0x00001000; RCBA32(0x3390) = 0x0001c000; RCBA32(0x33a0) = 0x00000800; RCBA32(0x33b0) = 0x00001000; RCBA32(0x33c0) = 0x00093900; RCBA32(0x33cc) = 0x24653002; RCBA32(0x33d0) = 0x067388fe; RCBA32_AND_OR(0x33d4, 0xf000f000, 0x00670060); RCBA32(0x3a28) = 0x01010000; RCBA32(0x3a2c) = 0x01010404; RCBA32(0x3a80) = 0x01040000; RCBA32_AND_OR(0x3a84, ~0x0000ffff, 0x00001001); RCBA32_AND_OR(0x3a84, ~0UL, (1 << 24)); /* SATA 2/3 disabled */ RCBA32_AND_OR(0x3a88, ~0UL, (1 << 0)); /* SATA 4/5 disabled */ RCBA32(0x3a6c) = 0x00000001; RCBA32_AND_OR(0x2344, 0x00ffff00, 0xff00000c); RCBA32_AND_OR(0x80c, ~(0xff << 20), 0x11 << 20); RCBA32_AND_OR(0x33a4, ~0UL, (1 << 0)); RCBA32(0x33c8) = 0; RCBA32_AND_OR(0x21b0, ~0UL, 0xf); }
void lan_init(void) { u16 io_base = 0; struct device *ethernet_dev = NULL; /* Get NIC's IO base address */ ethernet_dev = dev_find_device(PANTHER_NIC_VENDOR_ID, PANTHER_NIC_DEVICE_ID, 0); if (ethernet_dev != NULL) { io_base = pci_read_config16(ethernet_dev, 0x10) & 0xfffe; /* * Battery life time - LAN PCIe should enter ASPM L1 to save * power when LAN connection is idle. * enable CLKREQ: LAN pci config space 0x81h=01 */ pci_write_config8(ethernet_dev, 0x81, 0x01); } if (io_base) { /* Program MAC address based on VPD data */ program_mac_address(io_base); /* * Program NIC LEDS * * RTL8105E Series EEPROM-Less Application Note, * Section 5.6 LED Mode Configuration * * Step1: Write C0h to I/O register 0x50 via byte access to * disable 'register protection' * Step2: Write xx001111b to I/O register 0x52 via byte access * (bit7 is LEDS1 and bit6 is LEDS0) * Step3: Write 0x00 to I/O register 0x50 via byte access to * enable 'register protection' */ outb(0xc0, io_base + 0x50); /* Disable protection */ outb((PANTHER_NIC_LED_MODE << 6) | 0x0f, io_base + 0x52); outb(0x00, io_base + 0x50); /* Enable register protection */ } }
static void ich7_enable_lpc(void) { // Enable Serial IRQ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); // decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0210); // decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1f0d); /* range 0x1600 - 0x167f */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x1601); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x007c); /* range 0x15e0 - 0x10ef */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x15e1); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x000c); /* range 0x1680 - 0x169f */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x1681); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x001c); }
static void ctrl_init(struct device *dev) { /* TODO: Fix some ordering issue fo V-link set Rx77[6] and PCI1_Rx4F[0] should to 1 */ /* C2P Read ACK Return Priority */ /* PCI CFG Address bits[27:24] are used as extended register address bit[11:8] */ pci_write_config8(dev, 0x47, 0x30); /* VT8237R specific configuration other SB are done in their own directories */ device_t devsb = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); if (devsb) { vt8237r_vlink_init(dev); vt8237r_cfg(dev, devsb); } }
static void ich7_enable_lpc(void) { int lpt_en = 0; if (read_option(lpt, 0) != 0) lpt_en = LPT_LPC_EN; // Enable Serial IRQ pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); // decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007); // decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN | FDD_LPC_EN| lpt_en | COMB_LPC_EN | COMA_LPC_EN); // Enable 0x02e0 - 0x2ff pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x001c02e1); // Enable 0x600 - 0x6ff pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x00fc0601); // Enable 0x68 - 0x6f pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x00040069); }
static void sio_setup(void) { uint32_t dword; uint8_t byte; enable_smbus(); // smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */ smbusx_write_byte(1, (0x58 >> 1), 0xb1, 0xff); /* set FAN ctrl to DC mode */ byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b); byte |= 0x20; pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, byte); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0); dword |= (1 << 0); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, dword); dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4); dword |= (1 << 16); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword); }
static void ide_init(struct device *dev) { /* Enable ide devices so the linux ide driver will work */ u32 dword; u8 byte; /* RPR10.1 disable MSI */ dword = pci_read_config32(dev, 0x70); dword &= ~(1 << 16); pci_write_config32(dev, 0x70, dword); /* Enable UDMA on all devices, it will become UDMA0 (default PIO is PIO0) */ byte = pci_read_config8(dev, 0x54); byte |= 0xf; pci_write_config8(dev, 0x54, byte); /* Enable I/O Access&& Bus Master */ dword = pci_read_config16(dev, 0x4); dword |= 1 << 2; pci_write_config16(dev, 0x4, dword); }
static void ich7_enable_lpc(void) { int lpt_en = 0; if (read_option(lpt, 0) != 0) { lpt_en = 1<<2; // enable LPT } // Enable Serial IRQ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); // Set COM1/COM2 decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); // Enable COM1/COM2/KBD/SuperIO1+2 pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b | lpt_en); // Enable HWM at 0xa00 pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0a01); // COM3 decode pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9); // COM4 decode pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9); // io 0x300 decode pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); }
static void enable_smbus(void) { uint32_t reg; const uint32_t smbus_dev = PCI_DEV(0, SMBUS_DEV, SMBUS_FUNC); /* SMBus I/O BAR */ reg = SMBUS_BASE_ADDRESS | 2; pci_write_config32(smbus_dev, PCI_BASE_ADDRESS_4, reg); /* Enable decode of I/O space. */ reg = pci_read_config16(smbus_dev, PCI_COMMAND); reg |= 0x1; pci_write_config16(smbus_dev, PCI_COMMAND, reg); /* Enable Host Controller */ reg = pci_read_config8(smbus_dev, 0x40); reg |= 1; pci_write_config8(smbus_dev, 0x40, reg); /* Configure pads to be used for SMBus */ score_select_func(PCU_SMB_CLK_PAD, 1); score_select_func(PCU_SMB_DATA_PAD, 1); }
/* * Enables several BARs and devices which are needed for memory init * - MCH_BASE_ADDR is needed in order to talk to the memory controller * - PMC_BAR0 and PMC_BAR1 are used by FSP (with the base address hardcoded) * Once raminit is done, we can safely let the allocator re-assign them * - HPET is enabled because FSP wants to store a pointer to global data in the * HPET comparator register */ static void soc_early_romstage_init(void) { device_t pmc = PMC_DEV; /* Set MCH base address and enable bit */ pci_write_config32(NB_DEV_ROOT, MCHBAR, MCH_BASE_ADDR | 1); /* Set PMC base addresses and enable decoding. */ pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PMC_BAR0); pci_write_config32(pmc, PCI_BASE_ADDRESS_1, 0); /* 64-bit BAR */ pci_write_config32(pmc, PCI_BASE_ADDRESS_2, PMC_BAR1); pci_write_config32(pmc, PCI_BASE_ADDRESS_3, 0); /* 64-bit BAR */ pci_write_config16(pmc, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE); pci_write_config16(pmc, PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); /* Enable decoding for HPET. Needed for FSP global pointer storage */ pci_write_config8(P2SB_DEV, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 | P2SB_HPTC_ADDRESS_ENABLE); }
void sdram_set_registers(void) { int i, max; uint8_t reg; PRINT_DEBUG("Northbridge prior to SDRAM init:\n"); DUMPNORTH(); max = ARRAY_SIZE(register_values); /* Set registers as specified in the register_values[] array. */ for (i = 0; i < max; i += 3) { reg = pci_read_config8(NB, register_values[i]); reg &= register_values[i + 1]; reg |= register_values[i + 2] & ~(register_values[i + 1]); pci_write_config8(NB, register_values[i], reg); #if 0 PRINT_DEBUG(" Set register 0x%02x to 0x%02x\n", register_values[i], reg); #endif } }
/*This routine process the ability for North Bridge side burst functionality There are 3 variances that are valid: 1. DIMM BL=8, chipset BL=8 2. DIMM BL=4, chipset BL=4 3. DIMM BL=4, chipset BL=8 (only happened on Dual channel) Device 0 function 2 HOST:REG54[4] must be 1 when 128-bit mode. Since DIMM will be initialized in each rank individually, 1.If all DIMM BL=4, DIMM will initialize BL=4 first, then check dual_channel flag to enable VIA_NB2HOST_REG54[4]. 2.If all DIMM BL=8, DIMM will initialize BL=8 first, then check dual_channel flag for re-initialize DIMM BL=4. also VIA_NB2HOST_REG54[4] need to be enabled. Chipset_BL8==>chipset side can set burst length=8 two register need to set 1. Device 0 function 2 HOST:REG54[4] 2. Device 0 function 3 DRAM:REG6C[3] */ void DRAMBurstLength(DRAM_SYS_ATTR * DramAttr) { u8 Data, BL; u8 Sockets; /*SPD byte16 bit3,2 describes the burst length supported. bit3=1 support BL=8 bit2=1 support BL=4 */ BL = 0x0c; for (Sockets = 0; Sockets < 2; Sockets++) { if (DramAttr->DimmInfo[Sockets].bPresence) { BL &= (DramAttr-> DimmInfo[Sockets].SPDDataBuf [SPD_SDRAM_BURSTLENGTH]); } } /*D0F3Rx6c bit3 CHA SDRAM effective burst length, for 64bit mode ranks =0 BL=4 ; =1 BL=8 */ if (BL & 0x08) /*All Assembly support BL=8 */ BL = 0x8; /*set bit3 */ else BL = 0x00; /*clear bit3 */ Data = pci_read_config8(MEMCTRL, 0x6c); Data = (u8) ((Data & 0xf7) | BL); #if ENABLE_CHB if (DramAttr->RankNumChB > 0) { BL = DramAttr->DimmInfo[2].SPDDataBuf[SPD_SDRAM_BURSTLENGTH]; //Rx6c[1], CHB burst length if (BL & 0x08) /*CHB support BL=8 */ BL = 0x2; /*set bit1 */ else BL = 0x00; /*clear bit1 */ Data = (Data & 0xFD) | BL; } #endif pci_write_config8(MEMCTRL, 0x6c, Data); }
static void lpc_init(struct device *dev) { uint8_t scnt; struct soc_intel_apollolake_config *cfg; cfg = dev->chip_info; if (!cfg) { printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); return; } scnt = pci_read_config8(dev, REG_SERIRQ_CTL); scnt &= ~(SCNT_EN | SCNT_MODE); if (cfg->serirq_mode == SERIRQ_QUIET) scnt |= SCNT_EN; else if (cfg->serirq_mode == SERIRQ_CONTINUOUS) scnt |= SCNT_EN | SCNT_MODE; pci_write_config8(dev, REG_SERIRQ_CTL, scnt); /* Initialize RTC */ rtc_init(); }
static void ide_init(struct device *dev) { struct southbridge_nvidia_ck804_config *conf; u32 dword; u16 word; u8 byte; conf = dev->chip_info; word = pci_read_config16(dev, 0x50); /* Ensure prefetch is disabled. */ word &= ~((1 << 15) | (1 << 13)); if (conf->ide1_enable) { /* Enable secondary IDE interface. */ word |= (1 << 0); printk(BIOS_DEBUG, "IDE1 \t"); } if (conf->ide0_enable) { /* Enable primary IDE interface. */ word |= (1 << 1); printk(BIOS_DEBUG, "IDE0\n"); } word |= (1 << 12); word |= (1 << 14); pci_write_config16(dev, 0x50, word); byte = 0x20; /* Latency: 64 --> 32 */ pci_write_config8(dev, 0xd, byte); dword = pci_read_config32(dev, 0xf8); dword |= 12; pci_write_config32(dev, 0xf8, dword); #if CONFIG_PCI_ROM_RUN pci_dev_init(dev); #endif }
static void pch_rtc_init(void) { u8 reg8; int rtc_failed; /*PMC Controller Device 0x1F, Func 02*/ device_t dev = PCH_DEV_PMC; reg8 = pci_read_config8(dev, GEN_PMCON_B); rtc_failed = reg8 & RTC_BATTERY_DEAD; if (rtc_failed) { reg8 &= ~RTC_BATTERY_DEAD; pci_write_config8(dev, GEN_PMCON_B, reg8); printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed); } /* Ensure the date is set including century byte. */ cmos_check_update_date(); if (IS_ENABLED(CONFIG_VBOOT_VBNV_CMOS)) init_vbnv_cmos(rtc_failed); else cmos_init(rtc_failed); }
static UINT8 select_socket(UINT8 socket_id) { device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBus UINT8 value = 0; UINT8 gpio56_to_53 = 0; /* Configure GPIO54,53 to select the desired socket * GPIO54,53 control the HC4052 S1,S0 * S1 S0 true table * 0 0 channel 1 (Socket1) * 0 1 channel 2 (Socket2) * 1 0 channel 3 (Socket3) * 1 1 channel 4 (Socket4) */ gpio56_to_53 = pci_read_config8(sm_dev, PCI_REG_GPIO_56_to_53_CNTRL); value = gpio56_to_53 & (~GPIO_OUT_BIT_GPIO54_to_53_MASK); value |= socket_id; value &= (~GPIO_OUT_ENABLE_BIT_GPIO54_to_53_MASK); // 0=Output Enabled, 1=Tristate pci_write_config8(sm_dev, PCI_REG_GPIO_56_to_53_CNTRL, value); return gpio56_to_53; }
static void sio_setup(void) { unsigned value; uint32_t dword; uint8_t byte; pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400); byte = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b); byte |= 0x20; pci_write_config8(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0x7b, byte); dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0); dword |= (1<<29)|(1<<0); pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77); value &= 0xbf; lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value); }
static int pch_pirq_init(const void *blob, int node, pci_dev_t dev) { uint8_t route[8], *ptr; if (fdtdec_get_byte_array(blob, node, "intel,pirq-routing", route, sizeof(route))) return -EINVAL; ptr = route; pci_write_config8(dev, PIRQA_ROUT, *ptr++); pci_write_config8(dev, PIRQB_ROUT, *ptr++); pci_write_config8(dev, PIRQC_ROUT, *ptr++); pci_write_config8(dev, PIRQD_ROUT, *ptr++); pci_write_config8(dev, PIRQE_ROUT, *ptr++); pci_write_config8(dev, PIRQF_ROUT, *ptr++); pci_write_config8(dev, PIRQG_ROUT, *ptr++); pci_write_config8(dev, PIRQH_ROUT, *ptr++); /* * TODO([email protected]): U-Boot does not set up the interrupts * here. It's unclear if it is needed */ return 0; }
static void mb_lpc_setup(void) { u32 reg32; /* Set the value for GPIO base address register and enable GPIO. */ pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); setup_pch_gpios(&mainboard_gpio_map); /* Set GPIOs on superio, enable UART */ if (IS_ENABLED(CONFIG_SUPERIO_NUVOTON_NCT6776)) { nuvoton_pnp_enter_conf_state(SERIAL_DEV_R2); pnp_set_logical_device(SERIAL_DEV_R2); pnp_write_config(SERIAL_DEV_R2, 0x1c, 0x80); pnp_write_config(SERIAL_DEV_R2, 0x27, 0x80); pnp_write_config(SERIAL_DEV_R2, 0x2a, 0x60); nuvoton_pnp_exit_conf_state(SERIAL_DEV_R2); nuvoton_enable_serial(SERIAL_DEV_R2, CONFIG_TTYS0_BASE); } else { winbond_enable_serial(SERIAL_DEV_R1, CONFIG_TTYS0_BASE); } /* IRQ routing */ RCBA16(D31IR) = 0x0132; RCBA16(D29IR) = 0x0237; /* Enable IOAPIC */ RCBA8(OIC) = 0x03; RCBA8(OIC); reg32 = RCBA32(GCS); reg32 |= (1 << 5); RCBA32(GCS) = reg32; RCBA32(FD) = FD_PCIE6 | FD_PCIE5 | FD_PCIE4 | FD_PCIE3 | FD_ACMOD | FD_ACAUD | 1; RCBA32(CG) = 0x00000001; }
static void pch_enable_apic(struct device *dev) { int i; u32 reg32; volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR); volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10); /* Enable ACPI I/O and power management. * Set SCI IRQ to IRQ9 */ pci_write_config8(dev, ACPI_CNTL, 0x80); *ioapic_index = 0; *ioapic_data = (1 << 25); /* affirm full set of redirection table entries ("write once") */ *ioapic_index = 1; reg32 = *ioapic_data; *ioapic_index = 1; *ioapic_data = reg32; *ioapic_index = 0; reg32 = *ioapic_data; printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); if (reg32 != (1 << 25)) die("APIC Error\n"); printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); for (i=0; i<3; i++) { *ioapic_index = i; printk(BIOS_SPEW, " reg 0x%04x:", i); reg32 = *ioapic_data; printk(BIOS_SPEW, " 0x%08x\n", reg32); } *ioapic_index = 3; /* Select Boot Configuration register. */ *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ }
static void bcm5785_enable_wdt_port_cf9(void) { pci_devfn_t dev; uint32_t dword; uint32_t dword_old; dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); dword_old = pci_read_config32(dev, 0x4c); dword = dword_old | (1 << 4); //enable Timer Func if (dword != dword_old) pci_write_config32(dev, 0x4c, dword); dword_old = pci_read_config32(dev, 0x6c); dword = dword_old | (1 << 9); //unhide Timer Func in pci space if (dword != dword_old) pci_write_config32(dev, 0x6c, dword); dev = pci_locate_device(PCI_ID(0x1166, 0x0238), 0); /* enable cf9 */ pci_write_config8(dev, 0x40, 1 << 2); }
static void enable_smbus(void) { device_t dev; uint8_t enable; dev = pci_locate_device(PCI_ID(0x1022, 0x746b), 0); if (dev == PCI_DEV_INVALID) { die("SMBUS controller not found\n"); } pci_write_config32(dev, 0x58, SMBUS_IO_BASE | 1); enable = pci_read_config8(dev, 0x41); pci_write_config8(dev, 0x41, enable | (1 << 7)); /* check that we can see the smbus controller I/O. */ if (inw(SMBUS_IO_BASE)==0xFF){ die("SMBUS controller I/O not found\n"); } /* clear any lingering errors, so the transaction will run */ outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS); print_spew("SMBus controller enabled\n"); }
static void vt8231_enable_rom(void) { device_t dev; dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231), 0); /* * ROM decode control register (0x43): * * Bit Decode range * ----------------- * 7 0xFFFE0000-0xFFFEFFFF * 6 0xFFF80000-0xFFFDFFFF * 5 0xFFF00000-0xFFF7FFFF * 4 0x000E0000-0x000EFFFF * 3 0x000D8000-0x000DFFFF * 2 0x000D0000-0x000D7FFF * 1 0x000C8000-0x000CFFFF * 0 0x000C0000-0x000C7FFF */ pci_write_config8(dev, 0x43, (1 << 7) | (1 << 6) | (1 << 5)); }
void enable_pm(void) { device_t dev; u8 reg8; u16 reg16; /* Get the SMBus/PM device of the 82371AB/EB/MB. */ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_SMB_ACPI), 0); /* Set the PM I/O base. */ pci_write_config32(dev, PMBA, DEFAULT_PMBASE | 1); /* Enable access to the PM I/O space. */ reg16 = pci_read_config16(dev, PCI_COMMAND); reg16 |= PCI_COMMAND_IO; pci_write_config16(dev, PCI_COMMAND, reg16); /* PM I/O Space Enable (PMIOSE). */ reg8 = pci_read_config8(dev, PMREGMISC); reg8 |= PMIOSE; pci_write_config8(dev, PMREGMISC, reg8); }
void SetTrcd(DRAM_SYS_ATTR * DramAttr) { u8 Data; u16 Max, Tmp; u8 Socket; /*get the max Trcd value from SPD data SPD Byte29, Bit7:2->1ns~63ns, Bit1:0->0ns, 0.25ns, 0.50ns, 0.75ns */ Max = 0; for (Socket = 0; Socket < MAX_SOCKETS; Socket++) { if (DramAttr->DimmInfo[Socket].bPresence) { Tmp = (u16) (DramAttr-> DimmInfo[Socket].SPDDataBuf[SPD_SDRAM_TRCD]); if (Tmp > Max) Max = Tmp; } } /*Calculate clock,this value should be 2T,3T,4T,5T */ Tmp = (u16) CEIL_DIV(Max * 100, (DramAttr->DramCyc) << 2); PRINT_DEBUG_MEM("Trcd ="); PRINT_DEBUG_MEM_HEX16(Tmp); PRINT_DEBUG_MEM("\r"); if (Tmp > MAX_TRCD) Tmp = MAX_TRCD; else if (Tmp < MIN_TRCD) Tmp = MIN_TRCD; Tmp -= 2; //00->2T, 01->3T, 10->4T, 11->5T Tmp <<= 5; //bit5,6,7 Data = pci_read_config8(MEMCTRL, 0x64); Data = (u8) ((Data & 0x1f) | (u8) Tmp); pci_write_config8(MEMCTRL, 0x64, Data); }
void hudson_pci_port80(void) { u8 byte; pci_devfn_t dev; /* P2P Bridge */ dev = PCI_DEV(0, 0x14, 4); /* Chip Control: Enable subtractive decoding */ byte = pci_read_config8(dev, 0x40); byte |= 1 << 5; pci_write_config8(dev, 0x40, byte); /* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */ byte = pci_read_config8(dev, 0x4B); byte |= 1 << 7; pci_write_config8(dev, 0x4B, byte); /* The same IO Base and IO Limit here is meaningful because we set the * bridge to be subtractive. During early setup stage, we have to make * sure that data can go through port 0x80. */ /* IO Base: 0xf000 */ byte = pci_read_config8(dev, 0x1C); byte |= 0xF << 4; pci_write_config8(dev, 0x1C, byte); /* IO Limit: 0xf000 */ byte = pci_read_config8(dev, 0x1D); byte |= 0xF << 4; pci_write_config8(dev, 0x1D, byte); /* PCI Command: Enable IO response */ byte = pci_read_config8(dev, 0x04); byte |= 1 << 0; pci_write_config8(dev, 0x04, byte); /* LPC controller */ dev = PCI_DEV(0, 0x14, 3); byte = pci_read_config8(dev, 0x4A); byte &= ~(1 << 5); /* disable lpc port 80 */ pci_write_config8(dev, 0x4A, byte); }
static void haswell_setup_bars(void) { printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32); pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+DEFAULT_MCHBAR) >> 32); pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+(uintptr_t)DEFAULT_DMIBAR) >> 32); /* Set C0000-FFFFF to access RAM on both reads and writes */ pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30); pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33); pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33); pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33); pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33); pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); printk(BIOS_DEBUG, " done.\n"); }
static void usb_init(struct device *dev) { printk(BIOS_DEBUG, "USB 1.1 INIT:---------->\n"); //-------------- enable USB1.1 (SiS7001) ------------------------- { uint8_t temp8; int i=0; while(SiS_SiS7001_init[i][0] != 0) { temp8 = pci_read_config8(dev, SiS_SiS7001_init[i][0]); temp8 &= SiS_SiS7001_init[i][1]; temp8 |= SiS_SiS7001_init[i][2]; pci_write_config8(dev, SiS_SiS7001_init[i][0], temp8); i++; }; } //----------------------------------------------------------- #if DEBUG_USB { int i; printk(BIOS_DEBUG, "****** USB 1.1 PCI config ******"); printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C"); for(i=0;i<0xff;i+=4){ if((i%16)==0) printk(BIOS_DEBUG, "\n%02x: ", i); printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i)); } printk(BIOS_DEBUG, "\n"); } #endif printk(BIOS_DEBUG, "USB 1.1 INIT:<----------\n"); }
void SetTras(DRAM_SYS_ATTR * DramAttr) { u8 Data; u16 Max, Tmp; u8 Socket; /*get the max Tras value from SPD data SPD byte30: bit0:7 1ns~255ns */ Max = 0; for (Socket = 0; Socket < MAX_SOCKETS; Socket++) { if (DramAttr->DimmInfo[Socket].bPresence) { Tmp = (u16) (DramAttr-> DimmInfo[Socket].SPDDataBuf[SPD_SDRAM_TRAS]); if (Tmp > Max) Max = Tmp; } } /*Calculate clock,value range 5T-20T */ Tmp = (u16) CEIL_DIV((Max * 100), DramAttr->DramCyc); PRINT_DEBUG_MEM("Tras ="); PRINT_DEBUG_MEM_HEX16(Tmp); PRINT_DEBUG_MEM("\r"); if (Tmp > MAX_TRAS) Tmp = MAX_TRAS; else if (Tmp < MIN_TRAS) Tmp = MIN_TRAS; Tmp -= 5; //0->5T ... 1111->20T Tmp <<= 4; //bit4:7 Data = pci_read_config8(MEMCTRL, 0x62); Data = (u8) ((Data & 0x0f) | (u8) Tmp); pci_write_config8(MEMCTRL, 0x62, Data); }
static void usb_i_init(struct device *dev) { #if CONFIG_EPIA_VT8237R_INIT u8 reg8; printk(BIOS_DEBUG, "Entering %s\n", __func__); reg8 = pci_read_config8(dev, 0x04); printk(BIOS_SPEW, "%s Read %02X from PCI Command Reg\n", dev_path(dev), reg8); reg8 = reg8 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config8(dev, 0x04, reg8); printk(BIOS_SPEW, "%s Wrote %02X to PCI Command Reg\n", dev_path(dev), reg8); /* Set Cache Line Size and Latency Timer */ pci_write_config8(dev, 0x0c, 0x08); pci_write_config8(dev, 0x0d, 0x20); /* Enable Sub Device ID Back Door and set Generic */ reg8 = pci_read_config8(dev, 0x42); reg8 |= 0x10; pci_write_config8(dev, 0x42, reg8); pci_write_config16(dev, 0x2e, 0xAA07); reg8 &= ~0x10; pci_write_config8(dev, 0x42, reg8); pci_write_config8(dev, 0x41, 0x12); pci_write_config8(dev, 0x49, 0x0B); /* Clear PCI Status */ pci_write_config16(dev, 0x06, 0x7A10); #endif return; }