static int netx_eth_open(struct eth_device *edev) { struct netx_eth_priv *priv = (struct netx_eth_priv *)edev->priv; return phy_device_connect(edev, &priv->miibus, 0, NULL, 0, PHY_INTERFACE_MODE_NA); }
static int usbnet_open(struct eth_device *edev) { struct usbnet *dev = (struct usbnet*)edev->priv; dev_dbg(&edev->dev, "%s\n",__func__); return phy_device_connect(edev, &dev->miibus, dev->phy_addr, NULL, 0, PHY_INTERFACE_MODE_NA); }
static int arc_emac_open(struct eth_device *edev) { struct arc_emac_priv *priv = edev->priv; void *rxbuf; int ret, i; priv->last_rx_bd = 0; rxbuf = priv->rxbuf; /* Allocate and set buffers for Rx BD's */ for (i = 0; i < RX_BD_NUM; i++) { unsigned int *last_rx_bd = &priv->last_rx_bd; struct arc_emac_bd *rxbd = &priv->rxbd[*last_rx_bd]; rxbd->data = cpu_to_le32(rxbuf); /* Return ownership to EMAC */ rxbd->info = cpu_to_le32(FOR_EMAC | PKTSIZE); *last_rx_bd = (*last_rx_bd + 1) % RX_BD_NUM; rxbuf += PKTSIZE; } /* Clean Tx BD's */ memset(priv->txbd, 0, TX_RING_SZ); /* Initialize logical address filter */ arc_reg_set(priv, R_LAFL, 0x0); arc_reg_set(priv, R_LAFH, 0x0); /* Set BD ring pointers for device side */ arc_reg_set(priv, R_RX_RING, (unsigned int)priv->rxbd); arc_reg_set(priv, R_TX_RING, (unsigned int)priv->txbd); /* Set CONTROL */ arc_reg_set(priv, R_CTRL, (RX_BD_NUM << 24) | /* RX BD table length */ (TX_BD_NUM << 16) | /* TX BD table length */ TXRN_MASK | RXRN_MASK); /* Enable EMAC */ arc_reg_or(priv, R_CTRL, EN_MASK); ret = phy_device_connect(edev, priv->bus, -1, NULL, 0, PHY_INTERFACE_MODE_NA); if (ret) return ret; return 0; }
static int ar231x_eth_open(struct eth_device *edev) { struct ar231x_eth_priv *priv = edev->priv; u32 tmp; /* Enable RX. Now the rx_buffer will be filled. * If it is full we may lose first transmission. In this case * barebox should retry it. * Or TODO: - force HW to filter some how broadcasts * - disable RX if we do not need it. */ tmp = eth_readl(priv, AR231X_ETH_MAC_CONTROL); eth_writel(priv, (tmp | MAC_CONTROL_RE), AR231X_ETH_MAC_CONTROL); return phy_device_connect(edev, &priv->miibus, (int)priv->phy_regs, ar231x_adjust_link, 0, PHY_INTERFACE_MODE_MII); }
static int gfar_open(struct eth_device *edev) { int ix; struct gfar_private *priv = edev->priv; struct gfar_phy *phy = priv->gfar_mdio; void __iomem *regs = priv->regs; int ret; ret = phy_device_connect(edev, &phy->miibus, priv->phyaddr, gfar_adjust_link, 0, PHY_INTERFACE_MODE_NA); if (ret) return ret; /* Point to the buffer descriptors */ out_be32(regs + GFAR_TBASE0_OFFSET, (unsigned int)priv->txbd); out_be32(regs + GFAR_RBASE0_OFFSET, (unsigned int)priv->rxbd); /* Initialize the Rx Buffer descriptors */ for (ix = 0; ix < RX_BUF_CNT; ix++) { out_be16(&priv->rxbd[ix].status, RXBD_EMPTY); out_be16(&priv->rxbd[ix].length, 0); out_be32(&priv->rxbd[ix].bufPtr, (uint) NetRxPackets[ix]); } out_be16(&priv->rxbd[RX_BUF_CNT - 1].status, RXBD_EMPTY | RXBD_WRAP); /* Initialize the TX Buffer Descriptors */ for (ix = 0; ix < TX_BUF_CNT; ix++) { out_be16(&priv->txbd[ix].status, 0); out_be16(&priv->txbd[ix].length, 0); out_be32(&priv->txbd[ix].bufPtr, 0); } out_be16(&priv->txbd[TX_BUF_CNT - 1].status, TXBD_WRAP); /* Enable Transmit and Receive */ setbits_be32(regs + GFAR_MACCFG1_OFFSET, GFAR_MACCFG1_RX_EN | GFAR_MACCFG1_TX_EN); /* Tell the DMA it is clear to go */ setbits_be32(regs + GFAR_DMACTRL_OFFSET, DMACTRL_INIT_SETTINGS); out_be32(regs + GFAR_TSTAT_OFFSET, GFAR_TSTAT_CLEAR_THALT); out_be32(regs + GFAR_RSTAT_OFFSET, GFAR_RSTAT_CLEAR_RHALT); clrbits_be32(regs + GFAR_DMACTRL_OFFSET, GFAR_DMACTRL_GRS | GFAR_DMACTRL_GTS); return 0; }
static int at91_ether_open(struct eth_device *edev) { int i; unsigned long ctl; struct ether_device *etdev = to_ether(edev); unsigned char *rbf_framebuf = etdev->rbf_framebuf; int ret; ret = phy_device_connect(edev, &etdev->miibus, etdev->phy_addr, update_linkspeed, 0, etdev->interface); if (ret) return ret; /* Clear internal statistics */ ctl = at91_emac_read(AT91_EMAC_CTL); at91_emac_write(AT91_EMAC_CTL, ctl | AT91_EMAC_CSR); /* Init Ethernet buffers */ etdev->rbfp = etdev->rbfdt; for (i = 0; i < MAX_RX_DESCR; i++) { etdev->rbfp[i].addr = (unsigned long)rbf_framebuf; etdev->rbfp[i].size = 0; rbf_framebuf += MAX_RBUFF_SZ; } etdev->rbfp[i - 1].addr |= RBF_WRAP; /* Program address of descriptor list in Rx Buffer Queue register */ at91_emac_write(AT91_EMAC_RBQP, (unsigned long) etdev->rbfdt); ctl = at91_emac_read(AT91_EMAC_RSR); ctl &= ~(AT91_EMAC_RSR_OVR | AT91_EMAC_RSR_REC | AT91_EMAC_RSR_BNA); at91_emac_write(AT91_EMAC_RSR, ctl); ctl = at91_emac_read(AT91_EMAC_CFG); ctl |= AT91_EMAC_CAF | AT91_EMAC_NBC; at91_emac_write(AT91_EMAC_CFG, ctl); /* Enable Receive and Transmit */ ctl = at91_emac_read(AT91_EMAC_CTL); ctl |= AT91_EMAC_RE | AT91_EMAC_TE; at91_emac_write(AT91_EMAC_CTL, ctl); return 0; }
static int dwc_ether_open(struct eth_device *dev) { struct dw_eth_dev *priv = dev->priv; struct eth_mac_regs *mac_p = priv->mac_regs_p; struct eth_dma_regs *dma_p = priv->dma_regs_p; int ret; ret = phy_device_connect(dev, &priv->miibus, priv->phy_addr, dwc_update_linkspeed, 0, priv->interface); if (ret) return ret; descs_init(dev); /* * Start/Enable xfer at dma as well as mac level */ writel(readl(&dma_p->opmode) | RXSTART, &dma_p->opmode); writel(readl(&dma_p->opmode) | TXSTART, &dma_p->opmode); writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf); return 0; }
static int davinci_emac_open(struct eth_device *edev) { struct davinci_emac_priv *priv = edev->priv; uint32_t clkdiv, cnt; void __iomem *rx_desc; unsigned long mac_hi, mac_lo; int ret; dev_dbg(priv->dev, "+ emac_open\n"); dev_dbg(priv->dev, "emac->TXIDVER: 0x%08x\n", readl(priv->adap_emac + EMAC_TXIDVER)); dev_dbg(priv->dev, "emac->RXIDVER: 0x%08x\n", readl(priv->adap_emac + EMAC_RXIDVER)); /* Reset EMAC module and disable interrupts in wrapper */ writel(1, priv->adap_emac + EMAC_SOFTRESET); while (readl(priv->adap_emac + EMAC_SOFTRESET) != 0); writel(1, priv->adap_ewrap + EMAC_EWRAP_SOFTRESET); while (readl(priv->adap_ewrap + EMAC_EWRAP_SOFTRESET) != 0); writel(0, priv->adap_ewrap + EMAC_EWRAP_C0RXEN); writel(0, priv->adap_ewrap + EMAC_EWRAP_C1RXEN); writel(0, priv->adap_ewrap + EMAC_EWRAP_C2RXEN); writel(0, priv->adap_ewrap + EMAC_EWRAP_C0TXEN); writel(0, priv->adap_ewrap + EMAC_EWRAP_C1TXEN); writel(0, priv->adap_ewrap + EMAC_EWRAP_C2TXEN); writel(0, priv->adap_ewrap + EMAC_EWRAP_C0MISCEN); writel(0, priv->adap_ewrap + EMAC_EWRAP_C1MISCEN); writel(0, priv->adap_ewrap + EMAC_EWRAP_C2MISCEN); rx_desc = priv->emac_rx_desc; /* * Set MAC Addresses & Init multicast Hash to 0 (disable any multicast * receive) * Use channel 0 only - other channels are disabled */ writel(0, priv->adap_emac + EMAC_MACINDEX); mac_hi = (priv->mac_addr[3] << 24) | (priv->mac_addr[2] << 16) | (priv->mac_addr[1] << 8) | (priv->mac_addr[0]); mac_lo = (priv->mac_addr[5] << 8) | (priv->mac_addr[4]); writel(mac_hi, priv->adap_emac + EMAC_MACADDRHI); writel(mac_lo | EMAC_MAC_ADDR_IS_VALID | EMAC_MAC_ADDR_MATCH, priv->adap_emac + EMAC_MACADDRLO); /* Set source MAC address - REQUIRED */ writel(mac_hi, priv->adap_emac + EMAC_MACSRCADDRHI); writel(mac_lo, priv->adap_emac + EMAC_MACSRCADDRLO); /* Set DMA head and completion pointers to 0 */ for(cnt = 0; cnt < 8; cnt++) { writel(0, (void *)priv->adap_emac + EMAC_TX0HDP + 4 * cnt); writel(0, (void *)priv->adap_emac + EMAC_RX0HDP + 4 * cnt); writel(0, (void *)priv->adap_emac + EMAC_TX0CP + 4 * cnt); writel(0, (void *)priv->adap_emac + EMAC_RX0CP + 4 * cnt); } /* Clear Statistics (do this before setting MacControl register) */ for(cnt = 0; cnt < EMAC_NUM_STATS; cnt++) writel(0, (void *)priv->adap_emac + EMAC_RXGOODFRAMES + 4 * cnt); /* No multicast addressing */ writel(0, priv->adap_emac + EMAC_MACHASH1); writel(0, priv->adap_emac + EMAC_MACHASH2); writel(0x01, priv->adap_emac + EMAC_TXCONTROL); writel(0x01, priv->adap_emac + EMAC_RXCONTROL); /* Create RX queue and set receive process in place */ priv->emac_rx_active_head = priv->emac_rx_desc; for (cnt = 0; cnt < EMAC_MAX_RX_BUFFERS; cnt++) { writel(BD_TO_HW(rx_desc + EMAC_DESC_SIZE), rx_desc + EMAC_DESC_NEXT); writel(&priv->emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE + EMAC_PKT_ALIGN)], rx_desc + EMAC_DESC_BUFFER); writel(EMAC_MAX_ETHERNET_PKT_SIZE, rx_desc + EMAC_DESC_BUFF_OFF_LEN); writel(EMAC_CPPI_OWNERSHIP_BIT, rx_desc + EMAC_DESC_PKT_FLAG_LEN); rx_desc += EMAC_DESC_SIZE; } /* Set the last descriptor's "next" parameter to 0 to end the RX desc list */ rx_desc -= EMAC_DESC_SIZE; writel(0, rx_desc + EMAC_DESC_NEXT); priv->emac_rx_active_tail = rx_desc; priv->emac_rx_queue_active = 1; /* Enable TX/RX */ writel(EMAC_MAX_ETHERNET_PKT_SIZE, priv->adap_emac + EMAC_RXMAXLEN); writel(0, priv->adap_emac + EMAC_RXBUFFEROFFSET); /* No fancy configs - Use this for promiscous for debug - EMAC_RXMBPENABLE_RXCAFEN_ENABLE */ writel(EMAC_RXMBPENABLE_RXBROADEN, priv->adap_emac + EMAC_RXMBPENABLE); /* Enable ch 0 only */ writel(0x01, priv->adap_emac + EMAC_RXUNICASTSET); /* Enable MII interface and full duplex mode (using RMMI) */ writel((EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE | EMAC_MACCONTROL_RMIISPEED_100), priv->adap_emac + EMAC_MACCONTROL); /* Init MDIO & get link state */ clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1; writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT, priv->adap_mdio + EMAC_MDIO_CONTROL); /* Start receive process */ writel(BD_TO_HW(priv->emac_rx_desc), priv->adap_emac + EMAC_RX0HDP); ret = phy_device_connect(edev, &priv->miibus, priv->phy_addr, NULL, priv->phy_flags, priv->interface); if (ret) return ret; dev_dbg(priv->dev, "- emac_open\n"); return 0; }