static void mtk_disable_pmic_otg_mode(void)
{
int val;
pmic_config_interface(0x8068, 0x0, 0x1, 0);
pmic_config_interface(0x8084, 0x0, 0x1, 0);
mdelay(50);
pmic_config_interface(0x8068, 0x0, 0x1, 1);
val = 1;
while (val == 1) {
pmic_read_interface(0x805E, &val, 0x1, 4);
}
#if 0
pmic_config_interface(0x809E, 0x8000, 0xFFFF, 0);
val = 1;
while (val == 1) {
pmic_read_interface(0x809A, &val, 0x1, 15);
}
#endif
/* restore PMIC registers */
pmic_restore_regs();
mtk_xhci_mtk_log("set pimc power off, done\n");
}
void mt_power_off(void)
{
#ifdef CONFIG_MTK_PMIC_MT6397
int ret_val=0;
int reg_val=0;
#endif
printk("mt_power_off\n");
#ifdef CONFIG_MTK_PMIC_MT6397
//Enable CA15 by default for different PMIC behavior
pmic_config_interface(VCA15_CON7, 0x1, PMIC_VCA15_EN_MASK, PMIC_VCA15_EN_SHIFT);
pmic_config_interface(VSRMCA15_CON7, 0x1, PMIC_VSRMCA15_EN_MASK, PMIC_VSRMCA15_EN_SHIFT);
udelay(200);
ret_val=pmic_read_interface(VCA15_CON7, ®_val, 0xFFFF, 0);
printk("Reg[0x%x]=0x%x\n", VCA15_CON7, reg_val);
ret_val=pmic_read_interface(VSRMCA15_CON7, ®_val, 0xFFFF, 0);
printk("Reg[0x%x]=0x%x\n", VSRMCA15_CON7, reg_val);
#endif
/* pull PWRBB low */
rtc_bbpu_power_down();
while (1) {
#if defined(CONFIG_POWER_EXT)
//EVB
printk("EVB without charger\n");
#else
//Phone
printk("Phone with charger\n");
if (pmic_chrdet_status() == KAL_TRUE)
arch_reset(0, "power_off_with_charger");
#endif
}
}
static void mtk_enable_pmic_otg_mode(void)
{
int val;
printk("set pmic power on, begin\n");
mt_set_gpio_mode(GPIO_OTG_DRVVBUS_PIN, GPIO_MODE_GPIO);
mt_set_gpio_pull_select(GPIO_OTG_DRVVBUS_PIN, GPIO_PULL_DOWN);
mt_set_gpio_pull_enable(GPIO_OTG_DRVVBUS_PIN, GPIO_PULL_ENABLE);
/* save PMIC related registers */
printk("set pmic power on, begin2\n");
pmic_save_regs();
printk("set pmic power on, begin3\n");
pmic_config_interface(0x8D22, 0x1, 0x1, 12);
pmic_config_interface(0x8D14, 0x1, 0x1, 12);
pmic_config_interface(0x803C, 0x3, 0x3, 0);
pmic_config_interface(0x803C, 0x2, 0x3, 2);
pmic_config_interface(0x803C, 0x1, 0x1, 14);
pmic_config_interface(0x8036, 0x0, 0x0, 0);
pmic_config_interface(0x8D24, 0xf, 0xf, 12);
pmic_config_interface(0x8D16, 0x1, 0x1, 15);
pmic_config_interface(0x803A, 0x1, 0x1, 6);
pmic_config_interface(0x8046, 0x00A0, 0xffff, 0);
pmic_config_interface(0x803E, 0x1, 0x1, 2);
pmic_config_interface(0x803E, 0x1, 0x1, 3);
pmic_config_interface(0x803E, 0x3, 0x3, 8);
pmic_config_interface(0x803E, 0x0, 0x1, 10);
pmic_config_interface(0x8044, 0x3, 0x3, 0);
pmic_config_interface(0x8044, 0x3, 0x7, 8);
pmic_config_interface(0x8044, 0x1, 0x1, 11);
pmic_config_interface(0x809C, 0x8000, 0xFFFF, 0);
printk("set pmic power on, begin4\n");
val = 0;
while (val == 0) {
pmic_read_interface(0x809A, &val, 0x1, 15);
}
printk("set pmic power on, begin5\n");
pmic_config_interface(0x8084, 0x1, 0x1, 0);
mdelay(50);
val = 0;
while (val == 0) {
pmic_read_interface(0x8060, &val, 0x1, 14);
}
printk("set pmic power on, done\n");
}
void set_cv_volt(void)
{
kal_uint32 is_m3_en = 0;
pmic_read_interface(0x805E, &is_m3_en, 0x1, 2); //RGS_M3_EN
if(is_m3_en==1)
{
battery_xlog_printk(BAT_LOG_FULL,"[set_cv_volt] RGS_M3_EN=%d, set CV to high\n", is_m3_en);
#if 0 // for phone
battery_xlog_printk(BAT_LOG_CRTI,"[set_cv_volt] g_cv_reg_val=0x%x\n", g_cv_reg_val);
mt6332_upmu_set_rg_cv_sel(g_cv_reg_val);
mt6332_upmu_set_rg_cv_pp_sel(g_cv_reg_val);
#else
//set CV_VTH (ex=4.2) and RG_CV_PP_SEL (ex=4.3)
#if defined(HIGH_BATTERY_VOLTAGE_SUPPORT)
//battery_xlog_printk(BAT_LOG_CRTI, "[set_cv_volt] HIGH_BATTERY_VOLTAGE_SUPPORT\n");
mt6332_upmu_set_rg_cv_sel(0x5); // 4.35V
mt6332_upmu_set_rg_cv_pp_sel(0x5); // 4.35V
#else
mt6332_upmu_set_rg_cv_sel(0x8); // 4.2V
mt6332_upmu_set_rg_cv_pp_sel(0x8); // 4.2V
#endif
#endif
//Reg[0x816A]
pmic_config_interface(0x816A,0x1,0x1,5);
}
else
{
battery_xlog_printk(BAT_LOG_CRTI,"[set_cv_volt] RGS_M3_EN=%d, can not set CV to high\n", is_m3_en);
}
}
static void pmic_save_regs(void){
int i;
for(i = 0; i < PMIC_REG_BAK_NUM; i++){
pmic_read_interface(pmic_bak_regs[i][0], &pmic_bak_regs[i][1], 0xffffffff, 0);
}
}
static int mtktspmic_get_hw_temp(void)
{
kal_uint32 ret_val=0;
kal_uint8 thermal_status=0;
int t_ret=0;
mtktspmic_dprintk("[mtktspmic_get_hw_temp] \n");
if(ts_pmic_at_boot_time==0){
ts_pmic_at_boot_time=1;
mtktspmic_dprintk("[mtktspmic_get_hw_temp] at boot time, return 100002 as default\n");
return 100002;
}
//get HW PMIC temp (TSPMIC)
ret_val=pmic_read_interface(0x13,&thermal_status,0x7,4);
if(thermal_status == 0x0) {
t_ret = 100002;
} else if (thermal_status == 0x1) {
t_ret = 115002;
} else if (thermal_status == 0x3) {
t_ret = 140002;
} else if (thermal_status == 0x7) {
t_ret = 160002;
} else {
mtktspmic_dprintk("[mtktspmic_get_hw_temp] error register value (%d)\n", thermal_status);
}
mtktspmic_dprintk("[mtktspmic_get_hw_temp] T_PMIC, %d, %d\n", t_ret, thermal_status);
return t_ret;
}
static kal_uint16 gs6323_pmic_read(kal_uint16 reg)
{
kal_uint32 ret = 0;
kal_uint32 reg_val = 0;
ret = pmic_read_interface(reg, ®_val, 0xFFFF, 0x0);
return (kal_uint16)reg_val;
}
static kal_uint32 is_chr_det(void)
{
kal_uint32 val=0;
pmic_config_interface(0x10A, 0x1, 0xF, 8);
pmic_config_interface(0x10A, 0x17,0xFF,0);
pmic_read_interface(0x108, &val,0x1, 1);
battery_xlog_printk(BAT_LOG_CRTI,"[is_chr_det] %d\n", val);
return val;
}
static unsigned int _golden_read_reg(unsigned int addr)
{
unsigned int reg_val;
if (_is_pmic_addr(addr))
pmic_read_interface(addr, ®_val, 0xFFFFFFFF, 0x0);
else
reg_val = *((unsigned int *)IO_PHYS_TO_VIRT(addr));
return reg_val;
}
U32 upmu_get_cid(void)
{
U32 ret=0;
U32 val=0;
pmic_lock();
ret=pmic_read_interface( (U32)(CID),
(&val),
(U32)(PMIC_CID_MASK),
(U32)(PMIC_CID_SHIFT)
);
pmic_unlock();
return val;
}
BOOL mtk_detect_pmic_just_rst(void)
{
kal_uint32 just_rst = 0;
printf("detecting pmic just reset\n");
pmic_read_interface(STRUP_CON8, &just_rst, PMIC_JUST_PWRKEY_RST_MASK, PMIC_JUST_PWRKEY_RST_SHIFT);
if (just_rst)
{
printf("Just recover from a reset\n");
pmic_config_interface(STRUP_CON8, 0x01, PMIC_CLR_JUST_RST_MASK, PMIC_CLR_JUST_RST_SHIFT);
return TRUE;
}
return FALSE;
}
BOOL mtk_detect_pmic_just_rst(void)
{
kal_uint32 just_rst=0;
kal_uint32 ret=0;
printf("detecting pmic just reset\n");
ret=pmic_read_interface(0x04A, &just_rst, 0x01, 14);
if(just_rst)
{
printf("Just recover form a reset\n");
pmic_config_interface(0x04A, 0x01, 0x01, 4);
return TRUE;
}
return FALSE;
}
static unsigned int _golden_read_reg(unsigned int addr)
{
unsigned int reg_val;
if (_is_pmic_addr(addr))
pmic_read_interface(addr, ®_val, 0xFFFFFFFF, 0x0);
else
{
#ifdef CONFIG_OF
reg_val = ioread32(_golden_io_phys_to_virt(addr));
#else
reg_val = *((unsigned int *)IO_PHYS_TO_VIRT(addr));
#endif
}
return reg_val;
}
kal_uint32 pmic_is_auxadc_ready(kal_int32 channel_num, upmu_adc_chip_list_enum chip_num, upmu_adc_user_list_enum user_num)
{
#if 1
kal_uint32 ret=0;
kal_uint32 int_status_val_0=0;
//unsigned long flags;
//spin_lock_irqsave(&pmic_adc_lock, flags);
if (chip_num ==MT6325_CHIP) {
if (user_num == GPS ) {
ret=mt6325_upmu_get_rg_adc_rdy_gps();
} else if (user_num == MD ) {
ret=mt6325_upmu_get_rg_adc_rdy_md();
} else if (user_num == AP ) {
pmic_read_interface(MT6325_AUXADC_ADC0+channel_num * 2,(&int_status_val_0),0x8000,0x0);
ret = int_status_val_0 >> 15;
}
} else if (chip_num == MT6311_CHIP) {
static kal_uint32 charging_get_charger_det_status(void *data)
{
kal_uint32 status = STATUS_OK;
#if 1
kal_uint32 val=0;
pmic_config_interface(0x10A, 0x1, 0xF, 8);
pmic_config_interface(0x10A, 0x17,0xFF,0);
pmic_read_interface(0x108, &val,0x1, 1);
*(kal_bool*)(data) = val;
battery_xlog_printk(BAT_LOG_CRTI,"[charging_get_charger_det_status] CHRDET status = %d\n", val);
#else
//*(kal_bool*)(data) = upmu_get_rgs_chrdet();
*(kal_bool*)(data) = 1;
battery_xlog_printk(BAT_LOG_CRTI,"[charging_get_charger_det_status] no HW function\n");
#endif
return status;
}
static kal_uint32 charging_get_charger_det_status(void *data)
{
kal_uint32 status = STATUS_OK;
#if 0
// *(kal_bool*)(data) = upmu_get_rgs_chrdet();
#else
kal_uint32 val=0;
pmic_config_interface(0x10A, 0x1, 0xF, 8);
pmic_config_interface(0x10A, 0x17,0xFF,0);
pmic_read_interface(0x108, &val,0x1, 1);
*(kal_bool*)(data) = val;
battery_xlog_printk(BAT_LOG_CRTI,"[charging_get_charger_det_status][JJP][20140401] CHRDET status = %d\n", val);
/* if(val == 0)
g_charger_type = CHARGER_UNKNOWN;*/
#endif
return status;
}
static kal_uint32 charging_get_battery_status(void *data)
{
kal_uint32 status = STATUS_OK;
kal_uint32 val = 0;
#if defined(CONFIG_POWER_EXT) || defined(CONFIG_MTK_FPGA)
*(kal_bool*)(data) = 0; // battery exist
battery_xlog_printk(BAT_LOG_CRTI,"[charging_get_battery_status] battery exist for bring up.\n");
#else
pmic_read_interface( MT6325_CHR_CON7, &val, MT6325_PMIC_BATON_TDET_EN_MASK, MT6325_PMIC_BATON_TDET_EN_SHIFT);
battery_xlog_printk(BAT_LOG_FULL,"[charging_get_battery_status] BATON_TDET_EN = %d\n", val);
if (val) {
mt6325_upmu_set_baton_tdet_en(1);
mt6325_upmu_set_rg_baton_en(1);
*(kal_bool*)(data) = mt6325_upmu_get_rgs_baton_undet();
} else {
*(kal_bool*)(data) = KAL_FALSE;
}
#endif
return status;
}
void sw_plug_out_check(void)
{
// chr_plug_out_sw_detect
#if 1
if(upmu_is_chr_det_hal()==1) //sync USB device/otg state
{
kal_uint32 cv_val = 0;
kal_uint32 ich_low_val = 0;
kal_uint32 is_charge_complete = 0;
pmic_read_interface(0x805E, &cv_val, 0x1, 0);
if(cv_val == 1)
{
battery_xlog_printk(BAT_LOG_FULL,"[chr_plug_out_sw_detect] in CV\n");
pmic_config_interface(0x8074, 0x1, 0x1, 9);
pmic_config_interface(0x8166, 0x1, 0x1,12);
pmic_config_interface(0x8D36, 0x3, 0x3,11); //[12:11]=0x3
}
else
{
battery_xlog_printk(BAT_LOG_FULL,"[chr_plug_out_sw_detect] not in CV\n");
pmic_config_interface(0x8074, 0x0, 0x1, 9);
pmic_config_interface(0x8166, 0x1, 0x1,12);
pmic_config_interface(0x8D36, 0x0, 0x3,11); //[12:11]=0x0
}
#if 1
battery_xlog_printk(BAT_LOG_FULL,"[chr_plug_out_sw_detect] Reg[0x%x]=0x%x\n", 0x8074, upmu_get_reg_value(0x8074) );
pmic_read_interface(0x8054, &ich_low_val, 0x1, 1);
pmic_read_interface(0x805E, &is_charge_complete, 0x1, 10);
battery_xlog_printk(BAT_LOG_CRTI,"[chr_plug_out_sw_detect] ich_low_val=%d, is_charge_complete=%d\n",
ich_low_val, is_charge_complete);
//if( (ich_low_val==1) || (is_charge_complete==1) )
if(is_chr_det()==1) // for evb
{
set_usb_dc_in_mode(0,0);
set_usb_dc_in_mode(0,1);
battery_xlog_printk(BAT_LOG_CRTI,"[chr_plug_out_sw_detect] Reg[0x%x]=0x%x\n", 0x816C, upmu_get_reg_value(0x816C) );
//
msleep(10);
if(is_chr_det()==1)
{
set_usb_dc_in_mode(0,0);
}
}
else
{
set_usb_dc_in_mode(0,0);
}
#endif
//debug
swchr_dump_register();
mt_swchr_debug_msg();
battery_xlog_printk(BAT_LOG_FULL,"[chr_plug_out_sw_detect] Reg[0x%x]=0x%x, Reg[0x%x]=0x%x, Reg[0x%x]=0x%x\n",
0x8D1E, upmu_get_reg_value(0x8D1E), 0x8D2C, upmu_get_reg_value(0x8D2C), 0x816C, upmu_get_reg_value(0x816C) );
}
else
{
battery_xlog_printk(BAT_LOG_FULL,"[chr_plug_out_sw_detect] no cable\n");
}
#endif
}
/* will be placed in mediatek/platform/mt6582/lk/platform.c */
int repair_sram(void)
{
// --------------------------------------------------
// common
// --------------------------------------------------
unsigned int status;
unsigned int pwr_ack_status, pwr_acks_status;
int ret = 0;
UINT32 rdata;
UINT32 rdata_mm1;
UINT32 rdata_mm0;
UINT32 rdata_cksw0;
UINT32 rdata_cksw1;
UINT32 rdata_cksw2;
UINT32 rdata_cksw3;
UINT32 rdata_cksw4;
UINT32 reg_val=0;
#if 0
printf("=================================Before Repair SRAM===========================\n");
printf("Repair SRAM 0520 v3-do load_fuse-2000 and Clock switch Enable and add PLL detail INFO\n");
printf("[Repair SRAM Check] Check MTCMOS Before Repair SRAM: START\n");
printf("[Repair SRAM Check] MFG_PWR_CON:0x10006214=0x%x\n",*((UINT32P) (0x10006214)));
printf("[Repair SRAM Check] ISP_PWR_CON:0x10006238=0x%x\n",*((UINT32P) (0x10006238)));
printf("[Repair SRAM Check] DIS_PWR_CON:0x1000623C=0x%x\n",*((UINT32P) (0x1000623C)));
printf("[Repair SRAM Check] MD_PWR_CON:0x10006284=0x%x\n",*((UINT32P) (0x10006284)));
printf("[Repair SRAM Check] PWR_STATUS:0x1000660C=0x%x\n",*((UINT32P) (0x1000660C)));
printf("[Repair SRAM Check] PWR_STATUS_S:0x10006610=0x%x\n",*((UINT32P) (0x10006610)));
printf("[Repair SRAM Check] Check MTCMOS: END\n");
printf("[Repair SRAM Check] Check PLL Before Repair SRAM: START\n");
printf("[Repair SRAM Check] AP_PLL_CON1:0x10209004=0x%x\n",*((UINT32P) (0x10209004)));
printf("[Repair SRAM Check] MAINPLL_CON1:0x10209214=0x%x\n",*((UINT32P) (0x10209214)));
printf("[Repair SRAM Check] MMPLL_CON1:0x0x10209234=0x%x\n",*((UINT32P) (0x10209234)));
printf("[Repair SRAM Check] VENCPLL_CON1:0x1000F804=0x%x\n",*((UINT32P) (0x1000F804)));
printf("[Repair SRAM Check] MSDCPLL_CON1:0x10209244=0x%x\n",*((UINT32P) (0x10209244)));
printf("[Repair SRAM Check] VENCPLL_CON0:0x1000F800=0x%x\n",*((UINT32P) (0x1000F800)));
printf("[Repair SRAM Check] VENCPLL_CON1:0x1000F804=0x%x\n",*((UINT32P) (0x1000F804)));
printf("[Repair SRAM Check] VENCPLL_CON2:0x1000F808=0x%x\n",*((UINT32P) (0x1000F808)));
printf("[Repair SRAM Check] VENCPLL_PWR_CON0:0x1000F80C=0x%x\n",*((UINT32P) (0x1000F80C)));
printf("[Repair SRAM Check] *CLK_CFG_0=0x%x\n",*CLK_CFG_0);
printf("[Repair SRAM Check] *CLK_CFG_1=0x%x\n",*CLK_CFG_1);
printf("[Repair SRAM Check] *CLK_CFG_2=0x%x\n",*CLK_CFG_2);
printf("[Repair SRAM Check] *CLK_CFG_3=0x%x\n",*CLK_CFG_3);
printf("[Repair SRAM Check] *CLK_CFG_4=0x%x\n",*CLK_CFG_4);
printf("[Repair SRAM Check] Check PLL END\n");
printf("[Repair SRAM Check] VProc Monitor Before Repair SRAM START\n");
ret=pmic_read_interface(0x21E,®_val,0xFFFF,0);
printf("Reg[0x21E]=0x%x, %d\n", reg_val, ret);
ret=pmic_read_interface(0x220,®_val,0xFFFF,0);
printf("Reg[0x220]=0x%x, %d\n", reg_val, ret);
ret=pmic_read_interface(0x222,®_val,0xFFFF,0);
printf("Reg[0x222]=0x%x, %d\n", reg_val, ret);
ret=pmic_read_interface(0x216,®_val,0xFFFF,0);
printf("Reg[0x216]=0x%x, %d\n", reg_val, ret);
ret=pmic_read_interface(0x224,®_val,0xFFFF,0);
printf("Reg[0x224]=0x%x, %d\n", reg_val, ret);
printf("[Repair SRAM Check] VProc Monitor End\n");
printf("\n");
printf("=======================================END===============================\n");
#endif
/*TINFO="instruction code " */
// --------------------------------------------------
// Turn on MDMCU
// --------------------------------------------------
// *ACLKEN_DIV = 0x12; //div2
// *PCLKEN_DIV = 0x14; //div4
// *MEM_PWR_CTRL = 0x3; //slpb_dly and mem_off_dly
// //Enable MCUSYS command queue
// *MCU_BIU_CON |= 0x1; //enable out-of-order queue
// *MCU_BIU_CON |= 0x1000;
// *CA7_MISC_CONFIG |= 0x200;
///1. set MTCMOS
// --------------------------------------------------
*POWRON_CONFIG_EN = 0x0B160001; //spm power code
*((UINT32P) (0x10006214)) = 0x00000f16; //MFG MTCOMS
*((UINT32P) (0x10006214)) = 0x00000f1e; //MFG MTCOMS
udelay(10);
pwr_ack_status = (*SLEEP_PWR_STA & 0x00000010) >> 4; //[04]
pwr_acks_status = (*SLEEP_PWR_STAS & 0x00000010) >> 4; //[04]
if ((pwr_ack_status != 0x01) | (pwr_acks_status != 0x01)) {
/* TINFO="Wait for Power Up MFGSys ..." */
printf("Power Up MFGSys fail %d\n", __LINE__);
ret = -1;
}
*((UINT32P) (0x10006214)) = 0x00000f0e; //MFG MTCOMS
*((UINT32P) (0x10006214)) = 0x00000f0c; //MFG MTCOMS
*((UINT32P) (0x10006214)) = 0x00000f0d; //MFG MTCOMS
*((UINT32P) (0x10006214)) = 0x00000e0d; //MFG MTCOMS
*((UINT32P) (0x10006214)) = 0x00000c0d; //MFG MTCOMS
*((UINT32P) (0x10006214)) = 0x0000080d; //MFG MTCOMS
*((UINT32P) (0x10006214)) = 0x0000000d; //MFG MTCOMS
*((UINT32P) (0x10006238)) = 0x00000f16; //ISP MTCOMS
*((UINT32P) (0x10006238)) = 0x00000f1e; //ISP MTCOMS
udelay(10);
pwr_ack_status = (*SLEEP_PWR_STA & 0x00000020) >> 5; //[05]
pwr_acks_status = (*SLEEP_PWR_STAS & 0x00000020) >> 5; //[05]
if ((pwr_ack_status != 0x01) | (pwr_acks_status != 0x01)) {
/* TINFO="Wait for Power On ISPSys ..." */
printf("Power Up ISPSys fail %d\n", __LINE__);
ret = -1;
}
*((UINT32P) (0x10006238)) = 0x00000f0e; //ISP MTCOMS
*((UINT32P) (0x10006238)) = 0x00000f0c; //ISP MTCOMS
*((UINT32P) (0x10006238)) = 0x00000f0d; //ISP MTCOMS
*((UINT32P) (0x10006238)) = 0x00000e0d; //ISP MTCOMS
*((UINT32P) (0x10006238)) = 0x00000c0d; //ISP MTCOMS
*((UINT32P) (0x10006238)) = 0x0000080d; //ISP MTCOMS
*((UINT32P) (0x10006238)) = 0x0000000d; //ISP MTCOMS
#if 0 //DISP already opened in preloader
*((UINT32P) (0x1000623c)) = 0x00000f16; //DISP MTCOMS
*((UINT32P) (0x1000623c)) = 0x00000f1e; //DISP MTCOMS
udelay(10);
pwr_ack_status = (*SLEEP_PWR_STA & 0x00000008) >> 3; //[03]
pwr_acks_status = (*SLEEP_PWR_STAS & 0x00000008) >> 3; //[03]
if ((pwr_ack_status != 0x01) | (pwr_acks_status != 0x01)) {
/* TINFO="Wait for Power Up DisSys ..." */
printf("Power Up DISPSys fail %d\n", __LINE__);
ret = -1;
}
*((UINT32P) (0x1000623c)) = 0x00000f0e; //DISP MTCOMS
*((UINT32P) (0x1000623c)) = 0x00000f0c; //DISP MTCOMS
*((UINT32P) (0x1000623c)) = 0x00000f0d; //DISP MTCOMS
*((UINT32P) (0x1000623c)) = 0x00000e0d; //DISP MTCOMS
*((UINT32P) (0x1000623c)) = 0x00000c0d; //DISP MTCOMS
*((UINT32P) (0x1000623c)) = 0x0000080d; //DISP MTCOMS
*((UINT32P) (0x1000623c)) = 0x0000000d; //DISP MTCOMS
#endif
//enable MD MTCOM
if( (*((UINT32P) (0x10206040)) & 0x00400000) == 0x0) { //MD efuse not disable
if( (*((UINT32P) (0x10206044)) & 0x00000080) == 0x0) { //TDD efuse not disable
*((UINT16P) (0x2400001e)) = 0x000d; // tddsys mbist_mem_clk_en
} //TDD efuse not disable
// --------------------------------------------------
/* TINFO=" rdata = %h", *((UINT32P)(0x23010800)) */
*((UINT32P) (0x23010800)) = 0xa244; //md2g MODEM2G_TOPSM_RM_PWR_CON0
/* TINFO=" rdata = %h", *((UINT32P)(0x23010804)) */
*((UINT32P) (0x23010804)) = 0xa244; //md_hspa1 MODEM2G_TOPSM_RM_PWR_CON1
/* TINFO=" rdata = %h", *((UINT32P)(0x2301080c)) */
*((UINT32P) (0x2301080c)) = 0xa244; //md_hspa3 MODEM2G_TOPSM_RM_PWR_CON3
/* TINFO=" rdata = %h", *((UINT32P)(0x23010810)) */
*((UINT32P) (0x23010810)) = 0xa244; //md_hspa4 MODEM2G_TOPSM_RM_PWR_CON4
//md_top
/* TINFO=" rdata = %h", *((UINT32P)(0x20030018)) */
*((UINT32P) (0x20030018)) = 0x0; //MD_TOPSM_RM_TMR_PWR0
/* TINFO=" rdata = %h", *((UINT32P)(0x23010018)) */
*((UINT32P) (0x23010018)) = 0x0; //MODEM2G_TOPSM_RM_TMR_PWR0
} //MD efuse not disable
////2. enable PLL
//// --------------------------------------------------
////2.1 enable PLL power
//*MMPLL_PWR_CON0 |= 0x1;
////wait 5us
///* TINFO="wait 5u"*/
//for(i=0;i<4;i=i+1){
//j=0;
//}
////2.2 release PLL ISO
//*MMPLL_PWR_CON0 &= 0xfffffffd;
////2.3 setting PLL frequency
//ck swithc initial setting recored
rdata_cksw0 = *CLK_CFG_0;
rdata_cksw1 = *CLK_CFG_1;
rdata_cksw2 = *CLK_CFG_2;
rdata_cksw3 = *CLK_CFG_3;
rdata_cksw4 = *CLK_CFG_4;
//clock switch of MM --> 26M
//
//*MMPLL_CON1 = 0x80134000; //2002/4=500.5M
//*MMPLL_CON0 = 0x120; //2002/4=500.5M
////2.4 enable PLL
//*MMPLL_CON0 |= 0x1;
////wait 20us
//for(i=0;i<9;i=i+1){
//j=0;
//}
//
/*TINFO="Set this register before AXI clock switch to fast clock, APB/AHB" */
//!!!already set in pre-loader,
// *INFRA_TOPCKGEN_DCMCTL |= 0x1;
//
/*TINFO="cksys clock switch"*/
// ------------------------------------------------------------------
// open ckswitch power// clear power down
*CLK_CFG_0_CLR = 0x80800080; //MEMPLL don't change setting
*CLK_CFG_1_CLR = 0x80808080;
*CLK_CFG_2_CLR = 0x80808080;
*CLK_CFG_3_CLR = 0x80808080;
*CLK_CFG_4_CLR = 0x80808080;
// wait clock switch power
udelay(1);
if (((*CKSTA_REG) & 0xffffffff) != 0x0) {
printf("Clock switch failed %d\n", __LINE__);
ret = -1;
}
*CLK_CFG_0 = 0x01010001 | (rdata_cksw0 & 0x0000FF00); //for MEMPLL //mem clock[8] not switch or will let dram hang(w/o set PLL clock source)
*CLK_CFG_1 = 0x02010103;
*CLK_CFG_2 = 0x01010101;
*CLK_CFG_3 = 0x01010101;
*CLK_CFG_4 = 0x01010101;
printf("[CLK_CFG_4] *CLK_CFG_4=0x%x\n",*CLK_CFG_4);
// ------------------------------------------------------------------
//wait md2g_power[0] hspa power [1]
if( (*((UINT32P) (0x10206040)) & 0x00400000) == 0x0) { //MD efuse not disable
/*TINFO="check MD MTCMOS ready" */
udelay(2000);
if ((*((UINT32P) (0x23010820)) & 0x00000003) != 0x3) {
printf("MD MTCMOS is not ready. %d\n", __LINE__);
ret = -1;
}
//wait tdd power
udelay(500);
if( (*((UINT32P) (0x10206044)) & 0x00000080) == 0x0) { //TDD efuse not disable
if (!(*((UINT16P) (0x24000002)) & 0x2)) {
printf("tdd power is not ready %d\n", __LINE__);
ret = -1;
}
}
//enable MD PLL
/*TINFO="enable MD PLL" */
*((UINT32P) (0x201200ac)) = 0x3f; //PLL_DFS_CON7, bit 0~5 set to 1 // [FORCE ON] Bit 5: SYSCLK, Bit 4: MDPLL, Bit 3: WHPLL, Bit 2: WPLL, Bit 1: MCUPLL, Bit 0: No use (HW limit when boot)
*((UINT32P) (0x2012004c)) = 0x8300; //PLL_PLL_CON3, bit 12,4 set to 0// [POWER ON] Bit15: MCUPLL, Bit 8: WPLL
/*TINFO="wait 1us check" */
udelay(1);
*((UINT32P) (0x2012004c)) = 0x0; // bit 15,8,1,0 set to 0
*((UINT32P) (0x20120048)) = 0x0; //PLL_PLL_CON2, bit 12,10, 8, 6, 2 set to 0// [TOPSM & SW CTRL] Bit12: MDPLL, Bit 8: MCUPLL, Bit 4: WPLL, Bit 0: WHPLL
*((UINT32P) (0x20120700)) = 0x10; //PLL_PLLTD_CON0, bit 0 set to 0// [FHCTL & SW CTRL] Bit 4: CHG_CTRL
/*TINFO="wait 3us check" */
udelay(3);
/* TINFO="Enable PLLs" */
*((UINT32P) (0x20120100)) = 0x410f | 0x8000; // Enable PLLs, PLL_MDPLL_CON0
/*TINFO="wait 100us check" */
udelay(100);
*((UINT32P) (0x20120100)) &= 0x7fff; // Enable PLLs, PLL_MDPLL_CON0
/*TINFO="wait 30ns check" */
udelay(1);
*((UINT32P) (0x20120140)) = 0x0810 | 0x8000; // Enable PLLs, PLL_MCUPLL_CON0
*((UINT32P) (0x201201c0)) = 0x0800 | 0x8000; // Enable PLLs, PLL_WPLL_CON0
*((UINT32P) (0x20120200)) = 0x0500 | 0x8000; // Enable PLLs, PLL_WHPLL_CON0
/*TINFO="wait 100us check" */
udelay(100);
/* TINFO="Disable MDPLL and MDPLL2 AUTOK" */
*((UINT32P) (0x20120110)) &= 0xfffffffe; // PLL_MDPLL_CON4, bit0 set to 0
/*TINFO="wait 2us check" */
udelay(2);
*((UINT32P) (0x20120100)) = 0x410f | 0x8000; // Enable PLLs, PLL_MDPLL_CON0
/* TINFO="wait 20u"*/
udelay(20);
// ------------------------------------------------------------------
//SWITCH PLL clock
//switch CR4 clock to 481M
/* TINFO="Clock Switch Setting" */
/* TINFO=" rdata = %h", *((UINT32P)(0x2000045c)) */
*((UINT32P) (0x2000045c)) |= 0x20000000; //MD_GLOBAL_CON1, BUS_CLK = PLL Freq (not 26MHz)
/* TINFO=" rdata = %h", *((UINT32P)(0x20120060)) */
*((UINT32P) (0x20120060)) = 0x2020; //PLL_CLKSW_CKSEL0, Bit 15-12: MDMCU_CLK = MCUPLL 481MHz, Bit 7- 4: DSP_CLK = MCUPLL DIV3 = 481 MHz / 2 = 240.5 MHz
/* TINFO=" rdata = %h", *((UINT32P)(0x20120064)) */
*((UINT32P) (0x20120064)) = 0x2000; //PLL_CLKSW_CKSEL1, Bit 15-12: BUS_CLK = MCUPLL DIV2 = 481 MHz / 4 = 120.25MHz
/* TINFO=" rdata = %h", *((UINT32P)(0x20120068)) */
*((UINT32P) (0x20120068)) = 0x2240; //PLL_CLKSW_CKSEL2, Bit 15-12: FX64W_CLK = WPLL = 245.76MHz, Bit 11- 8: FX16G_CLK = MDPLL DIV3 = 416 MHz / 2 = 208 MHz, Bit 7- 4: HW64W_CLK = WHPLL = 250.25MHz
/* TINFO=" rdata = %h", *((UINT32P)(0x22c00040)) */
*((UINT32P) (0x22c00040)) = 0x41f041f0; // MD2GSYS_clock switch
} // MD efuse not disable
//===========MD PLL setting end
//
// ------------------------------------------------------------------
//DCM
*((UINT32P) (0x13000010)) = 0x0; //disable mfg DCM [15]
// ------------------------------------------------------------------
//clock enable
/* TINFO="clock enable" */
/* TINFO=" rdata = %h", *((UINT32P)(0x14000108)) */
*((UINT32P) (0x14000108)) = 0xffffffff; //turn mmsys clock
/* TINFO=" rdata = %h", *((UINT32P)(0x14000118)) */
*((UINT32P) (0x14000118)) = 0xffffffff; //turn mmsys clock
/* TINFO=" rdata = %h", *((UINT32P)(0x14000118)) */
*((UINT32P) (0x15000008)) = 0xffffffff; //turn img clock
/* TINFO=" rdata = %h", *((UINT32P)(0x14000118)) */
*((UINT32P) (0x15004150)) = 0x0000ffff; //turn img clock
// ------------------------------------------------------------------
if( (*((UINT32P) (0x10206040)) & 0x00400000) == 0x0) { //MD efuse not disable
*((UINT32P) (0x20000458)) = 0xffffffff; //turn md infrasys clock
*((UINT32P) (0x23000010)) = 0xffffffff; //turn md modem clock
*((UINT32P) (0x23000018)) = 0xffffffff; //turn md modem clock
*((UINT32P) (0x23000098)) = 0xffffffff; //turn md modem clock
if( (*((UINT32P) (0x10206044)) & 0x00000001) == 0x0) { //HSPA efuse not disable
*((UINT32P) (0x2367002c)) = 0xffffffff; //turn md hspa3 clock
*((UINT32P) (0x23670010)) = 0x00000000; //turn md hspa3 clock
}
if( (*((UINT32P) (0x10206044)) & 0x00000080) == 0x0) { //TDD efuse not disable
*((UINT16P) (0x24000422)) = 0x4911; //turn on tddsys clock
*((UINT16P) (0x24000422)) = 0xc911; //turn on tddsys clock
}
} //MD efuse not disable
// ------------------------------------------------------------------
//printf("[Repair SRAM Check ] Start 1nd MBIST\n");
//=============================================
//set mbist_rstb & rp_rstb
/* TINFO="set mbist_rstb" */
*((UINT32P) (0x13000100)) = 0x00000000; // [0] mfg rp_rstb=0
*((UINT32P) (0x13000060)) = 0x00000000; // set mfgsys mbist_rstb, [31]:mbist_rstb
*((UINT32P) (0x14000850)) = 0x00000000; // set mm_mdp [0] rp_rstb
*((UINT32P) (0x1400081C)) = 0x00000000; // set mmsys mbist_rstb, [15]: mbist_rstb [31:16]: mm background
//*((UINT32P)(0x150001a0)) = 0x00000000; // set imgsys [0]: rp_rstb
*((UINT32P) (0x15000070)) = 0x00000000; // set imgsys mbist_rstb, [0]: mbist_rstb
*((UINT32P) (0x150001A0)) = 0x00000000; // set imgsys rp_rst, [0] henry add
if( (*((UINT32P) (0x10206040)) & 0x00400000) == 0x0) { //MD efuse not disable
*((UINT32P) (0x200e0044)) = 0x00000000; // set mdsys mbist_rstb, [0]: mbist_rstb, [1]:repair reset [2]:reg_load_fuse
//*((UINT32P)(0x23008040)) = 0x00000000; // set modemsys mbist_rstb, [0]: mbist_rstb
//*((UINT32P)(0x236e008c)) = 0x00000000; // set hspa3sys [0]: rp_rstb
if( (*((UINT32P) (0x10206044)) & 0x00000001) == 0x0) { //HSPA efuse not disable
*((UINT32P)(0x236e008c)) = 0x00000000; // set hspa3sys [0]: rp_rstb henry add
*((UINT32P)(0x236e007c)) = 0x00000000; // set hspa3sys mbist_rst, [0]: mbist_rstbb
}
if( (*((UINT32P) (0x10206044)) & 0x00000080) == 0x0) { //HSPA efuse not disabl
*((UINT32P) (0x24050068)) = 0x00000000; // set tddsys mbist_rst, [0]: mbist_rstbb
}
}//MD efuse not disable
// ------------------------------------------------------------------
//release mbist_rstb & rp_rstb
/* TINFO="release mbist_rstb" */
*((UINT32P) (0x13000100)) = 0x00000001; // [0] mfg rp_rstb=1
*((UINT32P) (0x13000060)) = 0x80000000; // release mfgsys mbist_rstb, [31]:mbist_rstb
*((UINT32P) (0x14000850)) = 0x00000001; // set mm_mdp 0 rp_rstb
*((UINT32P) (0x1400081C)) = 0x00008000; // release mmsys mbist_rstb, [15]: mbist_rstb [31:16]: mm background (TBD)
//*((UINT32P)(0x150001a0)) = 0x00000001; // set imgsys [0]: rp_rstb
*((UINT32P) (0x15000070)) = 0x00000001; // release imgsys mbist_rstb, [0]: mbist_rstb
*((UINT32P) (0x150001A0)) = 0x00000001; // set imgsys rp_rst, [0] //add by henry
if( (*((UINT32P) (0x10206040)) & 0x00400000) == 0x0) { //MD efuse not disable
*((UINT32P) (0x200e0044)) = 0x00000003; // release mdsys mbist_rstb, [0]: mbist_rstb, [1]:repair reset [2]:reg_load_fuse
//*((UINT32P)(0x23008040)) = 0x00000001; // release modemsys mbist_rstb, [0]: mbist_rstb
//*((UINT32P)(0x236e008c)) = 0x00000001; // set hspa3sys [0]: rp_rstb
if( (*((UINT32P) (0x10206044)) & 0x00000001) == 0x0) { //HSPA efuse not disable
*((UINT32P)(0x236e008c)) = 0x00000001; // set hspa3sys [0]: rp_rstb //add by henry
*((UINT32P)(0x236e007c)) = 0x00000001; // release hspa3sys mbist_rst, [0]: mbist_rstbb
}
if( (*((UINT32P) (0x10206044)) & 0x00000080) == 0x0) { //HSPA efuse not disabl
*((UINT32P) (0x24050068)) = 0x00000001; // release tddsys mbist_rst, [0]: mbist_rstbb
}
}
// ------------------------------------------------------------------
//set mbist_mode=1
/* TINFO="set mbist_mode" */
*((UINT32P) (0x13000060)) = 0x80000002; // [1] mbist_mode, [31]: mbist_rstb mfg
*((UINT32P) (0x14000810)) = 0x00000040; // [6] mbist_mode mm
*((UINT32P) (0x15000074)) = 0x00001c00; // [12:10] mbist_mode img
if( (*((UINT32P) (0x10206040)) & 0x00400000) == 0x0) { //MD efuse not disable
*((UINT32P) (0x200e0000)) = 0x00000ff6; // [11:4,2:1] mbist_mode md
if( (*((UINT32P) (0x10206044)) & 0x00000001) == 0x0) { //HSPA efuse not disable
*((UINT32P) (0x236e0000)) = 0x00000080; // [7] mbist_mode md_hspa3
}
if( (*((UINT32P) (0x10206044)) & 0x00000080) == 0x0) { //HSPA efuse not disabl
*((UINT32P) (0x24050000)) = 0x3b438000; // [29~27, 25~24,22,17~15] mbist_mode tdd
}
}
// ------------------------------------------------------------------
//wait mbist_done
udelay(2000);
/* TINFO="wait mbist_done" */
if ((*((UINT32P) (0x13000090)) & 0x7fff8) != 0x7fff8) { //mfg mbist_done
printf("mfg mbist_done is not ready %d\n", __LINE__);
ret = -1;
}
/* TINFO="mfg mbist_done" */
// printf("[Repair SRAM Check ] Value check 1nd MM:0x14000800=0x%x\n",*((UINT32P) (0x14000800)));
if ((*((UINT32P) (0x14000800)) & 0x20f) != 0x20f) { //mm mbist_done
printf("mm mbist_done is not ready %d\n", __LINE__);
printf("[Repair SRAM Check ] 1nd MM:0x14000800=0x%x\n",*((UINT32P) (0x14000800)));
printf("[Repair SRAM Check ] 1nd MM:0x14000804=0x%x\n",*((UINT32P) (0x14000804)));
ret = -1;
}
/* TINFO="mm mbist_done" */
// printf("[Repair SRAM Check] Value check 1nd IMG:0x15000038=0x%x\n",*((UINT32P) (0x15000038)));
if ((*((UINT32P) (0x15000038)) & 0x1c40) != 0x1c40) { //img mbist_done
printf("img mbist_done is not ready %d\n", __LINE__);
printf("[Repair SRAM Check] 1nd IMG:0x15000038=0x%x\n",*((UINT32P) (0x15000038)));
printf("[Repair SRAM Check] 1nd IMG:0x15000048=0x%x\n",*((UINT32P) (0x15000048)));
printf("[Repair SRAM Check] 1nd IMG:0x1500004c=0x%x\n",*((UINT32P) (0x1500004c)));
printf("[fuse check] 1nd IMG:0x100011ec=0x%x\n",*((UINT32P) (0x100011ec)));
printf("[img repair status] IMG:0x150001a4=0x%x\n",*((UINT32P) (0x150001a4)));
ret = -1;
}
/* TINFO="img mbist_done" */
if( (*((UINT32P) (0x10206040)) & 0x00400000) == 0x0) { //MD efuse not disable
if ((*((UINT32P) (0x200e0024)) & 0x1fec) != 0x1fec) { //md mbist_done
printf("md mbist_done is not ready %d\n", __LINE__);
ret = -1;
}
/* TINFO="mdmcu mbist_done" */
if( (*((UINT32P) (0x10206044)) & 0x00000001) == 0x0) { //HSPA efuse not disable
if ((*((UINT32P) (0x236e002c)) & 0x4) != 0x4) { //hspa3 mbist_done
printf("hspa3 mbist_done is not ready %d\n", __LINE__);
ret = -1;
}
}
/* TINFO="hspa3 mbist_done" */
if( (*((UINT32P) (0x10206044)) & 0x00000080) == 0x0) { //TDD efuse not disable
if ((*((UINT32P) (0x2405001c)) & 0x76870000) != 0x76870000) { //tdd mbist_done
printf("tdd mbist_done is not ready %d\n", __LINE__);
ret = -1;
}
}
/* TINFO="tdd mbist_done" */
}
#if 1
printf("==============================================After 1's MBIST===============================\n");
printf("[img repair status] IMG:0x150001a4=0x%x\n",*((UINT32P) (0x150001a4)));
printf("[Repair SRAM Check] 1nd MBIST TEST Check: START\n");
printf("[Repair SRAM Check] IMAGE:0x15000038=0x%x\n",*((UINT32P) (0x15000038)));
printf("[Repair SRAM Check] hspa3:0x236e002c=0x%x\n",*((UINT32P) (0x236e002c)));
printf("[Repair SRAM Check] efuse:0x10206040=0x%x\n",*((UINT32P) (0x10206040)));
printf("[Repair SRAM Check] efuse:0x10206044=0x%x\n",*((UINT32P) (0x10206044)));
printf("[Repair SRAM Check] TDD:0x2405001c=0x%x\n",*((UINT32P) (0x2405001c)));
printf("[Repair SRAM Check] MBIST TEST Check: END\n");
printf("\n");
printf("[Repair SRAM Check] After 1nd MBIST TEST: START\n");
printf("[Repair SRAM Check] MFG:0x130000a8=0x%x\n",*((UINT32P) (0x130000a8)));
printf("[Repair SRAM Check] MM:0x14000804=0x%x\n",*((UINT32P) (0x14000804)));
printf("[Repair SRAM Check] IMG:0x15000048=0x%x\n",*((UINT32P) (0x15000048)));
printf("[Repair SRAM Check] IMG:0x0x1500004c=0x%x\n",*((UINT32P) (0x1500004c)));
printf("[Repair SRAM Check] MD:0x200e0030=0x%x\n",*((UINT32P) (0x200e0030)));
printf("[Repair SRAM Check] MD:0x200e0034=0x%x\n",*((UINT32P) (0x200e0034)));
printf("[Repair SRAM Check] HSPA:0x236e0034=0x%x\n",*((UINT32P) (0x236e0034)));
printf("[Repair SRAM Check] HSPA:0x236e0038=0x%x\n",*((UINT32P) (0x236e0038)));
printf("[Repair SRAM Check] TDD:0x2405002c=0x%x\n",*((UINT32P) (0x2405002c)));
printf("[Repair SRAM Check] TDD:0x24050030=0x%x\n",*((UINT32P) (0x24050030)));
printf("[Repair SRAM Check] TDD:0x24050034=0x%x\n",*((UINT32P) (0x24050034)));
printf("\n");
printf("[Repair SRAM Check] VENCPLL Monitor START\n");
*((UINT32P) (0x10000220)) = 0x80;
*((UINT32P) (0x10000214)) = 0x0;
*((UINT32P) (0x10000100)) = 0x1600;
*((UINT32P) (0x10000220)) = 0x81;
udelay(500);
printf("[Repair SRAM Check] CLK26CALI_0:0x1000_0220=0x%x\n",*((UINT32P) (0x10000220)));
printf("[Repair SRAM Check] CLK26CALI_1:0x1000_0224=0x%x\n",*((UINT32P) (0x10000224)));
/*
printf("[Repair SRAM Check] VENCPLL_CON0:0x1000F800=0x%x\n",*((UINT32P) (0x1000F800)));
printf("[Repair SRAM Check] VENCPLL_CON1:0x1000F804=0x%x\n",*((UINT32P) (0x1000F804)));
printf("[Repair SRAM Check] VENCPLL_CON2:0x1000F808=0x%x\n",*((UINT32P) (0x1000F808)));
printf("[Repair SRAM Check] VENCPLL_PWR_CON0:0x1000F80C=0x%x\n",*((UINT32P) (0x1000F80C)));
*/
printf("[Repair SRAM Check] VENCPLL Monitor End");
printf("\n");
printf("=================================================END=========================\n");
#endif
/* TINFO="check mbist_fail" */
/* TINFO="mfg mbist_fail" */
#if 0
// ------------------------------------------------------------------
//WHILE could change to IF, check correlation result
// ------------------------------------------------------------------
if ((*((UINT32P) (0x130000a8)) & 0x0007fff8)) // [18:3]: mfgsys mbist_fail
printf("mfgsys sram fail %d\n", __LINE__);
/* TINFO="mm mbist_fail" */
if ((*((UINT32P) (0x14000804)) & 0x00040000)) // [18] mm mbist_fail
printf("mm sram fail %d\n", __LINE__);
/* TINFO="img mbist_fail"
[31:26]: img mbist_fail
[40, 37, 34:32]: mbist_fail */
if ((*((UINT32P) (0x15000048)) & 0xfc000000)
|| (*((UINT32P) (0x1500004c)) & 0x00000127))
printf("img sram fail %d\n", __LINE__);
/* TINFO="md mbist_fail"
[28:26, 16:9] mbist_fail, [0]: mbist_fail_all md
[28:0] mbist_fail */
if (((*((UINT32P) (0x200e0030)) & 0x1c03fc01))
|| ((*((UINT32P) (0x200e0034)) & 0x1fffffff)))
printf("md sram fail %d\n", __LINE__);
/* TINFO="hspa3 mbist_fail"
[31:29] mbist_fail hspa3
[5:0] mbist_fail */
if (((*((UINT32P) (0x236e0034)) & 0xc0000000))
|| ((*((UINT32P) (0x236e0038)) & 0x0000003f)))
printf("hspa3 sram fail %d\n", __LINE__);
/* TINFO="tdd mbist_fail"
[16:11] mbist_fail tdd
[31:28, 26:23, 20, 19] mbist_fail
[1] mbist_fail */
if (((*((UINT32P) (0x2405002c)) & 0x0001f800))
|| ((*((UINT32P) (0x24050030)) & 0xf7980000))
|| ((*((UINT32P) (0x24050034)) & 0x00000001)))
printf("tdd sram fail %d\n", __LINE__);
/* TINFO="check repair status" */
/* TINFO="check mfg status" */
// ------------------------------------------------------------------
//WHILE could change to IF, correlation result
// ------------------------------------------------------------------
if ((*((UINT32P) (0x13000104)) & 0xff000000)) //[31:24] rp_fail, [23:16] rp_ok, [6:0]: fuse , can't rp_fail, but rp_ok 1 or 0 is ok
printf("mfg repair failed %d\n", __LINE__);
if ((*((UINT32P) (0x13000108)) & 0xff000000)) //[31:24] rp_fail, [23:16] rp_ok, [6:0]: fuse ,can't rp_fail, but rp_ok 1 or 0 is ok
printf("mfg repair failed %d\n", __LINE__);
/* TINFO="check mm status" */
if ((*((UINT32P) (0x14000854)) & 0x00000001)) //[0] mm rp_fail
printf("mm repair failed %d\n", __LINE__);
/* TINFO="check img status" */
if ((*((UINT32P) (0x150001a4)) & 0x07ff0000)) // [26:16] imgsys rp_fail, [10:0] rp_ok
printf("img repair failed %d\n", __LINE__);
/* TINFO="check md status" */
if ((*((UINT32P) (0x200e0050)) & 0xffffffff)) // md rp_fail [31:0]
printf("md repair failed %d\n", __LINE__);
if ((*((UINT32P) (0x200e0054)) & 0x000000ff)) // md rp_fail [7:0]
printf("md repair failed %d\n", __LINE__);
/* TINFO="check hspa3 status" */
if ((*((UINT32P) (0x236e0094)) & 0x000000ff)) // hspa3 rp_fail [7:0]
printf("hspa3 repair failed %d\n", __LINE__);
/* TINFO="check tdd status" */
if ((*((UINT32P) (0x24050064)) & 0x0001ffff)) // tdd rp_fail [16:0]
printf("tdd repair failed %d\n", __LINE__);
#endif
// ------------------------------------------------------------------
/* TINFO="reg_load_fuse" */
#if 1
*((UINT32P) (0x100011a8)) = 0x000f0000; //INFRA fuse load for mfg/img/mm
if( (*((UINT32P) (0x10206040)) & 0x00400000) == 0x0) { //MD efuse not disable
*((UINT32P) (0x200e0044)) = 0x00000002; //MDMCU 0: mbist_rstb, 1: rp_rstb, 2: load_fuse
*((UINT32P) (0x200e0044)) = 0x00000007; // load fuse
if( (*((UINT32P) (0x10206044)) & 0x00000001) == 0x0) { //HSPA efuse not disable
*((UINT32P) (0x236e00a8)) = 0x00000001; //hspa3 0: load fuse
}
if( (*((UINT32P) (0x10206044)) & 0x00000080) == 0x0) { //TDD efuse not disable
*((UINT16P) (0x2400001e)) = 0x004d; //6: tdd load fuse
}
}
#endif
// ------------------------------------------------------------------
/* TINFO="clear mbist_mode" */
*((UINT32P) (0x13000060)) = 0x00000000; // [1] mbist_mode, [31]: mbist_rstb mfg
*((UINT32P) (0x14000810)) = 0x00000000; // [6] mbist_mode mm
*((UINT32P) (0x15000074)) = 0x00000000; // [12:10] mbist_mode img
if( (*((UINT32P) (0x10206040)) & 0x00400000) == 0x0) { //MD efuse not disable
*((UINT32P) (0x200e0000)) = 0x00000000; // [11:4,2:1] mbist_mode md
if( (*((UINT32P) (0x10206044)) & 0x00000001) == 0x0) { //HSPA efuse not disable
*((UINT32P) (0x236e0000)) = 0x00000000; // [7] mbist_mode md_hspa3
}
if( (*((UINT32P) (0x10206044)) & 0x00000080) == 0x0) { //TDD efuse not disable
*((UINT32P) (0x24050000)) = 0x00000000; // [29~27, 25~24,22,17~15] mbist_mode tdd
}
}
//printf("[Repair SRAM Check ] Start 2nd MBIST\n");
// ------------------------------------------------------------------
/* TINFO="re-set mbist_rstb" */
*((UINT32P) (0x13000060)) = 0x00000000; // set mfgsys mbist_rstb, [31]:mbist_rstb
*((UINT32P) (0x1400081C)) = 0x00000000; // set mmsys mbist_rstb, [15]: mbist_rstb [31:16]: mm background
*((UINT32P) (0x15000070)) = 0x00000000; // set imgsys mbist_rstb, [0]: mbist_rstb
if( (*((UINT32P) (0x10206040)) & 0x00400000) == 0x0) { //MD efuse not disable
*((UINT32P) (0x23008040)) = 0x00000000; // set modemsys mbist_rstb, [0]: mbist_rstb
if( (*((UINT32P) (0x10206044)) & 0x00000001) == 0x0) { //HSPA efuse not disable
*((UINT32P) (0x236e007c)) = 0x00000000; // set hspa3sys mbist_rst, [0]: mbist_rstbb
}
if( (*((UINT32P) (0x10206044)) & 0x00000080) == 0x0) { //TDD efuse not disable
*((UINT32P) (0x24050068)) = 0x00000000; // set tddsys mbist_rst, [0]: mbist_rstbb
}
}
// ------------------------------------------------------------------
//release mbist_rstb
/* TINFO="release mbist_rstb" */
*((UINT32P) (0x13000060)) = 0x80000000; // release mfgsys mbist_rstb, [31]:mbist_rstb
*((UINT32P) (0x13000100)) = 0x00000001; // [0] mfg rp_rstb=1
*((UINT32P) (0x1400081C)) = 0x00008000; // release mmsys mbist_rstb, [15]: mbist_rstb [31:16]: mm background (TBD)
*((UINT32P) (0x15000070)) = 0x00000001; // release vencsys mbist_rstb, [0]: mbist_rstb
if( (*((UINT32P) (0x10206040)) & 0x00400000) == 0x0) { //MD efuse not disable
*((UINT32P) (0x23008040)) = 0x00000001; // release modemsys mbist_rstb, [0]: mbist_rstb
if( (*((UINT32P) (0x10206044)) & 0x00000001) == 0x0) { //HSPA efuse not disable
*((UINT32P) (0x236e007c)) = 0x00000001; // release hspa3sys mbist_rst, [0]: mbist_rstbb
}
if( (*((UINT32P) (0x10206044)) & 0x00000080) == 0x0) { //TDD efuse not disable
*((UINT32P) (0x24050068)) = 0x00000001; // release tddsys mbist_rst, [0]: mbist_rstbb
}
}
// ------------------------------------------------------------------
//set mbist_mode=1
/* TINFO="set mbist_mode" */
*((UINT32P) (0x13000060)) = 0x80000002; // [1] mbist_mode, [31]: mbist_rstb mfg
*((UINT32P) (0x14000810)) = 0x00000040; // [6] mbist_mode mm
*((UINT32P) (0x15000074)) = 0x00001c00; // [12:10] mbist_mode img
if( (*((UINT32P) (0x10206040)) & 0x00400000) == 0x0) { //MD efuse not disable
*((UINT32P) (0x200e0000)) = 0x00000ff6; // [11:4,2:1] mbist_mode md
if( (*((UINT32P) (0x10206044)) & 0x00000001) == 0x0) { //HSPA efuse not disable
*((UINT32P) (0x236e0000)) = 0x00000080; // [7] mbist_mode md_hspa3
}
if( (*((UINT32P) (0x10206044)) & 0x00000080) == 0x0) { //TDD efuse not disable
*((UINT32P) (0x24050000)) = 0x3b438000; // [29~27, 25~24,22,17~15] mbist_mode tdd
}
}
// ------------------------------------------------------------------
udelay(2000);
/* TINFO="wait mbist_done" */
if ((*((UINT32P) (0x13000090)) & 0x7fff8) != 0x7fff8) { //mfg mbist_done
printf("mfg mbist_done is not ready %d\n", __LINE__);
ret = -1;
}
// printf("[Repair SRAM Check ] Value check 1nd MM:0x14000800=0x%x\n",*((UINT32P) (0x14000800)));
/* TINFO="mfg mbist_done" */
if ((*((UINT32P) (0x14000800)) & 0x20f) != 0x20f) { //mm mbist_done
printf("mm mbist_done is not ready %d\n", __LINE__);
printf("[Repair SRAM Check ] 2nd MM:0x14000800=0x%x\n",*((UINT32P) (0x14000800)));
printf("[Repair SRAM Check ] 2nd MM:0x14000804=0x%x\n",*((UINT32P) (0x14000804)));
ret = -1;
}
// printf("[Repair SRAM Check] Value check 1nd IMG:0x15000038=0x%x\n",*((UINT32P) (0x15000038)));
/* TINFO="mm mbist_done" */
if ((*((UINT32P) (0x15000038)) & 0x1c40) != 0x1c40) { //img mbist_done
printf("img mbist_done is not ready %d\n", __LINE__);
printf("[Repair SRAM Check] 2nd IMG:0x15000038=0x%x\n",*((UINT32P) (0x15000038)));
printf("[Repair SRAM Check] 2nd IMG:0x15000048=0x%x\n",*((UINT32P) (0x15000048)));
printf("[Repair SRAM Check] 2nd IMG:0x1500004c=0x%x\n",*((UINT32P) (0x1500004c)));
ret = -1;
}
/* TINFO="img mbist_done" */
if( (*((UINT32P) (0x10206040)) & 0x00400000) == 0x0) { //MD efuse not disable
if ((*((UINT32P) (0x200e0024)) & 0x1fec) != 0x1fec) { //md mbist_done
printf("md mbist_done is not ready %d\n", __LINE__);
ret = -1;
}
/* TINFO="mdmcu mbist_done" */
if( (*((UINT32P) (0x10206044)) & 0x00000001) == 0x0) { //HSPA efuse not disable
if ((*((UINT32P) (0x236e002c)) & 0x4) != 0x4) { //hspa3 mbist_done
printf("hspa3 mbist_done is not ready %d\n", __LINE__);
ret = -1;
}
/* TINFO="hspa3 mbist_done" */
}
if( (*((UINT32P) (0x10206044)) & 0x00000080) == 0x0) { //TDD efuse not disable
if ((*((UINT32P) (0x2405001c)) & 0x76870000) != 0x76870000) { //tdd mbist_done
printf("tdd mbist_done is not ready %d\n", __LINE__);
ret = -1;
}
/* TINFO="tdd mbist_done" */
}
}
// ------------------------------------------------------------------
/* TINFO="check mbist_fail" */
/* TINFO="mfg mbist_fail" */
if ((*((UINT32P) (0x130000a8)) & 0x0007fff8)) { // [18:3]: mfgsys mbist_fail
printf("mfgsys sram fail %d\n", __LINE__);
ret = -1;
}
/* TINFO="mm mbist_fail" */
if ((*((UINT32P) (0x14000804)) & 0x00040000)) { // [18] mm mbist_fail
printf("mm sram fail %d\n", __LINE__);
ret = -1;
}
/* TINFO="img mbist_fail"
[31:26]: img mbist_fail
[40, 37, 34:32]: mbist_fail */
if (((*((UINT32P) (0x15000048)) & 0xfc000000))
|| ((*((UINT32P) (0x1500004c)) & 0x00000127))) {
printf("img sram fail %d\n", __LINE__);
ret = -1;
}
if( (*((UINT32P) (0x10206040)) & 0x00400000) == 0x0) { //MD efuse not disable
/* TINFO="md mbist_fail"
[28:26, 16:9] mbist_fail, [0]: mbist_fail_all md
[28:0] mbist_fail */
if (((*((UINT32P) (0x200e0030)) & 0x1c03fc01))
|| ((*((UINT32P) (0x200e0034)) & 0x1fffffff))) {
printf("md sram fail %d\n", __LINE__);
ret = -1;
}
if( (*((UINT32P) (0x10206044)) & 0x00000001) == 0x0) { //HSPA efuse not disable
/* TINFO="hspa3 mbist_fail"
[31:29] mbist_fail hspa3
[5:0] mbist_fail */
if (((*((UINT32P) (0x236e0034)) & 0xc0000000))
|| ((*((UINT32P) (0x236e0038)) & 0x0000003f))) {
printf("hspa3 sram fail %d\n", __LINE__);
ret = -1;
}
}
if( (*((UINT32P) (0x10206044)) & 0x00000080) == 0x0) { //TDD efuse not disable
/* TINFO="tdd mbist_fail"
[16:11] mbist_fail tdd
[31:28, 26:23, 20, 19] mbist_fail
[1] mbist_fail */
if (((*((UINT32P) (0x2405002c)) & 0x0001f800))
|| ((*((UINT32P) (0x24050030)) & 0xf7980000))
|| ((*((UINT32P) (0x24050034)) & 0x00000001))) {
printf("hspa3 sram fail %d\n", __LINE__);
ret = -1;
}
}
}
#if 0
printf("===================================After 2nd MBIST TEST============================\n");
printf("[Repair SRAM Check] 2nd MBIST TEST Check: START\n");
printf("[Repair SRAM Check] IMAGE:0x15000038=0x%x\n",*((UINT32P) (0x15000038)));
printf("[Repair SRAM Check] hspa3:0x236e002c=0x%x\n",*((UINT32P) (0x236e002c)));
printf("[Repair SRAM Check] efuse:0x10206040=0x%x\n",*((UINT32P) (0x10206040)));
printf("[Repair SRAM Check] efuse:0x10206044=0x%x\n",*((UINT32P) (0x10206044)));
printf("[Repair SRAM Check] TDD:0x2405001c=0x%x\n",*((UINT32P) (0x2405001c)));
printf("[Repair SRAM Check] MBIST TEST Check: END\n");
printf("\n");
printf("[Repair SRAM Check] After 2nd MBIST TEST: START\n");
printf("[Repair SRAM Check] MFG:0x130000a8=0x%x\n",*((UINT32P) (0x130000a8)));
printf("[Repair SRAM Check] MM:0x14000804=0x%x\n",*((UINT32P) (0x14000804)));
printf("[Repair SRAM Check] IMG:0x15000048=0x%x\n",*((UINT32P) (0x15000048)));
printf("[Repair SRAM Check] IMG:0x0x1500004c=0x%x\n",*((UINT32P) (0x1500004c)));
printf("[Repair SRAM Check] MD:0x200e0030=0x%x\n",*((UINT32P) (0x200e0030)));
printf("[Repair SRAM Check] MD:0x200e0034=0x%x\n",*((UINT32P) (0x200e0034)));
printf("[Repair SRAM Check] HSPA:0x236e0034=0x%x\n",*((UINT32P) (0x236e0034)));
printf("[Repair SRAM Check] HSPA:0x236e0038=0x%x\n",*((UINT32P) (0x236e0038)));
printf("[Repair SRAM Check] TDD:0x2405002c=0x%x\n",*((UINT32P) (0x2405002c)));
printf("[Repair SRAM Check] TDD:0x24050030=0x%x\n",*((UINT32P) (0x24050030)));
printf("[Repair SRAM Check] TDD:0x24050034=0x%x\n",*((UINT32P) (0x24050034)));
printf("[Repair SRAM Check] After 2nd MBIST TEST: END\n");
printf("\n");
#endif
printf("[Repair SRAM Check] VENCPLL Monitor START\n");
*((UINT32P) (0x10000220)) = 0x80;
*((UINT32P) (0x10000214)) = 0x0;
*((UINT32P) (0x10000100)) = 0x1600;
*((UINT32P) (0x10000220)) = 0x81;
udelay(500);
printf("[Repair SRAM Check] CLK26CALI_0:0x1000_0220=0x%x\n",*((UINT32P) (0x10000220)));
printf("[Repair SRAM Check] CLK26CALI_1:0x1000_0224=0x%x\n",*((UINT32P) (0x10000224)));
/*
printf("[Repair SRAM Check] VENCPLL_CON0:0x1000F800=0x%x\n",*((UINT32P) (0x1000F800)));
printf("[Repair SRAM Check] VENCPLL_CON1:0x1000F804=0x%x\n",*((UINT32P) (0x1000F804)));
printf("[Repair SRAM Check] VENCPLL_CON2:0x1000F808=0x%x\n",*((UINT32P) (0x1000F808)));
printf("[Repair SRAM Check] VENCPLL_PWR_CON0:0x1000F80C=0x%x\n",*((UINT32P) (0x1000F80C)));
*/
printf("[Repair SRAM Check] VENCPLL Monitor End\n");
printf("\n");
printf("=============================================END=================================\n");
/*
printf("[Repair SRAM Check] VProc Monitor START");
ret=pmic_read_interface(0x21E,®_val,0xFFFF,0);
printf("Reg[0x21E]=0x%x, %d\n", reg_val, ret);
ret=pmic_read_interface(0x220,®_val,0xFFFF,0);
printf("Reg[0x220]=0x%x, %d\n", reg_val, ret);
ret=pmic_read_interface(0x222,®_val,0xFFFF,0);
printf("Reg[0x222]=0x%x, %d\n", reg_val, ret);
ret=pmic_read_interface(0x216,®_val,0xFFFF,0);
printf("Reg[0x216]=0x%x, %d\n", reg_val, ret);
ret=pmic_read_interface(0x224,®_val,0xFFFF,0);
printf("Reg[0x224]=0x%x, %d\n", reg_val, ret);
printf("[Repair SRAM Check] VProc Monitor End");
printf("\n");
*/
// ------------------------------------------------------------------
/* TINFO="REVERT setting " */
/* TINFO="clear mbist mode =0 " */
*((UINT32P) (0x13000060)) = 0x00000000; // [1] mbist_mode, [31]: mbist_rstb mfg
*((UINT32P) (0x14000810)) = 0x00000000; // [6] mbist_mode mm
*((UINT32P) (0x15000074)) = 0x00000000; // [12:10] mbist_mode img
if( (*((UINT32P) (0x10206040)) & 0x00400000) == 0x0) { //MD efuse not disable
*((UINT32P) (0x200e0000)) = 0x00000000; // [11:4,2:1] mbist_mode md
if( (*((UINT32P) (0x10206044)) & 0x00000001) == 0x0) { //HSPA efuse not disable
*((UINT32P) (0x236e0000)) = 0x00000000; // [7] mbist_mode md_hspa3
}
if( (*((UINT32P) (0x10206044)) & 0x00000080) == 0x0) { //TDD efuse not disable
*((UINT32P) (0x24050000)) = 0x00000000; // [29~27, 25~24,22,17~15] mbist_mode tdd
}
}
rgu_swsys_reset(WD_MD_RST);
#if 0
// ------------------------------------------------------------------
if( (*((UINT32P) (0x10206040)) & 0x00400000) == 0x0) { //MD efuse not disable
/* TINFO="MD MTCMOS" */
*((UINT32P) (0x23010810)) = 0xa200; //md_hspa4 MODEM2G_TOPSM_RM_PWR_CON4
/* TINFO="MD MTCMOS1" */
*((UINT32P) (0x2301080c)) = 0xa200; //md_hspa3 MODEM2G_TOPSM_RM_PWR_CON3
/* TINFO="MD MTCMOS2" */
*((UINT32P) (0x23010804)) = 0xa200; //md_hspa1 MODEM2G_TOPSM_RM_PWR_CON1
/* TINFO="MD MTCMOS3" */
*((UINT32P) (0x23010800)) = 0xa200; //md2g MODEM2G_TOPSM_RM_PWR_CON0
/* TINFO="MD MTCMOS4" */
*((UINT32P) (0x23010018)) = 0x0; //MODEM2G_TOPSM_RM_TMR_PWR0
/* TINFO="MD MTCMOS5" */
/*TINFO="polling MD2g power off" */
// udelay(40);
udelay(2000);
if ((*((UINT32P) (0x23010820)) & 0x00030000) != 0x0) {
printf("MD2g power off is not ready %d\n", __LINE__);
ret = -1;
}
// ------------------------------------------------------------------
/*TINFO="MD clock enable" */
*((UINT32P) (0x20000458)) = 0x0; //turn md infrasys clock
*((UINT32P) (0x23000010)) = 0xffffffff; //turn md modem clock
*((UINT32P) (0x23000018)) = 0xffffffff; //turn md modem clock
*((UINT32P) (0x23000098)) = 0x0; //turn md modem clock
if( (*((UINT32P) (0x10206044)) & 0x00000001) == 0x0) { //HSPA efuse not disable
*((UINT32P) (0x2367002c)) = 0xffffffff; //turn md hspa3 clock
*((UINT32P) (0x23670010)) = 0xffffffff; //turn md hspa3 clock
}
if( (*((UINT32P) (0x10206044)) & 0x00000080) == 0x0) { //TDD efuse not disable
//*((UINT16P) (0x2400001e)) = 0x0002; // tddsys mbist_mem_clk_en
//*((UINT16P) (0x24000422)) = 0x4208; //turn on tddsys clock
//*((UINT16P) (0x24000422)) = 0xc208; //turn on tddsys clock
*((UINT16P) (0x24000018)) = 0x0; //tdd pmu sft rst
udelay(100); //wait > 62.5us
*((UINT16P) (0x24000018)) = 0x1; //set 1, after reset
}
//printf("5\n");
// ------------------------------------------------------------------
/*TINFO="MD clock switch" */
/* TINFO=" rdata = %h", *((UINT32P)(0x22c00040)) */
*((UINT32P) (0x22c00040)) = 0x0; // MD2GSYS_clock switch
//SWITCH PLL clock
*((UINT32P) (0x2000045c)) = 0x1008510; //MD_GLOBAL_CON1, BUS_CLK = PLL Freq (not 26MHz)
*((UINT32P) (0x20120060)) = 0x1010; //PLL_CLKSW_CKSEL0, Bit 15-12: MDMCU_CLK = MCUPLL 481MHz, Bit 7- 4: DSP_CLK = MCUPLL DIV3 = 481 MHz / 2 = 240.5 MHz
*((UINT32P) (0x20120064)) = 0x1000; //PLL_CLKSW_CKSEL1, Bit 15-12: BUS_CLK = MCUPLL DIV2 = 481 MHz / 4 = 120.25MHz
*((UINT32P) (0x20120068)) = 0x1110; //PLL_CLKSW_CKSEL2, Bit 15-12: FX64W_CLK = WPLL = 245.76MHz, Bit 11- 8: FX16G_CLK = MDPLL DIV3 = 416 MHz / 2 = 208 MHz, Bit 7- 4: HW64W_CLK = WHPLL = 250.25MHz
/*TINFO="MD PLL " */
*((UINT32P) (0x2012004c)) = 0x1111; // bit 15,8,1,0 set to 0
*((UINT32P) (0x2012004c)) = 0x9111; //PLL_PLL_CON3, bit 12,4 set to 0// [POWER ON] Bit15: MCUPLL, Bit 8: WPLL
/* TINFO="wait 2u"*/
udelay(2);
*((UINT32P) (0x20120048)) = 0x1111; //PLL_PLL_CON2, bit 12,10, 8, 6, 2 set to 0// [TOPSM & SW CTRL] Bit12: MDPLL, Bit 8: MCUPLL, Bit 4: WPLL, Bit 0: WHPLL
*((UINT32P) (0x20120700)) = 0x11; //PLL_PLLTD_CON0, bit 0 set to 0// [FHCTL & SW CTRL] Bit 4: CHG_CTRL
*((UINT32P) (0x20120100)) = 0x410f; // Enable PLLs, PLL_MDPLL_CON0
*((UINT32P) (0x20120140)) = 0x0810; // Enable PLLs, PLL_MCUPLL_CON0
*((UINT32P) (0x201201c0)) = 0x0800; // Enable PLLs, PLL_WPLL_CON0
*((UINT32P) (0x20120200)) = 0x0500; // Enable PLLs, PLL_WHPLL_CON0
*((UINT32P) (0x20120110)) = 0x8003; // PLL_MDPLL_CON4, bit0 set to 0
/*TINFO="enable MD PLL" */
*((UINT32P) (0x2012004c)) = 0x9311; //PLL_PLL_CON3, bit 12,4 set to 0// [POWER ON] Bit15: MCUPLL, Bit 8: WPLL
/* TINFO="wait 2u"*/
udelay(2);
*((UINT32P) (0x2012004c)) = 0x9331; //PLL_PLL_CON3, bit 12,4 set to 0// [POWER ON] Bit15: MCUPLL, Bit 8: WPLL
*((UINT32P) (0x201200ac)) = 0x0; //PLL_DFS_CON7, bit 0~5 set to 1 // [FORCE ON] Bit 5: SYSCLK, Bit 4: MDPLL, Bit 3: WHPLL, Bit 2: WPLL, Bit 1: MCUPLL, Bit 0: No use (HW limit when boot)
/* TINFO="MD TOP MTCMOS" */
*((UINT32P) (0x20030018)) = 0x0; //MD_TOPSM_RM_TMR_PWR0
/* TINFO="MD MTCMOS6" */
}
// ------------------------------------------------------------------
// ------------------------------------------------------------------
/* TINFO="MFG DCM" */
//*((UINT32P)(0x13000010)) = 0xc03f; //disable mfg DCM [15]
// ------------------------------------------------------------------
#endif
/*TINFO="cksys clock switch" */
*CLK_CFG_0 = rdata_cksw0 & 0x1F1F1F1F;
*CLK_CFG_1 = rdata_cksw1 & 0x1F1F1F1F;
*CLK_CFG_2 = rdata_cksw2 & 0x1F1F1F1F;
*CLK_CFG_3 = rdata_cksw3 & 0x1F1F1F1F;
*CLK_CFG_4 = rdata_cksw4 & 0x1F1F1F1F;
udelay(1);
if (((*CKSTA_REG) & 0xffffffff) != 0x0) {
printf("clock switch is not ready %d\n", __LINE__);
ret = -1;
}
*CLK_CFG_0_SET = rdata_cksw0 & 0x80808080; //mem clock[8] not switch or will let dram hang(w/o set PLL clock source)
*CLK_CFG_1_SET = rdata_cksw1 & 0x80808080;
*CLK_CFG_2_SET = rdata_cksw2 & 0x80808080;
*CLK_CFG_3_SET = rdata_cksw3 & 0x80808080;
*CLK_CFG_4_SET = rdata_cksw4 & 0x808080E0;
// *INFRA_TOPCKGEN_DCMCTL = 0x0; //Set this register before AXI clock switch to fast clock
////PLL_EN = 0
//*MMPLL_CON0 &= 0xfffffffe;
////*VENCPLL_CON0 &= 0xfffffffe;
////ISO_EN = 1
//*MMPLL_PWR_CON0 = 0x3;
////*VENCPLL_PWR_CON0 = 0x3;
////PWR_ON = 0
//*MMPLL_PWR_CON0 = 0x2;
////*VENCPLL_PWR_CON0 = 0x2;
// ------------------------------------------------------------------
// /* TINFO="clock enable" */
//*((UINT32P)(0x14000108)) = rdata_mm0;//turn mmsys clock
//*((UINT32P)(0x14000118)) = rdata_mm1;//turn mmsys clock
//*((UINT32P)(0x15000008)) = 0x0;//turn img clock
//*((UINT32P)(0x15004150)) = 0x0;//turn img clock
/* TINFO="AP MTCMOS" */
*((UINT32P) (0x10006214)) = 0x0000010d; //MFG MTCOMS
*((UINT32P) (0x10006214)) = 0x0000030d; //MFG MTCOMS
*((UINT32P) (0x10006214)) = 0x0000070d; //MFG MTCOMS
*((UINT32P) (0x10006214)) = 0x00000f0d; //MFG MTCOMS
*((UINT32P) (0x10006214)) = 0x00000f0f; //MFG MTCOMS
*((UINT32P) (0x10006214)) = 0x00000f1e; //MFG MTCOMS
*((UINT32P) (0x10006214)) = 0x00000f1a; //MFG MTCOMS
*((UINT32P) (0x10006214)) = 0x00000f12; //MFG MTCOMS
*((UINT32P) (0x10006238)) = 0x0000010d; //ISP MTCOMS
*((UINT32P) (0x10006238)) = 0x0000030d; //ISP MTCOMS
*((UINT32P) (0x10006238)) = 0x0000070d; //ISP MTCOMS
*((UINT32P) (0x10006238)) = 0x00000f0d; //ISP MTCOMS
*((UINT32P) (0x10006238)) = 0x00000f0f; //ISP MTCOMS
*((UINT32P) (0x10006238)) = 0x00000f1e; //ISP MTCOMS
*((UINT32P) (0x10006238)) = 0x00000f1a; //ISP MTCOMS
*((UINT32P) (0x10006238)) = 0x00000f12; //ISP MTCOMS
/* DISP already opened in preloader
*((UINT32P) (0x1000623c)) = 0x0000010d; //DISP MTCOMS
*((UINT32P) (0x1000623c)) = 0x0000030d; //DISP MTCOMS
*((UINT32P) (0x1000623c)) = 0x0000070d; //DISP MTCOMS
*((UINT32P) (0x1000623c)) = 0x00000f0d; //DISP MTCOMS
*((UINT32P) (0x1000623c)) = 0x00000f0f; //DISP MTCOMS
*((UINT32P) (0x1000623c)) = 0x00000f1e; //DISP MTCOMS
*((UINT32P) (0x1000623c)) = 0x00000f1a; //DISP MTCOMS
*((UINT32P) (0x1000623c)) = 0x00000f12; //DISP MTCOMS
*/
// /* TINFO="CPU revert" */
// *ACLKEN_DIV = 0x0; //div2
// *PCLKEN_DIV = 0x10; //div4
// *MEM_PWR_CTRL = 0x0; //slpb_dly and mem_off_dly
// *MCU_BIU_CON = 0x7f0; //enable out-of-order queue
// *CA7_MISC_CONFIG = 0x9c000000;
return ret;
}