static void sun4c_intctl_save(QEMUFile *f, void *opaque)
{
Sun4c_INTCTLState *s = opaque;
qemu_put_8s(f, &s->reg);
qemu_put_8s(f, &s->pending);
}
void virtio_save(VirtIODevice *vdev, QEMUFile *f)
{
int i;
if (vdev->binding->save_config)
vdev->binding->save_config(vdev->binding_opaque, f);
qemu_put_8s(f, &vdev->status);
qemu_put_8s(f, &vdev->isr);
qemu_put_be16s(f, &vdev->queue_sel);
qemu_put_be32s(f, &vdev->guest_features);
qemu_put_be32(f, vdev->config_len);
qemu_put_buffer(f, vdev->config, vdev->config_len);
for (i = 0; i < VIRTIO_PCI_QUEUE_MAX; i++) {
if (vdev->vq[i].vring.num == 0)
break;
}
qemu_put_be32(f, i);
for (i = 0; i < VIRTIO_PCI_QUEUE_MAX; i++) {
if (vdev->vq[i].vring.num == 0)
break;
qemu_put_be32(f, vdev->vq[i].vring.num);
qemu_put_be64(f, vdev->vq[i].pa);
qemu_put_be16s(f, &vdev->vq[i].last_avail_idx);
if (vdev->binding->save_queue)
vdev->binding->save_queue(vdev->binding_opaque, i, f);
}
}
static void kbd_save(QEMUFile* f, void* opaque)
{
KBDState *s = (KBDState*)opaque;
qemu_put_8s(f, &s->write_cmd);
qemu_put_8s(f, &s->status);
qemu_put_8s(f, &s->mode);
qemu_put_8s(f, &s->pending);
}
static void slavio_serial_save_chn(QEMUFile *f, ChannelState *s)
{
qemu_put_be32s(f, &s->irq);
qemu_put_be32s(f, &s->reg);
qemu_put_be32s(f, &s->rxint);
qemu_put_be32s(f, &s->txint);
qemu_put_be32s(f, &s->rxint_under_svc);
qemu_put_be32s(f, &s->txint_under_svc);
qemu_put_8s(f, &s->rx);
qemu_put_8s(f, &s->tx);
qemu_put_buffer(f, s->wregs, 16);
qemu_put_buffer(f, s->rregs, 16);
}
static void tcx_save(QEMUFile *f, void *opaque)
{
TCXState *s = opaque;
qemu_put_be16s(f, &s->height);
qemu_put_be16s(f, &s->width);
qemu_put_be16s(f, &s->depth);
qemu_put_buffer(f, s->r, 256);
qemu_put_buffer(f, s->g, 256);
qemu_put_buffer(f, s->b, 256);
qemu_put_8s(f, &s->dac_index);
qemu_put_8s(f, &s->dac_state);
}
static void max111x_save(QEMUFile *f, void *opaque)
{
struct max111x_s *s = (struct max111x_s *) opaque;
int i;
qemu_put_8s(f, &s->tb1);
qemu_put_8s(f, &s->rb2);
qemu_put_8s(f, &s->rb3);
qemu_put_be32(f, s->inputs);
qemu_put_be32(f, s->com);
for (i = 0; i < s->inputs; i ++)
qemu_put_byte(f, s->input[i]);
}
static void slavio_serial_save_chn(QEMUFile *f, ChannelState *s)
{
int tmp;
tmp = 0;
qemu_put_be32s(f, &tmp); /* unused, was IRQ. */
qemu_put_be32s(f, &s->reg);
qemu_put_be32s(f, &s->rxint);
qemu_put_be32s(f, &s->txint);
qemu_put_be32s(f, &s->rxint_under_svc);
qemu_put_be32s(f, &s->txint_under_svc);
qemu_put_8s(f, &s->rx);
qemu_put_8s(f, &s->tx);
qemu_put_buffer(f, s->wregs, SERIAL_REGS);
qemu_put_buffer(f, s->rregs, SERIAL_REGS);
}
static int put_uint8(QEMUFile *f, void *pv, size_t size, VMStateField *field,
QJSON *vmdesc)
{
uint8_t *v = pv;
qemu_put_8s(f, v);
return 0;
}
static void rtc_save(QEMUFile *f, void *opaque)
{
RTCState *s = opaque;
qemu_put_buffer(f, s->cmos_data, 128);
qemu_put_8s(f, &s->cmos_index);
}
static void pxa2xx_lcdc_save(QEMUFile *f, void *opaque)
{
PXA2xxLCDState *s = (PXA2xxLCDState *) opaque;
int i;
qemu_put_be32(f, s->irqlevel);
qemu_put_be32(f, s->transp);
for (i = 0; i < 6; i ++)
qemu_put_be32s(f, &s->control[i]);
for (i = 0; i < 2; i ++)
qemu_put_be32s(f, &s->status[i]);
for (i = 0; i < 2; i ++)
qemu_put_be32s(f, &s->ovl1c[i]);
for (i = 0; i < 2; i ++)
qemu_put_be32s(f, &s->ovl2c[i]);
qemu_put_be32s(f, &s->ccr);
qemu_put_be32s(f, &s->cmdcr);
qemu_put_be32s(f, &s->trgbr);
qemu_put_be32s(f, &s->tcr);
qemu_put_be32s(f, &s->liidr);
qemu_put_8s(f, &s->bscntr);
for (i = 0; i < 7; i ++) {
qemu_put_betl(f, s->dma_ch[i].branch);
qemu_put_byte(f, s->dma_ch[i].up);
qemu_put_buffer(f, s->dma_ch[i].pbuffer, sizeof(s->dma_ch[i].pbuffer));
qemu_put_betl(f, s->dma_ch[i].descriptor);
qemu_put_betl(f, s->dma_ch[i].source);
qemu_put_be32s(f, &s->dma_ch[i].id);
qemu_put_be32s(f, &s->dma_ch[i].command);
}
}
static void put_tlb(QEMUFile *f, void *pv, size_t size)
{
r4k_tlb_t *v = pv;
uint8_t asid = v->ASID;
uint16_t flags = ((v->EHINV << 15) |
(v->RI1 << 14) |
(v->RI0 << 13) |
(v->XI1 << 12) |
(v->XI0 << 11) |
(v->G << 10) |
(v->C0 << 7) |
(v->C1 << 4) |
(v->V0 << 3) |
(v->V1 << 2) |
(v->D0 << 1) |
(v->D1 << 0));
qemu_put_betls(f, &v->VPN);
qemu_put_be32s(f, &v->PageMask);
qemu_put_8s(f, &asid);
qemu_put_be16s(f, &flags);
qemu_put_be64s(f, &v->PFN[0]);
qemu_put_be64s(f, &v->PFN[1]);
}
static void s3c_rtc_save(QEMUFile *f, void *opaque)
{
struct s3c_rtc_state_s *s = (struct s3c_rtc_state_s *) opaque;
qemu_put_sbe64s(f, &s->next);
qemu_put_8s(f, &s->control);
qemu_put_8s(f, &s->tick);
qemu_put_8s(f, &s->alarm);
qemu_put_8s(f, &s->almsec);
qemu_put_8s(f, &s->almmin);
qemu_put_8s(f, &s->almday);
qemu_put_8s(f, &s->almhour);
qemu_put_8s(f, &s->almmon);
qemu_put_8s(f, &s->almyear);
qemu_put_8s(f, &s->reset);
qemu_put_be32s(f, &s->sec);
}
static void vmmouse_save(QEMUFile *f, void *opaque)
{
VMMouseState *s = (VMMouseState *)opaque;
int i;
qemu_put_be32(f, VMMOUSE_QUEUE_SIZE);
for (i = 0; i < VMMOUSE_QUEUE_SIZE; i++)
qemu_put_be32s(f, &s->queue[i]);
qemu_put_be16s(f, &s->nb_queue);
qemu_put_be16s(f, &s->status);
qemu_put_8s(f, &s->absolute);
}
void generic_usb_save(QEMUFile* f, void *opaque)
{
USBDevice *s = (USBDevice*)opaque;
qemu_put_be32s(f, &s->speed);
qemu_put_8s(f, &s->addr);
qemu_put_be32s(f, &s->state);
qemu_put_buffer(f, s->setup_buf, 8);
qemu_put_buffer(f, s->data_buf, 1024);
qemu_put_be32s(f, &s->remote_wakeup);
qemu_put_be32s(f, &s->setup_state);
qemu_put_be32s(f, &s->setup_len);
qemu_put_be32s(f, &s->setup_index);
}
static void ps2_mouse_save(QEMUFile* f, void* opaque)
{
PS2MouseState *s = (PS2MouseState*)opaque;
ps2_common_save (f, &s->common);
qemu_put_8s(f, &s->mouse_status);
qemu_put_8s(f, &s->mouse_resolution);
qemu_put_8s(f, &s->mouse_sample_rate);
qemu_put_8s(f, &s->mouse_wrap);
qemu_put_8s(f, &s->mouse_type);
qemu_put_8s(f, &s->mouse_detect_state);
qemu_put_be32(f, s->mouse_dx);
qemu_put_be32(f, s->mouse_dy);
qemu_put_be32(f, s->mouse_dz);
qemu_put_8s(f, &s->mouse_buttons);
}
static void rtc_save(QEMUFile *f, void *opaque)
{
RTCState *s = opaque;
qemu_put_buffer(f, s->cmos_data, 128);
qemu_put_8s(f, &s->cmos_index);
qemu_put_be32(f, s->current_tm.tm_sec);
qemu_put_be32(f, s->current_tm.tm_min);
qemu_put_be32(f, s->current_tm.tm_hour);
qemu_put_be32(f, s->current_tm.tm_wday);
qemu_put_be32(f, s->current_tm.tm_mday);
qemu_put_be32(f, s->current_tm.tm_mon);
qemu_put_be32(f, s->current_tm.tm_year);
qemu_put_timer(f, s->periodic_timer);
qemu_put_be64(f, s->next_periodic_time);
qemu_put_be64(f, s->next_second_time);
qemu_put_timer(f, s->second_timer);
qemu_put_timer(f, s->second_timer2);
}
void cpu_save(QEMUFile *f, void *opaque)
{
CPUMIPSState *env = opaque;
int i;
/* Save active TC */
save_tc(f, &env->active_tc);
/* Save active FPU */
save_fpu(f, &env->active_fpu);
/* Save MVP */
qemu_put_sbe32s(f, &env->mvp->CP0_MVPControl);
qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf0);
qemu_put_sbe32s(f, &env->mvp->CP0_MVPConf1);
/* Save TLB */
qemu_put_be32s(f, &env->tlb->nb_tlb);
for(i = 0; i < MIPS_TLB_MAX; i++) {
uint16_t flags = ((env->tlb->mmu.r4k.tlb[i].G << 10) |
(env->tlb->mmu.r4k.tlb[i].C0 << 7) |
(env->tlb->mmu.r4k.tlb[i].C1 << 4) |
(env->tlb->mmu.r4k.tlb[i].V0 << 3) |
(env->tlb->mmu.r4k.tlb[i].V1 << 2) |
(env->tlb->mmu.r4k.tlb[i].D0 << 1) |
(env->tlb->mmu.r4k.tlb[i].D1 << 0));
uint8_t asid;
qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].VPN);
qemu_put_be32s(f, &env->tlb->mmu.r4k.tlb[i].PageMask);
asid = env->tlb->mmu.r4k.tlb[i].ASID;
qemu_put_8s(f, &asid);
qemu_put_be16s(f, &flags);
qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[0]);
qemu_put_betls(f, &env->tlb->mmu.r4k.tlb[i].PFN[1]);
}
/* Save CPU metastate */
qemu_put_be32s(f, &env->current_tc);
qemu_put_be32s(f, &env->current_fpu);
qemu_put_sbe32s(f, &env->error_code);
qemu_put_be32s(f, &env->hflags);
qemu_put_betls(f, &env->btarget);
i = env->bcond;
qemu_put_sbe32s(f, &i);
/* Save remaining CP1 registers */
qemu_put_sbe32s(f, &env->CP0_Index);
qemu_put_sbe32s(f, &env->CP0_Random);
qemu_put_sbe32s(f, &env->CP0_VPEControl);
qemu_put_sbe32s(f, &env->CP0_VPEConf0);
qemu_put_sbe32s(f, &env->CP0_VPEConf1);
qemu_put_betls(f, &env->CP0_YQMask);
qemu_put_betls(f, &env->CP0_VPESchedule);
qemu_put_betls(f, &env->CP0_VPEScheFBack);
qemu_put_sbe32s(f, &env->CP0_VPEOpt);
qemu_put_betls(f, &env->CP0_EntryLo0);
qemu_put_betls(f, &env->CP0_EntryLo1);
qemu_put_betls(f, &env->CP0_Context);
qemu_put_sbe32s(f, &env->CP0_PageMask);
qemu_put_sbe32s(f, &env->CP0_PageGrain);
qemu_put_sbe32s(f, &env->CP0_Wired);
qemu_put_sbe32s(f, &env->CP0_SRSConf0);
qemu_put_sbe32s(f, &env->CP0_SRSConf1);
qemu_put_sbe32s(f, &env->CP0_SRSConf2);
qemu_put_sbe32s(f, &env->CP0_SRSConf3);
qemu_put_sbe32s(f, &env->CP0_SRSConf4);
qemu_put_sbe32s(f, &env->CP0_HWREna);
qemu_put_betls(f, &env->CP0_BadVAddr);
qemu_put_sbe32s(f, &env->CP0_Count);
qemu_put_betls(f, &env->CP0_EntryHi);
qemu_put_sbe32s(f, &env->CP0_Compare);
qemu_put_sbe32s(f, &env->CP0_Status);
qemu_put_sbe32s(f, &env->CP0_IntCtl);
qemu_put_sbe32s(f, &env->CP0_SRSCtl);
qemu_put_sbe32s(f, &env->CP0_SRSMap);
qemu_put_sbe32s(f, &env->CP0_Cause);
qemu_put_betls(f, &env->CP0_EPC);
qemu_put_sbe32s(f, &env->CP0_PRid);
qemu_put_sbe32s(f, &env->CP0_EBase);
qemu_put_sbe32s(f, &env->CP0_Config0);
qemu_put_sbe32s(f, &env->CP0_Config1);
qemu_put_sbe32s(f, &env->CP0_Config2);
qemu_put_sbe32s(f, &env->CP0_Config3);
qemu_put_sbe32s(f, &env->CP0_Config6);
qemu_put_sbe32s(f, &env->CP0_Config7);
qemu_put_betls(f, &env->lladdr);
for(i = 0; i < 8; i++)
qemu_put_betls(f, &env->CP0_WatchLo[i]);
for(i = 0; i < 8; i++)
qemu_put_sbe32s(f, &env->CP0_WatchHi[i]);
qemu_put_betls(f, &env->CP0_XContext);
qemu_put_sbe32s(f, &env->CP0_Framemask);
qemu_put_sbe32s(f, &env->CP0_Debug);
qemu_put_betls(f, &env->CP0_DEPC);
qemu_put_sbe32s(f, &env->CP0_Performance0);
qemu_put_sbe32s(f, &env->CP0_TagLo);
qemu_put_sbe32s(f, &env->CP0_DataLo);
qemu_put_sbe32s(f, &env->CP0_TagHi);
qemu_put_sbe32s(f, &env->CP0_DataHi);
qemu_put_betls(f, &env->CP0_ErrorEPC);
qemu_put_sbe32s(f, &env->CP0_DESAVE);
/* Save inactive TC state */
for (i = 0; i < MIPS_SHADOW_SET_MAX; i++)
save_tc(f, &env->tcs[i]);
for (i = 0; i < MIPS_FPU_MAX; i++)
save_fpu(f, &env->fpus[i]);
}
void cpu_save(QEMUFile *f, void *opaque)
{
CPUState *env = opaque;
uint16_t fptag, fpus, fpuc, fpregs_format;
uint32_t hflags;
int32_t a20_mask;
int i;
for(i = 0; i < CPU_NB_REGS; i++)
qemu_put_betls(f, &env->regs[i]);
qemu_put_betls(f, &env->eip);
qemu_put_betls(f, &env->eflags);
hflags = env->hflags; /* XXX: suppress most of the redundant hflags */
qemu_put_be32s(f, &hflags);
/* FPU */
fpuc = env->fpuc;
fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
fptag = 0;
for(i = 0; i < 8; i++) {
fptag |= ((!env->fptags[i]) << i);
}
qemu_put_be16s(f, &fpuc);
qemu_put_be16s(f, &fpus);
qemu_put_be16s(f, &fptag);
#ifdef USE_X86LDOUBLE
fpregs_format = 0;
#else
fpregs_format = 1;
#endif
qemu_put_be16s(f, &fpregs_format);
for(i = 0; i < 8; i++) {
#ifdef USE_X86LDOUBLE
{
uint64_t mant;
uint16_t exp;
/* we save the real CPU data (in case of MMX usage only 'mant'
contains the MMX register */
cpu_get_fp80(&mant, &exp, env->fpregs[i].d);
qemu_put_be64(f, mant);
qemu_put_be16(f, exp);
}
#else
/* if we use doubles for float emulation, we save the doubles to
avoid losing information in case of MMX usage. It can give
problems if the image is restored on a CPU where long
doubles are used instead. */
qemu_put_be64(f, env->fpregs[i].mmx.MMX_Q(0));
#endif
}
for(i = 0; i < 6; i++)
cpu_put_seg(f, &env->segs[i]);
cpu_put_seg(f, &env->ldt);
cpu_put_seg(f, &env->tr);
cpu_put_seg(f, &env->gdt);
cpu_put_seg(f, &env->idt);
qemu_put_be32s(f, &env->sysenter_cs);
qemu_put_betls(f, &env->sysenter_esp);
qemu_put_betls(f, &env->sysenter_eip);
qemu_put_betls(f, &env->cr[0]);
qemu_put_betls(f, &env->cr[2]);
qemu_put_betls(f, &env->cr[3]);
qemu_put_betls(f, &env->cr[4]);
for(i = 0; i < 8; i++)
qemu_put_betls(f, &env->dr[i]);
/* MMU */
a20_mask = (int32_t) env->a20_mask;
qemu_put_sbe32s(f, &a20_mask);
/* XMM */
qemu_put_be32s(f, &env->mxcsr);
for(i = 0; i < CPU_NB_REGS; i++) {
qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(0));
qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(1));
}
#ifdef TARGET_X86_64
qemu_put_be64s(f, &env->efer);
qemu_put_be64s(f, &env->star);
qemu_put_be64s(f, &env->lstar);
qemu_put_be64s(f, &env->cstar);
qemu_put_be64s(f, &env->fmask);
qemu_put_be64s(f, &env->kernelgsbase);
#endif
qemu_put_be32s(f, &env->smbase);
qemu_put_be64s(f, &env->pat);
qemu_put_be32s(f, &env->hflags2);
qemu_put_be64s(f, &env->vm_hsave);
qemu_put_be64s(f, &env->vm_vmcb);
qemu_put_be64s(f, &env->tsc_offset);
qemu_put_be64s(f, &env->intercept);
qemu_put_be16s(f, &env->intercept_cr_read);
qemu_put_be16s(f, &env->intercept_cr_write);
qemu_put_be16s(f, &env->intercept_dr_read);
qemu_put_be16s(f, &env->intercept_dr_write);
qemu_put_be32s(f, &env->intercept_exceptions);
qemu_put_8s(f, &env->v_tpr);
/* MTRRs */
for(i = 0; i < 11; i++)
qemu_put_be64s(f, &env->mtrr_fixed[i]);
qemu_put_be64s(f, &env->mtrr_deftype);
for(i = 0; i < 8; i++) {
qemu_put_be64s(f, &env->mtrr_var[i].base);
qemu_put_be64s(f, &env->mtrr_var[i].mask);
}
}
void cpu_save(QEMUFile *f, void *opaque)
{
CPUState *env = opaque;
uint16_t fptag, fpus, fpuc, fpregs_format;
uint32_t hflags;
int32_t a20_mask;
int32_t pending_irq;
int i, bit;
if (kvm_enabled()) {
kvm_save_registers(env);
kvm_arch_save_mpstate(env);
}
for(i = 0; i < CPU_NB_REGS; i++)
qemu_put_betls(f, &env->regs[i]);
qemu_put_betls(f, &env->eip);
qemu_put_betls(f, &env->eflags);
hflags = env->hflags; /* XXX: suppress most of the redundant hflags */
qemu_put_be32s(f, &hflags);
/* FPU */
fpuc = env->fpuc;
fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
fptag = 0;
for(i = 0; i < 8; i++) {
fptag |= ((!env->fptags[i]) << i);
}
qemu_put_be16s(f, &fpuc);
qemu_put_be16s(f, &fpus);
qemu_put_be16s(f, &fptag);
#ifdef USE_X86LDOUBLE
fpregs_format = 0;
#else
fpregs_format = 1;
#endif
qemu_put_be16s(f, &fpregs_format);
for(i = 0; i < 8; i++) {
#ifdef USE_X86LDOUBLE
{
uint64_t mant;
uint16_t exp;
/* we save the real CPU data (in case of MMX usage only 'mant'
contains the MMX register */
cpu_get_fp80(&mant, &exp, env->fpregs[i].d);
qemu_put_be64(f, mant);
qemu_put_be16(f, exp);
}
#else
/* if we use doubles for float emulation, we save the doubles to
avoid losing information in case of MMX usage. It can give
problems if the image is restored on a CPU where long
doubles are used instead. */
qemu_put_be64(f, env->fpregs[i].mmx.MMX_Q(0));
#endif
}
for(i = 0; i < 6; i++)
cpu_put_seg(f, &env->segs[i]);
cpu_put_seg(f, &env->ldt);
cpu_put_seg(f, &env->tr);
cpu_put_seg(f, &env->gdt);
cpu_put_seg(f, &env->idt);
qemu_put_be32s(f, &env->sysenter_cs);
qemu_put_betls(f, &env->sysenter_esp);
qemu_put_betls(f, &env->sysenter_eip);
qemu_put_betls(f, &env->cr[0]);
qemu_put_betls(f, &env->cr[2]);
qemu_put_betls(f, &env->cr[3]);
qemu_put_betls(f, &env->cr[4]);
for(i = 0; i < 8; i++)
qemu_put_betls(f, &env->dr[i]);
/* MMU */
a20_mask = (int32_t) env->a20_mask;
qemu_put_sbe32s(f, &a20_mask);
/* XMM */
qemu_put_be32s(f, &env->mxcsr);
for(i = 0; i < CPU_NB_REGS; i++) {
qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(0));
qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(1));
}
#ifdef TARGET_X86_64
qemu_put_be64s(f, &env->efer);
qemu_put_be64s(f, &env->star);
qemu_put_be64s(f, &env->lstar);
qemu_put_be64s(f, &env->cstar);
qemu_put_be64s(f, &env->fmask);
qemu_put_be64s(f, &env->kernelgsbase);
#endif
qemu_put_be32s(f, &env->smbase);
qemu_put_be64s(f, &env->pat);
qemu_put_be32s(f, &env->hflags2);
qemu_put_be64s(f, &env->vm_hsave);
qemu_put_be64s(f, &env->vm_vmcb);
qemu_put_be64s(f, &env->tsc_offset);
qemu_put_be64s(f, &env->intercept);
qemu_put_be16s(f, &env->intercept_cr_read);
qemu_put_be16s(f, &env->intercept_cr_write);
qemu_put_be16s(f, &env->intercept_dr_read);
qemu_put_be16s(f, &env->intercept_dr_write);
qemu_put_be32s(f, &env->intercept_exceptions);
qemu_put_8s(f, &env->v_tpr);
/* MTRRs */
for(i = 0; i < 11; i++)
qemu_put_be64s(f, &env->mtrr_fixed[i]);
qemu_put_be64s(f, &env->mtrr_deftype);
for(i = 0; i < 8; i++) {
qemu_put_be64s(f, &env->mtrr_var[i].base);
qemu_put_be64s(f, &env->mtrr_var[i].mask);
}
/* KVM-related states */
/* There can only be one pending IRQ set in the bitmap at a time, so try
to find it and save its number instead (-1 for none). */
pending_irq = -1;
for (i = 0; i < ARRAY_SIZE(env->interrupt_bitmap); i++) {
if (env->interrupt_bitmap[i]) {
bit = ctz64(env->interrupt_bitmap[i]);
pending_irq = i * 64 + bit;
break;
}
}
qemu_put_sbe32s(f, &pending_irq);
qemu_put_be32s(f, &env->mp_state);
qemu_put_be64s(f, &env->tsc);
/* MCE */
qemu_put_be64s(f, &env->mcg_cap);
if (env->mcg_cap && !kvm_enabled()) {
qemu_put_be64s(f, &env->mcg_status);
qemu_put_be64s(f, &env->mcg_ctl);
for (i = 0; i < (env->mcg_cap & 0xff); i++) {
qemu_put_be64s(f, &env->mce_banks[4*i]);
qemu_put_be64s(f, &env->mce_banks[4*i + 1]);
qemu_put_be64s(f, &env->mce_banks[4*i + 2]);
qemu_put_be64s(f, &env->mce_banks[4*i + 3]);
}
}
}
void cpu_save(QEMUFile *f, void *opaque)
{
CPUState *env = opaque;
uint16_t fptag, fpus, fpuc, fpregs_format;
uint32_t hflags;
int32_t a20_mask;
int i;
cpu_synchronize_state(env, 0);
for(i = 0; i < CPU_NB_REGS; i++)
qemu_put_betls(f, &env->regs[i]);
qemu_put_betls(f, &env->eip);
qemu_put_betls(f, &env->eflags);
hflags = env->hflags;
qemu_put_be32s(f, &hflags);
fpuc = env->fpuc;
fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
fptag = 0;
for(i = 0; i < 8; i++) {
fptag |= ((!env->fptags[i]) << i);
}
qemu_put_be16s(f, &fpuc);
qemu_put_be16s(f, &fpus);
qemu_put_be16s(f, &fptag);
#ifdef USE_X86LDOUBLE
fpregs_format = 0;
#else
fpregs_format = 1;
#endif
qemu_put_be16s(f, &fpregs_format);
for(i = 0; i < 8; i++) {
#ifdef USE_X86LDOUBLE
{
uint64_t mant;
uint16_t exp;
cpu_get_fp80(&mant, &exp, env->fpregs[i].d);
qemu_put_be64(f, mant);
qemu_put_be16(f, exp);
}
#else
qemu_put_be64(f, env->fpregs[i].mmx.MMX_Q(0));
#endif
}
for(i = 0; i < 6; i++)
cpu_put_seg(f, &env->segs[i]);
cpu_put_seg(f, &env->ldt);
cpu_put_seg(f, &env->tr);
cpu_put_seg(f, &env->gdt);
cpu_put_seg(f, &env->idt);
qemu_put_be32s(f, &env->sysenter_cs);
qemu_put_betls(f, &env->sysenter_esp);
qemu_put_betls(f, &env->sysenter_eip);
qemu_put_betls(f, &env->cr[0]);
qemu_put_betls(f, &env->cr[2]);
qemu_put_betls(f, &env->cr[3]);
qemu_put_betls(f, &env->cr[4]);
for(i = 0; i < 8; i++)
qemu_put_betls(f, &env->dr[i]);
a20_mask = (int32_t) env->a20_mask;
qemu_put_sbe32s(f, &a20_mask);
qemu_put_be32s(f, &env->mxcsr);
for(i = 0; i < CPU_NB_REGS; i++) {
qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(0));
qemu_put_be64s(f, &env->xmm_regs[i].XMM_Q(1));
}
#ifdef TARGET_X86_64
qemu_put_be64s(f, &env->efer);
qemu_put_be64s(f, &env->star);
qemu_put_be64s(f, &env->lstar);
qemu_put_be64s(f, &env->cstar);
qemu_put_be64s(f, &env->fmask);
qemu_put_be64s(f, &env->kernelgsbase);
#endif
qemu_put_be32s(f, &env->smbase);
qemu_put_be64s(f, &env->pat);
qemu_put_be32s(f, &env->hflags2);
qemu_put_be64s(f, &env->vm_hsave);
qemu_put_be64s(f, &env->vm_vmcb);
qemu_put_be64s(f, &env->tsc_offset);
qemu_put_be64s(f, &env->intercept);
qemu_put_be16s(f, &env->intercept_cr_read);
qemu_put_be16s(f, &env->intercept_cr_write);
qemu_put_be16s(f, &env->intercept_dr_read);
qemu_put_be16s(f, &env->intercept_dr_write);
qemu_put_be32s(f, &env->intercept_exceptions);
qemu_put_8s(f, &env->v_tpr);
for(i = 0; i < 11; i++)
qemu_put_be64s(f, &env->mtrr_fixed[i]);
qemu_put_be64s(f, &env->mtrr_deftype);
for(i = 0; i < 8; i++) {
qemu_put_be64s(f, &env->mtrr_var[i].base);
qemu_put_be64s(f, &env->mtrr_var[i].mask);
}
for (i = 0; i < sizeof(env->interrupt_bitmap)/8; i++) {
qemu_put_be64s(f, &env->interrupt_bitmap[i]);
}
qemu_put_be64s(f, &env->tsc);
qemu_put_be32s(f, &env->mp_state);
qemu_put_be64s(f, &env->mcg_cap);
if (env->mcg_cap) {
qemu_put_be64s(f, &env->mcg_status);
qemu_put_be64s(f, &env->mcg_ctl);
for (i = 0; i < (env->mcg_cap & 0xff); i++) {
qemu_put_be64s(f, &env->mce_banks[4*i]);
qemu_put_be64s(f, &env->mce_banks[4*i + 1]);
qemu_put_be64s(f, &env->mce_banks[4*i + 2]);
qemu_put_be64s(f, &env->mce_banks[4*i + 3]);
}
}
}
static void put_uint8(QEMUFile *f, void *pv, size_t size)
{
uint8_t *v = pv;
qemu_put_8s(f, v);
}
