static void cpu_devinit(const char *cpu_model, unsigned int id, uint64_t prom_addr, qemu_irq **cpu_irqs) { CPUState *cs; SPARCCPU *cpu; CPUSPARCState *env; cpu = cpu_sparc_init(cpu_model); if (cpu == NULL) { fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n"); exit(1); } env = &cpu->env; cpu_sparc_set_id(env, id); if (id == 0) { qemu_register_reset(main_cpu_reset, cpu); } else { qemu_register_reset(secondary_cpu_reset, cpu); cs = CPU(cpu); cs->halted = 1; } *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); env->prom_addr = prom_addr; }
void *sbi_init(target_phys_addr_t addr, qemu_irq **irq, qemu_irq **cpu_irq, qemu_irq **parent_irq) { unsigned int i; int sbi_io_memory; SBIState *s; s = qemu_mallocz(sizeof(SBIState)); if (!s) return NULL; for (i = 0; i < MAX_CPUS; i++) { s->cpu_irqs[i] = parent_irq[i]; } sbi_io_memory = cpu_register_io_memory(0, sbi_mem_read, sbi_mem_write, s); cpu_register_physical_memory(addr, SBI_SIZE, sbi_io_memory); register_savevm("sbi", addr, 1, sbi_save, sbi_load, s); qemu_register_reset(sbi_reset, s); *irq = qemu_allocate_irqs(sbi_set_irq, s, 32); *cpu_irq = qemu_allocate_irqs(sbi_set_timer_irq_cpu, s, MAX_CPUS); sbi_reset(s); return s; }
void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq, int disabled) { int slavio_serial_io_memory, i; SerialState *s; s = qemu_mallocz(sizeof(SerialState)); if (!s) return; for (i = 0; i < 2; i++) { s->chn[i].irq = irq; s->chn[i].chn = 1 - i; s->chn[i].chr = NULL; } s->chn[0].otherchn = &s->chn[1]; s->chn[1].otherchn = &s->chn[0]; s->chn[0].type = mouse; s->chn[1].type = kbd; s->chn[0].disabled = disabled; s->chn[1].disabled = disabled; slavio_serial_io_memory = cpu_register_io_memory(0, slavio_serial_mem_read, slavio_serial_mem_write, s); cpu_register_physical_memory(base, SERIAL_SIZE, slavio_serial_io_memory); qemu_add_mouse_event_handler(sunmouse_event, &s->chn[0], 0, "QEMU Sun Mouse"); qemu_add_kbd_event_handler(sunkbd_event, &s->chn[1]); register_savevm("slavio_serial_mouse", base, 2, slavio_serial_save, slavio_serial_load, s); qemu_register_reset(slavio_serial_reset, s); slavio_serial_reset(s); }
void *esp_init(target_phys_addr_t espaddr, int it_shift, espdma_memory_read_write dma_memory_read, espdma_memory_read_write dma_memory_write, void *dma_opaque, qemu_irq irq, qemu_irq *reset) { ESPState *s; int esp_io_memory; s = qemu_mallocz(sizeof(ESPState)); if (!s) return NULL; s->irq = irq; s->it_shift = it_shift; s->dma_memory_read = dma_memory_read; s->dma_memory_write = dma_memory_write; s->dma_opaque = dma_opaque; esp_io_memory = cpu_register_io_memory(0, esp_mem_read, esp_mem_write, s); cpu_register_physical_memory(espaddr, ESP_REGS << it_shift, esp_io_memory); esp_reset(s); register_savevm("esp", espaddr, 3, esp_save, esp_load, s); qemu_register_reset(esp_reset, s); *reset = *qemu_allocate_irqs(parent_esp_reset, s, 1); return s; }
SerialState *slavio_serial_init(int base, int irq, CharDriverState *chr1, CharDriverState *chr2) { int slavio_serial_io_memory, i; SerialState *s; s = qemu_mallocz(sizeof(SerialState)); if (!s) return NULL; slavio_serial_io_memory = cpu_register_io_memory(0, slavio_serial_mem_read, slavio_serial_mem_write, s); cpu_register_physical_memory(base, SERIAL_MAXADDR, slavio_serial_io_memory); s->chn[0].chr = chr1; s->chn[1].chr = chr2; for (i = 0; i < 2; i++) { s->chn[i].irq = irq; s->chn[i].chn = 1 - i; s->chn[i].type = ser; if (s->chn[i].chr) { qemu_chr_add_handlers(s->chn[i].chr, serial_can_receive, serial_receive1, serial_event, &s->chn[i]); } } s->chn[0].otherchn = &s->chn[1]; s->chn[1].otherchn = &s->chn[0]; register_savevm("slavio_serial", base, 2, slavio_serial_save, slavio_serial_load, s); qemu_register_reset(slavio_serial_reset, s); slavio_serial_reset(s); return s; }
void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift, qemu_irq irq, void* mem_opaque, void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write)) { dp8393xState *s; qemu_check_nic_model(nd, "dp83932"); s = qemu_mallocz(sizeof(dp8393xState)); s->mem_opaque = mem_opaque; s->memory_rw = memory_rw; s->it_shift = it_shift; s->irq = irq; s->watchdog = qemu_new_timer(vm_clock, dp8393x_watchdog, s); s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */ s->conf.macaddr = nd->macaddr; s->conf.vlan = nd->vlan; s->conf.peer = nd->netdev; s->nic = qemu_new_nic(&net_dp83932_info, &s->conf, nd->model, nd->name, s); qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a); qemu_register_reset(nic_reset, s); nic_reset(s); s->mmio_index = cpu_register_io_memory(dp8393x_read, dp8393x_write, s); cpu_register_physical_memory(base, 0x40 << it_shift, s->mmio_index); }
int kvm_init_vcpu(CPUArchState *env) { KVMState *s = kvm_state; long mmap_size; int ret; DPRINTF("kvm_init_vcpu\n"); #ifdef CONFIG_SOLARIS ret = kvm_vm_clone(kvm_state); if (ret < 0) { fprintf(stderr, "kvm_init_vcpu could not clone fd: %m\n"); goto err; } env->kvm_fd = ret; ret = ioctl(env->kvm_fd, KVM_CREATE_VCPU, env->cpu_index); #else ret = kvm_vm_ioctl(s, KVM_CREATE_VCPU, env->cpu_index); #endif if (ret < 0) { DPRINTF("kvm_create_vcpu failed\n"); goto err; } #ifndef CONFIG_SOLARIS env->kvm_fd = ret; #endif env->kvm_state = s; env->kvm_vcpu_dirty = 1; mmap_size = kvm_ioctl(s, KVM_GET_VCPU_MMAP_SIZE, 0); if (mmap_size < 0) { ret = mmap_size; DPRINTF("KVM_GET_VCPU_MMAP_SIZE failed\n"); goto err; } env->kvm_run = mmap(NULL, mmap_size, PROT_READ | PROT_WRITE, MAP_SHARED, env->kvm_fd, 0); if (env->kvm_run == MAP_FAILED) { ret = -errno; DPRINTF("mmap'ing vcpu state failed\n"); goto err; } if (s->coalesced_mmio && !s->coalesced_mmio_ring) { s->coalesced_mmio_ring = (void *)env->kvm_run + s->coalesced_mmio * PAGE_SIZE; } ret = kvm_arch_init_vcpu(env); if (ret == 0) { qemu_register_reset(kvm_reset_vcpu, env); kvm_arch_reset_vcpu(env); } err: return ret; }
/* via ide func */ static int vt82c686b_ide_initfn(PCIDevice *dev) { PCIIDEState *d = DO_UPCAST(PCIIDEState, dev, dev);; uint8_t *pci_conf = d->dev.config; pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_VIA); pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_VIA_IDE); pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE); pci_config_set_prog_interface(pci_conf, 0x8a); /* legacy ATA mode */ pci_config_set_revision(pci_conf,0x06); /* Revision 0.6 */ pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); qemu_register_reset(via_reset, d); pci_register_bar((PCIDevice *)d, 4, 0x10, PCI_BASE_ADDRESS_SPACE_IO, bmdma_map); vmstate_register(&dev->qdev, 0, &vmstate_ide_pci, d); ide_bus_new(&d->bus[0], &d->dev.qdev); ide_bus_new(&d->bus[1], &d->dev.qdev); ide_init2(&d->bus[0], isa_reserve_irq(14)); ide_init2(&d->bus[1], isa_reserve_irq(15)); ide_init_ioport(&d->bus[0], 0x1f0, 0x3f6); ide_init_ioport(&d->bus[1], 0x170, 0x376); return 0; }
void dp83932_init(NICInfo *nd, hwaddr base, int it_shift, MemoryRegion *address_space, qemu_irq irq, void* mem_opaque, void (*memory_rw)(void *opaque, hwaddr addr, uint8_t *buf, int len, int is_write)) { dp8393xState *s; qemu_check_nic_model(nd, "dp83932"); s = g_malloc0(sizeof(dp8393xState)); s->address_space = address_space; s->mem_opaque = mem_opaque; s->memory_rw = memory_rw; s->it_shift = it_shift; s->irq = irq; s->watchdog = timer_new_ns(QEMU_CLOCK_VIRTUAL, dp8393x_watchdog, s); s->regs[SONIC_SR] = 0x0004; /* only revision recognized by Linux */ s->conf.macaddr = nd->macaddr; s->conf.peers.ncs[0] = nd->netdev; s->nic = qemu_new_nic(&net_dp83932_info, &s->conf, nd->model, nd->name, s); qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); qemu_register_reset(nic_reset, s); nic_reset(s); memory_region_init_io(&s->mmio, NULL, &dp8393x_ops, s, "dp8393x", 0x40 << it_shift); memory_region_add_subregion(address_space, base, &s->mmio); }
static int rtc_initfn(ISADevice *dev) { RTCState *s = DO_UPCAST(RTCState, dev, dev); int base = 0x70; s->cmos_data[RTC_REG_A] = 0x26; s->cmos_data[RTC_REG_B] = 0x02; s->cmos_data[RTC_REG_C] = 0x00; s->cmos_data[RTC_REG_D] = 0x80; rtc_set_date_from_host(dev); s->periodic_timer = qemu_new_timer_ns(rtc_clock, rtc_periodic_timer, s); #ifdef TARGET_I386 if (rtc_td_hack) s->coalesced_timer = qemu_new_timer_ns(rtc_clock, rtc_coalesced_timer, s); #endif s->second_timer = qemu_new_timer_ns(rtc_clock, rtc_update_second, s); s->second_timer2 = qemu_new_timer_ns(rtc_clock, rtc_update_second2, s); s->next_second_time = qemu_get_clock_ns(rtc_clock) + (get_ticks_per_sec() * 99) / 100; qemu_mod_timer(s->second_timer2, s->next_second_time); register_ioport_write(base, 2, 1, cmos_ioport_write, s); register_ioport_read(base, 2, 1, cmos_ioport_read, s); isa_init_ioport_range(dev, base, 2); qdev_set_legacy_instance_id(&dev->qdev, base, 2); qemu_register_reset(rtc_reset, s); return 0; }
static CPUSPARCState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef) { CPUSPARCState *env; ResetData *reset_info; uint32_t tick_frequency = 100*1000000; uint32_t stick_frequency = 100*1000000; uint32_t hstick_frequency = 100*1000000; if (!cpu_model) cpu_model = hwdef->default_cpu_model; env = cpu_init(cpu_model); if (!env) { fprintf(stderr, "Unable to find Sparc CPU definition\n"); exit(1); } env->tick = cpu_timer_create("tick", env, tick_irq, tick_frequency, TICK_NPT_MASK); env->stick = cpu_timer_create("stick", env, stick_irq, stick_frequency, TICK_INT_DIS); env->hstick = cpu_timer_create("hstick", env, hstick_irq, hstick_frequency, TICK_INT_DIS); reset_info = g_malloc0(sizeof(ResetData)); reset_info->env = env; reset_info->prom_addr = hwdef->prom_addr; qemu_register_reset(main_cpu_reset, reset_info); return env; }
void slavio_serial_ms_kbd_init(int base, int irq) { int slavio_serial_io_memory, i; SerialState *s; s = qemu_mallocz(sizeof(SerialState)); if (!s) return; for (i = 0; i < 2; i++) { s->chn[i].irq = irq; s->chn[i].chn = 1 - i; s->chn[i].chr = NULL; } s->chn[0].otherchn = &s->chn[1]; s->chn[1].otherchn = &s->chn[0]; s->chn[0].type = mouse; s->chn[1].type = kbd; slavio_serial_io_memory = cpu_register_io_memory(0, slavio_serial_mem_read, slavio_serial_mem_write, s); cpu_register_physical_memory(base, SERIAL_MAXADDR, slavio_serial_io_memory); qemu_add_mouse_event_handler(sunmouse_event, &s->chn[0], 0, "QEMU Sun Mouse"); qemu_add_kbd_event_handler(sunkbd_event, &s->chn[1]); qemu_register_reset(slavio_serial_reset, s); slavio_serial_reset(s); }
/* Generic PowerPC 4xx processor instanciation */ CPUState *ppc4xx_init (const unsigned char *cpu_model, clk_setup_t *cpu_clk, clk_setup_t *tb_clk, uint32_t sysclk) { CPUState *env; /* init CPUs */ env = cpu_init(cpu_model); if (!env) { fprintf(stderr, "Unable to find PowerPC %s CPU definition\n", cpu_model); exit(1); } cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */ cpu_clk->opaque = env; /* Set time-base frequency to sysclk */ tb_clk->cb = ppc_emb_timers_init(env, sysclk); tb_clk->opaque = env; ppc_dcr_init(env, NULL, NULL); /* Register qemu callbacks */ qemu_register_reset(&cpu_ppc_reset, env); register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); return env; }
static void s390_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); S390CPU *cpu = S390_CPU(obj); CPUS390XState *env = &cpu->env; static bool inited; static int cpu_num = 0; #if !defined(CONFIG_USER_ONLY) struct tm tm; #endif cs->env_ptr = env; cpu_exec_init(env); #if !defined(CONFIG_USER_ONLY) qemu_register_reset(s390_cpu_machine_reset_cb, cpu); qemu_get_timedate(&tm, 0); env->tod_offset = TOD_UNIX_EPOCH + (time2tod(mktimegm(&tm)) * 1000000000ULL); env->tod_basetime = 0; env->tod_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_tod_timer, cpu); env->cpu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_cpu_timer, cpu); s390_cpu_set_state(CPU_STATE_STOPPED, cpu); #endif env->cpu_num = cpu_num++; if (tcg_enabled() && !inited) { inited = true; s390x_translate_init(); } }
void cris_load_image(CRISCPU *cpu, struct cris_load_info *li) { CPUCRISState *env = &cpu->env; uint64_t entry, high; int kcmdline_len; int image_size; env->load_info = li; /* Boots a kernel elf binary, os/linux-2.6/vmlinux from the axis devboard SDK. */ image_size = load_elf(li->image_filename, translate_kernel_address, NULL, &entry, NULL, &high, 0, ELF_MACHINE, 0); li->entry = entry; if (image_size < 0) { /* Takes a kimage from the axis devboard SDK. */ image_size = load_image_targphys(li->image_filename, 0x40004000, ram_size); li->entry = 0x40004000; } if (image_size < 0) { fprintf(stderr, "qemu: could not load kernel '%s'\n", li->image_filename); exit(1); } if (li->cmdline && (kcmdline_len = strlen(li->cmdline))) { if (kcmdline_len > 256) { fprintf(stderr, "Too long CRIS kernel cmdline (max 256)\n"); exit(1); } pstrcpy_targphys("cmdline", 0x40000000, 256, li->cmdline); } qemu_register_reset(main_cpu_reset, cpu); }
void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm, qemu_irq sci_irq) { memory_region_init(&pm->io, OBJECT(lpc_pci), "ich9-pm", ICH9_PMIO_SIZE); memory_region_set_enabled(&pm->io, false); memory_region_add_subregion(pci_address_space_io(lpc_pci), 0, &pm->io); acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io); acpi_pm1_evt_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io); acpi_pm1_cnt_init(&pm->acpi_regs, &pm->io, pm->disable_s3, pm->disable_s4, pm->s4_val); acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN); memory_region_init_io(&pm->io_gpe, OBJECT(lpc_pci), &ich9_gpe_ops, pm, "acpi-gpe0", ICH9_PMIO_GPE0_LEN); memory_region_add_subregion(&pm->io, ICH9_PMIO_GPE0_STS, &pm->io_gpe); memory_region_init_io(&pm->io_smi, OBJECT(lpc_pci), &ich9_smi_ops, pm, "acpi-smi", 8); memory_region_add_subregion(&pm->io, ICH9_PMIO_SMI_EN, &pm->io_smi); pm->irq = sci_irq; qemu_register_reset(pm_reset, pm); pm->powerdown_notifier.notify = pm_powerdown_req; qemu_register_powerdown_notifier(&pm->powerdown_notifier); acpi_cpu_hotplug_init(pci_address_space_io(lpc_pci), OBJECT(lpc_pci), &pm->gpe_cpu, ICH9_CPU_HOTPLUG_IO_BASE); if (pm->acpi_memory_hotplug.is_enabled) { acpi_memory_hotplug_init(pci_address_space_io(lpc_pci), OBJECT(lpc_pci), &pm->acpi_memory_hotplug); } }
/* If fd is zero, it means that the parallel device uses the console */ ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr) { ParallelState *s; uint8_t dummy; s = qemu_mallocz(sizeof(ParallelState)); s->irq = irq; s->chr = chr; parallel_reset(s); qemu_register_reset(parallel_reset, s); if (qemu_chr_ioctl(chr, CHR_IOCTL_PP_READ_STATUS, &dummy) == 0) { s->hw_driver = 1; s->status = dummy; } if (s->hw_driver) { register_ioport_write(base, 8, 1, parallel_ioport_write_hw, s); register_ioport_read(base, 8, 1, parallel_ioport_read_hw, s); register_ioport_write(base+4, 1, 2, parallel_ioport_eppdata_write_hw2, s); register_ioport_read(base+4, 1, 2, parallel_ioport_eppdata_read_hw2, s); register_ioport_write(base+4, 1, 4, parallel_ioport_eppdata_write_hw4, s); register_ioport_read(base+4, 1, 4, parallel_ioport_eppdata_read_hw4, s); register_ioport_write(base+0x400, 8, 1, parallel_ioport_ecp_write, s); register_ioport_read(base+0x400, 8, 1, parallel_ioport_ecp_read, s); } else { register_ioport_write(base, 8, 1, parallel_ioport_write_sw, s); register_ioport_read(base, 8, 1, parallel_ioport_read_sw, s); } return s; }
SPARCCPU *sparc64_cpu_devinit(const char *cpu_type, uint64_t prom_addr) { SPARCCPU *cpu; CPUSPARCState *env; ResetData *reset_info; uint32_t tick_frequency = 100 * 1000000; uint32_t stick_frequency = 100 * 1000000; uint32_t hstick_frequency = 100 * 1000000; cpu = SPARC_CPU(cpu_create(cpu_type)); qdev_init_gpio_in_named(DEVICE(cpu), sparc64_cpu_set_ivec_irq, "ivec-irq", IVEC_MAX); env = &cpu->env; env->tick = cpu_timer_create("tick", cpu, tick_irq, tick_frequency, TICK_INT_DIS, TICK_NPT_MASK); env->stick = cpu_timer_create("stick", cpu, stick_irq, stick_frequency, TICK_INT_DIS, TICK_NPT_MASK); env->hstick = cpu_timer_create("hstick", cpu, hstick_irq, hstick_frequency, TICK_INT_DIS, TICK_NPT_MASK); reset_info = g_malloc0(sizeof(ResetData)); reset_info->cpu = cpu; reset_info->prom_addr = prom_addr; qemu_register_reset(main_cpu_reset, reset_info); return cpu; }
static void s390_cpu_initfn(Object *obj) { CPUState *cs = CPU(obj); S390CPU *cpu = S390_CPU(obj); CPUS390XState *env = &cpu->env; static bool inited; static int cpu_num = 0; #if !defined(CONFIG_USER_ONLY) struct tm tm; #endif cs->env_ptr = env; cpu_exec_init(env); #if !defined(CONFIG_USER_ONLY) qemu_register_reset(s390_cpu_machine_reset_cb, cpu); qemu_get_timedate(&tm, 0); env->tod_offset = TOD_UNIX_EPOCH + (time2tod(mktimegm(&tm)) * 1000000000ULL); env->tod_basetime = 0; env->tod_timer = qemu_new_timer_ns(vm_clock, s390x_tod_timer, cpu); env->cpu_timer = qemu_new_timer_ns(vm_clock, s390x_cpu_timer, cpu); /* set CPUState::halted state to 1 to avoid decrementing the running * cpu counter in s390_cpu_reset to a negative number at * initial ipl */ cs->halted = 1; #endif env->cpu_num = cpu_num++; env->ext_index = -1; if (tcg_enabled() && !inited) { inited = true; s390x_translate_init(); } }
/* XXX Interrupt acknowledge cycles not supported. */ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4], target_phys_addr_t config_space, target_phys_addr_t int_ack, target_phys_addr_t special_cycle, target_phys_addr_t registers) { PPC4xxPCIState *controller; int index; static int ppc4xx_pci_id; uint8_t *pci_conf; controller = qemu_mallocz(sizeof(PPC4xxPCIState)); controller->pci_state.bus = pci_register_bus(ppc4xx_pci_set_irq, ppc4xx_pci_map_irq, pci_irqs, 0, 4); controller->pci_dev = pci_register_device(controller->pci_state.bus, "host bridge", sizeof(PCIDevice), 0, NULL, NULL); pci_conf = controller->pci_dev->config; pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM); pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_IBM_440GX); pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER); /* CFGADDR */ index = cpu_register_io_memory(0, pci4xx_cfgaddr_read, pci4xx_cfgaddr_write, controller); if (index < 0) goto free; cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index); /* CFGDATA */ index = cpu_register_io_memory(0, pci4xx_cfgdata_read, pci4xx_cfgdata_write, &controller->pci_state); if (index < 0) goto free; cpu_register_physical_memory(config_space + PCIC0_CFGDATA, 4, index); /* Internal registers */ index = cpu_register_io_memory(0, pci_reg_read, pci_reg_write, controller); if (index < 0) goto free; cpu_register_physical_memory(registers, PCI_REG_SIZE, index); qemu_register_reset(ppc4xx_pci_reset, controller); /* XXX load/save code not tested. */ register_savevm("ppc4xx_pci", ppc4xx_pci_id++, 1, ppc4xx_pci_save, ppc4xx_pci_load, controller); return controller->pci_state.bus; free: printf("%s error\n", __func__); qemu_free(controller); return NULL; }
static void rtc_realizefn(DeviceState *dev, Error **errp) { ISADevice *isadev = ISA_DEVICE(dev); RTCState *s = MC146818_RTC(dev); int base = 0x70; s->cmos_data[RTC_REG_A] = 0x26; s->cmos_data[RTC_REG_B] = 0x02; s->cmos_data[RTC_REG_C] = 0x00; s->cmos_data[RTC_REG_D] = 0x80; /* This is for historical reasons. The default base year qdev property * was set to 2000 for most machine types before the century byte was * implemented. * * This if statement means that the century byte will be always 0 * (at least until 2079...) for base_year = 1980, but will be set * correctly for base_year = 2000. */ if (s->base_year == 2000) { s->base_year = 0; } rtc_set_date_from_host(isadev); #ifdef TARGET_I386 switch (s->lost_tick_policy) { case LOST_TICK_POLICY_SLEW: s->coalesced_timer = timer_new_ns(rtc_clock, rtc_coalesced_timer, s); break; case LOST_TICK_POLICY_DISCARD: break; default: error_setg(errp, "Invalid lost tick policy."); return; } #endif s->periodic_timer = timer_new_ns(rtc_clock, rtc_periodic_timer, s); s->update_timer = timer_new_ns(rtc_clock, rtc_update_timer, s); check_update_timer(s); s->clock_reset_notifier.notify = rtc_notify_clock_reset; qemu_clock_register_reset_notifier(rtc_clock, &s->clock_reset_notifier); s->suspend_notifier.notify = rtc_notify_suspend; qemu_register_suspend_notifier(&s->suspend_notifier); memory_region_init_io(&s->io, OBJECT(s), &cmos_ops, s, "rtc", 2); isa_register_ioport(isadev, &s->io, base); qdev_set_legacy_instance_id(dev, base, 3); qemu_register_reset(rtc_reset, s); object_property_add(OBJECT(s), "date", "struct tm", rtc_get_date, NULL, NULL, s, NULL); }
static void wdt_diag288_realize(DeviceState *dev, Error **errp) { DIAG288State *diag288 = DIAG288(dev); qemu_register_reset(diag288_reset, diag288); diag288->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, diag288_timer_expired, dev); }
static void icp_realize(DeviceState *dev, Error **errp) { ICPState *icp = ICP(dev); PowerPCCPU *cpu; CPUPPCState *env; Object *obj; Error *err = NULL; obj = object_property_get_link(OBJECT(dev), ICP_PROP_XICS, &err); if (!obj) { error_propagate_prepend(errp, err, "required link '" ICP_PROP_XICS "' not found: "); return; } icp->xics = XICS_FABRIC(obj); obj = object_property_get_link(OBJECT(dev), ICP_PROP_CPU, &err); if (!obj) { error_propagate_prepend(errp, err, "required link '" ICP_PROP_CPU "' not found: "); return; } cpu = POWERPC_CPU(obj); icp->cs = CPU(obj); env = &cpu->env; switch (PPC_INPUT(env)) { case PPC_FLAGS_INPUT_POWER7: icp->output = env->irq_inputs[POWER7_INPUT_INT]; break; case PPC_FLAGS_INPUT_POWER9: /* For SPAPR xics emulation */ icp->output = env->irq_inputs[POWER9_INPUT_INT]; break; case PPC_FLAGS_INPUT_970: icp->output = env->irq_inputs[PPC970_INPUT_INT]; break; default: error_setg(errp, "XICS interrupt controller does not support this CPU bus model"); return; } if (kvm_irqchip_in_kernel()) { icp_kvm_realize(dev, &err); if (err) { error_propagate(errp, err); return; } } qemu_register_reset(icp_reset_handler, dev); vmstate_register(NULL, icp->cs->cpu_index, &vmstate_icp_server, icp); }
static int piix4_initfn(PCIDevice *dev) { PIIX4State *d = DO_UPCAST(PIIX4State, dev, dev); isa_bus_new(&d->dev.qdev, pci_address_space_io(dev)); piix4_dev = &d->dev; qemu_register_reset(piix4_reset, d); return 0; }
void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg) { PS2MouseState *s = (PS2MouseState *)qemu_mallocz(sizeof(PS2MouseState)); s->common.update_irq = update_irq; s->common.update_arg = update_arg; vmstate_register(NULL, 0, &vmstate_ps2_mouse, s); qemu_add_mouse_event_handler(ps2_mouse_event, s, 0, "QEMU PS/2 Mouse"); qemu_register_reset(ps2_mouse_reset, s); return s; }
static void piix4_realize(PCIDevice *dev, Error **errp) { PIIX4State *d = PIIX4_PCI_DEVICE(dev); if (!isa_bus_new(DEVICE(d), pci_address_space(dev), pci_address_space_io(dev), errp)) { return; } piix4_dev = &d->dev; qemu_register_reset(piix4_reset, d); }
static Lx60FpgaState *lx60_fpga_init(MemoryRegion *address_space, target_phys_addr_t base) { Lx60FpgaState *s = g_malloc(sizeof(Lx60FpgaState)); memory_region_init_io(&s->iomem, &lx60_fpga_ops, s, "lx60.fpga", 0x10000); memory_region_add_subregion(address_space, base, &s->iomem); lx60_fpga_reset(s); qemu_register_reset(lx60_fpga_reset, s); return s; }
static void serial_init_core(SerialState *s) { if (!s->chr) { fprintf(stderr, "Can't create radio device, empty char device\n"); exit(1); } qemu_register_reset(radio_reset, s); qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1, serial_event, s); }
void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg) { PS2MouseState *s = (PS2MouseState *)qemu_mallocz(sizeof(PS2MouseState)); s->common.update_irq = update_irq; s->common.update_arg = update_arg; ps2_reset(&s->common); register_savevm("ps2mouse", 0, 2, ps2_mouse_save, ps2_mouse_load, s); qemu_add_mouse_event_handler(ps2_mouse_event, s, 0, "QEMU PS/2 Mouse"); qemu_register_reset(ps2_reset, &s->common); return s; }
static void xtensa_sim_init(MachineState *machine) { XtensaCPU *cpu = NULL; CPUXtensaState *env = NULL; MemoryRegion *ram, *rom; ram_addr_t ram_size = machine->ram_size; const char *cpu_model = machine->cpu_model; const char *kernel_filename = machine->kernel_filename; int n; if (!cpu_model) { cpu_model = XTENSA_DEFAULT_CPU_MODEL; } for (n = 0; n < smp_cpus; n++) { cpu = cpu_xtensa_init(cpu_model); if (cpu == NULL) { error_report("unable to find CPU definition '%s'", cpu_model); exit(EXIT_FAILURE); } env = &cpu->env; env->sregs[PRID] = n; qemu_register_reset(sim_reset, cpu); /* Need MMU initialized prior to ELF loading, * so that ELF gets loaded into virtual addresses */ sim_reset(cpu); } ram = g_malloc(sizeof(*ram)); memory_region_init_ram(ram, NULL, "xtensa.sram", ram_size, &error_fatal); vmstate_register_ram_global(ram); memory_region_add_subregion(get_system_memory(), 0, ram); rom = g_malloc(sizeof(*rom)); memory_region_init_ram(rom, NULL, "xtensa.rom", 0x1000, &error_fatal); vmstate_register_ram_global(rom); memory_region_add_subregion(get_system_memory(), 0xfe000000, rom); if (kernel_filename) { uint64_t elf_entry; uint64_t elf_lowaddr; #ifdef TARGET_WORDS_BIGENDIAN int success = load_elf(kernel_filename, translate_phys_addr, cpu, &elf_entry, &elf_lowaddr, NULL, 1, ELF_MACHINE, 0); #else int success = load_elf(kernel_filename, translate_phys_addr, cpu, &elf_entry, &elf_lowaddr, NULL, 0, ELF_MACHINE, 0); #endif if (success > 0) { env->pc = elf_entry; } } }