static void __init cps_prepare_cpus(unsigned int max_cpus) { unsigned ncores, core_vpes, c, cca; bool cca_unsuitable; u32 *entry_code; mips_mt_set_cpuoptions(); /* Detect whether the CCA is unsuited to multi-core SMP */ cca = read_c0_config() & CONF_CM_CMASK; switch (cca) { case 0x4: /* CWBE */ case 0x5: /* CWB */ /* The CCA is coherent, multi-core is fine */ cca_unsuitable = false; break; default: /* CCA is not coherent, multi-core is not usable */ cca_unsuitable = true; } /* Warn the user if the CCA prevents multi-core */ ncores = mips_cm_numcores(); if (cca_unsuitable && ncores > 1) { pr_warn("Using only one core due to unsuitable CCA 0x%x\n", cca); for_each_present_cpu(c) { if (cpu_data[c].core) set_cpu_present(c, false); } }
void __init tlb_init(void) { unsigned int config = read_c0_config(); unsigned long status; probe_tlb(config); status = read_c0_status(); status &= ~(ST0_UPS | ST0_KPS); #ifdef CONFIG_PAGE_SIZE_4KB status |= (TFP_PAGESIZE_4K << 32) | (TFP_PAGESIZE_4K << 36); #elif defined(CONFIG_PAGE_SIZE_8KB) status |= (TFP_PAGESIZE_8K << 32) | (TFP_PAGESIZE_8K << 36); #elif defined(CONFIG_PAGE_SIZE_16KB) status |= (TFP_PAGESIZE_16K << 32) | (TFP_PAGESIZE_16K << 36); #elif defined(CONFIG_PAGE_SIZE_64KB) status |= (TFP_PAGESIZE_64K << 32) | (TFP_PAGESIZE_64K << 36); #endif write_c0_status(status); write_c0_wired(0); local_flush_tlb_all(); memcpy((void *)(CKSEG0 + 0x00), &except_vec0_generic, 0x80); memcpy((void *)(CKSEG0 + 0x80), except_vec1_r8k, 0x80); flush_icache_range(CKSEG0 + 0x80, CKSEG0 + 0x100); }
static int tx4939_proc_show_cp0(char *sysbuf, char **start, off_t off, int count, int *eof, void *data) { int len = 0; len += sprintf(sysbuf + len, "INDEX :0x%08x\n", read_c0_index()); len += sprintf(sysbuf + len, "ENTRYLO0:0x%08lx\n", read_c0_entrylo0()); len += sprintf(sysbuf + len, "ENTRYLO1:0x%08lx\n", read_c0_entrylo1()); len += sprintf(sysbuf + len, "CONTEXT :0x%08lx\n", read_c0_context()); len += sprintf(sysbuf + len, "PAGEMASK:0x%08x\n", read_c0_pagemask()); len += sprintf(sysbuf + len, "WIRED :0x%08x\n", read_c0_wired()); len += sprintf(sysbuf + len, "COUNT :0x%08x\n", read_c0_count()); len += sprintf(sysbuf + len, "ENTRYHI :0x%08lx\n", read_c0_entryhi()); len += sprintf(sysbuf + len, "COMPARE :0x%08x\n", read_c0_compare()); len += sprintf(sysbuf + len, "STATUS :0x%08x\n", read_c0_status()); len += sprintf(sysbuf + len, "CAUSE :0x%08x\n", read_c0_cause()); len += sprintf(sysbuf + len, "PRId :0x%08x\n", read_c0_prid()); len += sprintf(sysbuf + len, "CONFIG :0x%08x\n", read_c0_config()); len += sprintf(sysbuf + len, "XCONTEXT:0x%08lx\n", read_c0_xcontext()); len += sprintf(sysbuf + len, "TagLo :0x%08x\n", read_c0_taglo()); len += sprintf(sysbuf + len, "TagHi :0x%08x\n", read_c0_taghi()); len += sprintf(sysbuf + len, "ErrorEPC:0x%08lx\n", read_c0_errorepc()); *eof = 1; return len; }
/** * read core attribute */ void mips32_cfg_init(void) { rt_uint16_t val; rt_uint32_t cp0_config1; cp0_config1 = read_c0_config(); if (cp0_config1 & 0x80000000) { cp0_config1 = read_c0_config1(); val = (cp0_config1 & (7 << 22)) >> 22; g_mips_core.icache_lines_per_way = 64 * m_pow(2, val); val = (cp0_config1 & (7 << 19)) >> 19; g_mips_core.icache_line_size = 2 * m_pow(2, val); val = (cp0_config1 & (7 << 16)) >> 16; g_mips_core.icache_ways = val + 1; val = (cp0_config1 & (7 << 13)) >> 13; g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val); val = (cp0_config1 & (7 << 10)) >> 10; g_mips_core.dcache_line_size = 2 * m_pow(2, val); val = (cp0_config1 & (7 << 7)) >> 7; g_mips_core.dcache_ways = val + 1; val = (cp0_config1 & (0x3F << 25)) >> 25; g_mips_core.max_tlb_entries = val + 1; }
void tlb_init(void) { unsigned int config = read_c0_config(); unsigned long status; probe_tlb(config); status = read_c0_status(); status &= ~(ST0_UPS | ST0_KPS); #ifdef CONFIG_PAGE_SIZE_4KB status |= (TFP_PAGESIZE_4K << 32) | (TFP_PAGESIZE_4K << 36); #elif defined(CONFIG_PAGE_SIZE_8KB) status |= (TFP_PAGESIZE_8K << 32) | (TFP_PAGESIZE_8K << 36); #elif defined(CONFIG_PAGE_SIZE_16KB) status |= (TFP_PAGESIZE_16K << 32) | (TFP_PAGESIZE_16K << 36); #elif defined(CONFIG_PAGE_SIZE_64KB) status |= (TFP_PAGESIZE_64K << 32) | (TFP_PAGESIZE_64K << 36); #endif write_c0_status(status); write_c0_wired(0); local_flush_tlb_all(); build_tlb_refill_handler(); }
static inline void decode_config1(struct cpuinfo_mips *c) { unsigned long config0 = read_c0_config(); unsigned long config1; if ((config0 & (1 << 31)) == 0) return; /* actually wort a panic() */ /* MIPS32 or MIPS64 compliant CPU. Read Config 1 register. */ c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; config1 = read_c0_config1(); if (config1 & (1 << 3)) c->options |= MIPS_CPU_WATCH; if (config1 & (1 << 2)) c->options |= MIPS_CPU_MIPS16; if (config1 & (1 << 1)) c->options |= MIPS_CPU_EJTAG; if (config1 & 1) { c->options |= MIPS_CPU_FPU; c->options |= MIPS_CPU_32FPR; } c->scache.flags = MIPS_CACHE_NOT_PRESENT; c->tlbsize = ((config1 >> 25) & 0x3f) + 1; }
void __cpuinit spram_config(void) { struct cpuinfo_mips *c = ¤t_cpu_data; unsigned int config0; switch (c->cputype) { case CPU_24K: case CPU_34K: case CPU_74K: case CPU_1004K: config0 = read_c0_config(); /* FIXME: addresses are Malta specific */ #ifdef CONFIG_MIPS_TC3262 #ifdef CONFIG_TC3162_IMEM if (config0 & (1<<24)) { probe_spram("ISPRAM", CPHYSADDR(&__imem), &ispram_load_tag, &ispram_store_tag); ispram_fill(); if (!isRT63165 && !isRT63365 && !isMT751020) VPint(CR_DMC_ISPCFGR) = (CPHYSADDR(&__imem) & 0xfffff000) | (1<<8) | (0x7); } #endif #ifdef CONFIG_TC3162_DMEM if (isRT63165 || isRT63365) { VPint(CR_SRAM) = (CPHYSADDR(DSPRAM_BASE) & 0xffffc000) | (1<<0); printk(KERN_INFO "Enable SRAM=0x%08lx\n", VPint(CR_SRAM)); sram_allocp = (char *) CKSEG1ADDR(DSPRAM_BASE); sram_size = sram_free = 0x8000; } else { if (!isTC3182 && !isRT65168) { if (config0 & (1<<23)) { if(isMT751020){ probe_spram("DSPRAM", CPHYSADDR(DSPRAM_BASE), &dspram_load_tag, &dspram_store_tag); dspram_p = (char *)(DSPRAM_BASE); } else{ probe_spram("DSPRAM", CPHYSADDR(DSPRAM_BASE), &dspram_load_tag, &dspram_store_tag); VPint(CR_DMC_DSPCFGR) = (CPHYSADDR(DSPRAM_BASE) & 0xfffff000) | (1<<8) | (0x7); } } } } #endif #else if (config0 & (1<<24)) { probe_spram("ISPRAM", 0x1c000000, &ispram_load_tag, &ispram_store_tag); } if (config0 & (1<<23)) probe_spram("DSPRAM", 0x1c100000, &dspram_load_tag, &dspram_store_tag); #endif } }
void exception_handler(pt_regs_t *regs) { rt_uint32_t cause; rt_uint32_t index; cause = (read_c0_cause() & read_c0_config()); cause = (cause & 0xfc00) >> 8; for (index = RT_EXCEPTION_MAX; index > 0; index --) { if (cause & (1 << index)) { sys_exception_handlers[index](regs); cause &= ~(1 << index); } } }
void __init board_setup(void) { unsigned long config0, configpr; config0 = read_c0_config(); /* clear all three cache coherency fields */ config0 &= ~(0x7 | (7<<25) | (7<<28)); config0 |= (CONF_CM_DEFAULT | (CONF_CM_DEFAULT<<25) | (CONF_CM_DEFAULT<<28)); write_c0_config(config0); BARRIER; configpr = read_c0_config7(); configpr |= (1<<19); /* enable tlb */ write_c0_config7(configpr); BARRIER; }
PUBLIC void Jdb_kern_info_cpu::dump_cp0_regs() { Mword val; DUMP_CP0("EBase", read_c0_ebase(), val); DUMP_INT("Ebase.CPUNum", (val & 0x3ff)); DUMP_CP0("EntryHi", read_c0_entryhi(), val); DUMP_HEX("EntryHi.ASID", (val & 0xff)); DUMP_CP0("EPC", read_c0_epc(), val); DUMP_CP0("Status", read_c0_status(), val); DUMP_CP0("Cause", read_c0_cause(), val); DUMP_CP0("PRId", read_c0_prid(), val); DUMP_CP0("HWREna", read_c0_hwrena(), val); DUMP_CP0("Config", read_c0_config(), val); if (val & MIPS_CONF_M) { DUMP_CP0("Config1", read_c0_config1(), val); if (val & MIPS_CONF_M) { DUMP_CP0("Config2", read_c0_config2(), val); if (val & MIPS_CONF_M) { DUMP_CP0("Config3", read_c0_config3(), val); if (val & MIPS_CONF3_ULRI) DUMP_CP0("UserLocal", read_c0_userlocal(), val); } } } if (cpu_has_vz) DUMP_CP0("GuestCtl0", read_c0_guestctl0(), val); if (cpu_has_guestctl0ext) DUMP_CP0("GuestCtl0Ext", read_c0_guestctl0ext(), val); if (cpu_has_vz) DUMP_CP0("GTOffset", read_c0_gtoffset(), val); if (cpu_has_guestctl1) { DUMP_CP0("GuestCtl1", read_c0_guestctl1(), val); DUMP_HEX("GuestCtl1.ID", (val & GUESTCTL1_ID)); } if (cpu_has_guestctl2) { DUMP_CP0("GuestCtl2", read_c0_guestctl2(), val); DUMP_HEX("GuestCtl2.VIP", (val & GUESTCTL2_VIP)); } }
__cpuinit void spram_config(void) { struct cpuinfo_mips *c = ¤t_cpu_data; unsigned int config0; switch (c->cputype) { case CPU_24K: case CPU_34K: case CPU_74K: config0 = read_c0_config(); /* FIXME: addresses are Malta specific */ if (config0 & (1<<24)) { probe_spram("ISPRAM", 0x1c000000, &ispram_load_tag, &ispram_store_tag); } if (config0 & (1<<23)) probe_spram("DSPRAM", 0x1c100000, &dspram_load_tag, &dspram_store_tag); } }
void dump_cp0(char *key) { if (key == NULL) key = ""; print_cp0(key, 0, "INDEX ", read_c0_index()); print_cp0(key, 2, "ENTRYLO1", read_c0_entrylo0()); print_cp0(key, 3, "ENTRYLO2", read_c0_entrylo1()); print_cp0(key, 4, "CONTEXT ", read_c0_context()); print_cp0(key, 5, "PAGEMASK", read_c0_pagemask()); print_cp0(key, 6, "WIRED ", read_c0_wired()); //print_cp0(key, 8, "BADVADDR", read_c0_badvaddr()); print_cp0(key, 9, "COUNT ", read_c0_count()); print_cp0(key, 10, "ENTRYHI ", read_c0_entryhi()); print_cp0(key, 11, "COMPARE ", read_c0_compare()); print_cp0(key, 12, "STATUS ", read_c0_status()); print_cp0(key, 13, "CAUSE ", read_c0_cause() & 0xffff87ff); print_cp0(key, 16, "CONFIG ", read_c0_config()); return; }
void __cpuinit spram_config(void) { struct cpuinfo_mips *c = ¤t_cpu_data; unsigned int config0; switch (c->cputype) { case CPU_24K: case CPU_34K: case CPU_74K: case CPU_1074K: case CPU_1004K: config0 = read_c0_config(); if (config0 & (1<<24)) { probe_spram("ISPRAM", 0x1c000000, &ispram_load_tag, &ispram_store_tag); } if (config0 & (1<<23)) probe_spram("DSPRAM", 0x1c100000, &dspram_load_tag, &dspram_store_tag); } }
static void __init rbtx4927_mem_setup(void) { u32 cp0_config; char *argptr; /* enable caches -- HCP5 does this, pmon does not */ cp0_config = read_c0_config(); cp0_config = cp0_config & ~(TX49_CONF_IC | TX49_CONF_DC); write_c0_config(cp0_config); if (TX4927_REV_PCODE() == 0x4927) { rbtx4927_clock_init(); tx4927_setup(); } else { rbtx4937_clock_init(); tx4938_setup(); } _machine_restart = toshiba_rbtx4927_restart; #ifdef CONFIG_PCI txx9_alloc_pci_controller(&txx9_primary_pcic, RBTX4927_PCIMEM, RBTX4927_PCIMEM_SIZE, RBTX4927_PCIIO, RBTX4927_PCIIO_SIZE); txx9_board_pcibios_setup = tx4927_pcibios_setup; #else set_io_port_base(KSEG1 + RBTX4927_ISA_IO_OFFSET); #endif tx4927_sio_init(0, 0); #ifdef CONFIG_SERIAL_TXX9_CONSOLE argptr = prom_getcmdline(); if (!strstr(argptr, "console=")) strcat(argptr, " console=ttyS0,38400"); #endif }
static inline void cpu_probe_legacy(struct cpuinfo_mips *c) { switch (c->processor_id & 0xff00) { case PRID_IMP_R2000: c->cputype = CPU_R2000; c->isa_level = MIPS_CPU_ISA_I; c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX; if (__cpu_has_fpu()) c->options |= MIPS_CPU_FPU; c->tlbsize = 64; break; case PRID_IMP_R3000: if ((c->processor_id & 0xff) == PRID_REV_R3000A) if (cpu_has_confreg()) c->cputype = CPU_R3081E; else c->cputype = CPU_R3000A; else c->cputype = CPU_R3000; c->isa_level = MIPS_CPU_ISA_I; c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX; if (__cpu_has_fpu()) c->options |= MIPS_CPU_FPU; c->tlbsize = 64; break; case PRID_IMP_R4000: if (read_c0_config() & CONF_SC) { if ((c->processor_id & 0xff) >= PRID_REV_R4400) c->cputype = CPU_R4400PC; else c->cputype = CPU_R4000PC; } else { if ((c->processor_id & 0xff) >= PRID_REV_R4400) c->cputype = CPU_R4400SC; else c->cputype = CPU_R4000SC; } c->isa_level = MIPS_CPU_ISA_III; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_WATCH | MIPS_CPU_VCE | MIPS_CPU_LLSC; c->tlbsize = 48; break; case PRID_IMP_VR41XX: switch (c->processor_id & 0xf0) { #ifndef CONFIG_VR4181 case PRID_REV_VR4111: c->cputype = CPU_VR4111; break; #else case PRID_REV_VR4181: c->cputype = CPU_VR4181; break; #endif case PRID_REV_VR4121: c->cputype = CPU_VR4121; break; case PRID_REV_VR4122: if ((c->processor_id & 0xf) < 0x3) c->cputype = CPU_VR4122; else c->cputype = CPU_VR4181A; break; case PRID_REV_VR4130: if ((c->processor_id & 0xf) < 0x4) c->cputype = CPU_VR4131; else c->cputype = CPU_VR4133; break; default: printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); c->cputype = CPU_VR41XX; break; } c->isa_level = MIPS_CPU_ISA_III; c->options = R4K_OPTS; c->tlbsize = 32; break; case PRID_IMP_R4300: c->cputype = CPU_R4300; c->isa_level = MIPS_CPU_ISA_III; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_LLSC; c->tlbsize = 32; break; case PRID_IMP_R4600: c->cputype = CPU_R4600; c->isa_level = MIPS_CPU_ISA_III; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; c->tlbsize = 48; break; #if 0 case PRID_IMP_R4650: /* * This processor doesn't have an MMU, so it's not * "real easy" to run Linux on it. It is left purely * for documentation. Commented out because it shares * it's c0_prid id number with the TX3900. */ c->cputype = CPU_R4650; c->isa_level = MIPS_CPU_ISA_III; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; c->tlbsize = 48; break; #endif case PRID_IMP_TX39: c->isa_level = MIPS_CPU_ISA_I; c->options = MIPS_CPU_TLB; if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { c->cputype = CPU_TX3927; c->tlbsize = 64; } else { switch (c->processor_id & 0xff) { case PRID_REV_TX3912: c->cputype = CPU_TX3912; c->tlbsize = 32; break; case PRID_REV_TX3922: c->cputype = CPU_TX3922; c->tlbsize = 64; break; default: c->cputype = CPU_UNKNOWN; break; } } break; case PRID_IMP_R4700: c->cputype = CPU_R4700; c->isa_level = MIPS_CPU_ISA_III; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_LLSC; c->tlbsize = 48; break; case PRID_IMP_TX49: c->cputype = CPU_TX49XX; c->isa_level = MIPS_CPU_ISA_III; c->options = R4K_OPTS | MIPS_CPU_LLSC; if (!(c->processor_id & 0x08)) c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; c->tlbsize = 48; break; case PRID_IMP_R5000: c->cputype = CPU_R5000; c->isa_level = MIPS_CPU_ISA_IV; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_LLSC; c->tlbsize = 48; break; case PRID_IMP_R5432: c->cputype = CPU_R5432; c->isa_level = MIPS_CPU_ISA_IV; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_WATCH | MIPS_CPU_LLSC; c->tlbsize = 48; break; case PRID_IMP_R5500: c->cputype = CPU_R5500; c->isa_level = MIPS_CPU_ISA_IV; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_WATCH | MIPS_CPU_LLSC; c->tlbsize = 48; break; case PRID_IMP_NEVADA: c->cputype = CPU_NEVADA; c->isa_level = MIPS_CPU_ISA_IV; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_DIVEC | MIPS_CPU_LLSC; c->tlbsize = 48; break; case PRID_IMP_R6000: c->cputype = CPU_R6000; c->isa_level = MIPS_CPU_ISA_II; c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | MIPS_CPU_LLSC; c->tlbsize = 32; break; case PRID_IMP_R6000A: c->cputype = CPU_R6000A; c->isa_level = MIPS_CPU_ISA_II; c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | MIPS_CPU_LLSC; c->tlbsize = 32; break; case PRID_IMP_RM7000: c->cputype = CPU_RM7000; c->isa_level = MIPS_CPU_ISA_IV; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_LLSC; /* * Undocumented RM7000: Bit 29 in the info register of * the RM7000 v2.0 indicates if the TLB has 48 or 64 * entries. * * 29 1 => 64 entry JTLB * 0 => 48 entry JTLB */ c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; break; case PRID_IMP_RM9000: c->cputype = CPU_RM9000; c->isa_level = MIPS_CPU_ISA_IV; c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_LLSC; /* * Bit 29 in the info register of the RM9000 * indicates if the TLB has 48 or 64 entries. * * 29 1 => 64 entry JTLB * 0 => 48 entry JTLB */ c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; break; case PRID_IMP_R8000: c->cputype = CPU_R8000; c->isa_level = MIPS_CPU_ISA_IV; c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_LLSC; c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ break; case PRID_IMP_R10000: c->cputype = CPU_R10000; c->isa_level = MIPS_CPU_ISA_IV; c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | MIPS_CPU_LLSC; c->tlbsize = 64; break; case PRID_IMP_R12000: c->cputype = CPU_R12000; c->isa_level = MIPS_CPU_ISA_IV; c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_FPU | MIPS_CPU_32FPR | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | MIPS_CPU_LLSC; c->tlbsize = 64; break; } }
void __init prom_init(void) { #ifdef CONFIG_MIPS_BRCM97XXX int hasCfeParms = 0; int res = -1; char msg[COMMAND_LINE_SIZE]; extern void determineBootFromFlashOrRom(void); #endif uart_init(27000000); /* jipeng - mask out UPG L2 interrupt here */ BDEV_WR(BCHP_IRQ0_IRQEN, 0); #ifdef CONFIG_TIVO_KONTIKI board_pinmux_setup(); #endif /* Fill in platform information */ mips_machgroup = MACH_GROUP_BRCM; mips_machtype = MACH_BRCM_STB; #ifdef BRCM_SATA_SUPPORTED brcm_sata_enabled = 1; #endif #ifdef BRCM_ENET_SUPPORTED brcm_enet_enabled = 1; #endif #ifdef BRCM_EMAC_1_SUPPORTED brcm_emac_1_enabled = 1; #endif #ifdef BRCM_PCI_SUPPORTED brcm_pci_enabled = 1; #endif #ifdef CONFIG_SMP brcm_smp_enabled = 1; #endif #ifdef CONFIG_MIPS_BCM7118 /* detect 7118RNG board */ if( BDEV_RD(BCHP_CLKGEN_REG_START) == 0x1c ) brcm_sata_enabled = 0; /* onchip DOCSIS owns the ENET */ brcm_enet_enabled = 0; #endif #ifdef CONFIG_MIPS_BCM7405 /* detect 7406 */ if(BDEV_RD(BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS) & BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_sata_disable_MASK) brcm_sata_enabled = 0; switch(BDEV_RD(BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS) & 0xf) { case 0x0: /* 7405/7406 */ break; case 0x1: /* 7466 */ brcm_pci_enabled = 0; brcm_emac_1_enabled = 0; break; case 0x3: /* 7106 */ brcm_emac_1_enabled = 0; brcm_smp_enabled = 0; break; case 0x4: /* 7205 */ brcm_emac_1_enabled = 0; break; } #endif #if defined( CONFIG_MIPS_BCM7118 ) || defined( CONFIG_MIPS_BCM7401C0 ) \ || defined( CONFIG_MIPS_BCM7402C0 ) || defined( CONFIG_MIPS_BCM3563 ) \ || defined (CONFIG_MIPS_BCM3563C0) /*need set bus to async mode before enabling the following*/ if(!(read_c0_diag4() & 0x400000)) { int val=read_c0_diag4(); write_c0_diag4(val | 0x400000); sprintf(msg, "CP0 reg 22 sel 0 to 5: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", read_c0_diag(), read_c0_diag1(), read_c0_diag2(), read_c0_diag3(), read_c0_diag4(), read_c0_diag5()); uart_puts(msg); write_c0_config(0x80008083); sprintf(msg, "CP0 reg 16 sel 0 to 1: 0x%08x 0x%08x \n", read_c0_config(), read_c0_config1()); uart_puts(msg); } /* Enable write gathering (BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT) */ BDEV_WR(0x0000040c, 0x264); /* Enable Split Mode (BCHP_MISB_BRIDGE_MISB_SPLIT_MODE) */ BDEV_WR(0x00000410, 0x1); #elif defined( CONFIG_MIPS_BCM7440A0 ) if(!(read_c0_diag4() & 0x400000)) { int val=read_c0_diag4(); write_c0_diag4(val | 0x400000); sprintf(msg, "CP0 reg 22 sel 0 to 5: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", read_c0_diag(), read_c0_diag1(), read_c0_diag2(), read_c0_diag3(), read_c0_diag4(), read_c0_diag5()); uart_puts(msg); write_c0_config(0x80008083); sprintf(msg, "CP0 reg 16 sel 0 to 1: 0x%08x 0x%08x \n", read_c0_config(), read_c0_config1()); uart_puts(msg); } /* Enable write gathering (BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT) */ BDEV_WR(0x0000040c, 0x2803); #endif #ifdef CONFIG_TIVO_MOJAVE if ( cfe_seal != CFE_SEAL ){ goto noncfe; } #endif /* Kernel arguments */ #ifdef CONFIG_MIPS_BRCM97XXX /* For the 97xxx series STB, process CFE boot parms */ { int i; for (i=0; i<MAX_HWADDR; i++) { gHwAddrs[i] = &privHwAddrs[i][0]; } } #ifdef CONFIG_TIVO_KONTIKI res = get_cfe_boot_parms(); hasCfeParms = (res == 0); #if 1 /* ###JLF */ if (gNumHwAddrs > 0) { printk("%s(): Got CFE MAC address " "%02x:%02x:%02x:%02x:%02x:%02x\n", __FUNCTION__, gHwAddrs[0][0], gHwAddrs[0][1], gHwAddrs[0][2], gHwAddrs[0][3], gHwAddrs[0][4], gHwAddrs[0][5]); } #endif #ifdef BRCM_MEMORY_STRAPS get_RAM_size(); #else if(brcm_dram0_size == 0) brcm_dram0_size = probe_memsize(); #ifndef CONFIG_DISCONTIGMEM if(brcm_dram0_size > (256 << 20)) { printk("Extra RAM beyond 256MB ignored. Please " "use a kernel that supports DISCONTIG.\n"); brcm_dram0_size = 256 << 20; } #endif /* CONFIG_DISCONTIGMEM */ #endif /* BRCM_MEMORY_STRAPS */ // Make sure cfeBootParms is not empty or contains all white space if (hasCfeParms) { int i; hasCfeParms = 0; for (i=0; i < strlen(cfeBootParms); i++) { if (isspace(cfeBootParms[i])) { continue; } else if (cfeBootParms[i] == '\0') { break; // and leave hasCfeParms false } else { hasCfeParms = 1; break; } } } #else /* if !defined(CONFIG_TIVO_KONTIKI) */ res = get_cfe_boot_parms(cfeBootParms, &gNumHwAddrs, gHwAddrs); if(gNumHwAddrs <= 0) { #if !defined(CONFIG_BRCM_PCI_SLAVE) unsigned int i, mac = FLASH_MACADDR_ADDR, ok = 0; for(i = 0; i < 3; i++) { u16 word = readw((void *)mac); if(word != 0x0000 && word != 0xffff) ok = 1; gHwAddrs[0][(i << 1)] = word & 0xff; gHwAddrs[0][(i << 1) + 1] = word >> 8; mac += 2; } /* display warning for all 00's, all ff's, or multicast */ if(! ok || (gHwAddrs[0][1] & 1)) { printk(KERN_WARNING "WARNING: read invalid MAC address " "%02x:%02x:%02x:%02x:%02x:%02x from flash @ 0x%08x\n", gHwAddrs[0][0], gHwAddrs[0][1], gHwAddrs[0][2], gHwAddrs[0][3], gHwAddrs[0][4], gHwAddrs[0][5], FLASH_MACADDR_ADDR); } #else /* PCI slave mode - no EBI/flash available */ u8 fixed_macaddr[] = { 0x00, 0xc0, 0xa8, 0x74, 0x3b, 0x51 }; memcpy(&gHwAddrs[0][0], fixed_macaddr, sizeof(fixed_macaddr)); #endif gNumHwAddrs = 1; }