/* HW Initialization, if return 0, initialization is successful. */
static int board_sata_init(struct device *dev, void __iomem *addr)
{
u32 tmpdata;
int ret = 0;
struct clk *clk;
sata_clk = clk_get(dev, "imx_sata_clk");
if (IS_ERR(sata_clk)) {
dev_err(dev, "no sata clock.\n");
return PTR_ERR(sata_clk);
}
ret = clk_enable(sata_clk);
if (ret) {
dev_err(dev, "can't enable sata clock.\n");
goto put_sata_clk;
}
/* Set PHY Paremeters, two steps to configure the GPR13,
* one write for rest of parameters, mask of first write is 0x07FFFFFD,
* and the other one write for setting the mpll_clk_off_b
*.rx_eq_val_0(iomuxc_gpr13[26:24]),
*.los_lvl(iomuxc_gpr13[23:19]),
*.rx_dpll_mode_0(iomuxc_gpr13[18:16]),
*.sata_speed(iomuxc_gpr13[15]),
*.mpll_ss_en(iomuxc_gpr13[14]),
*.tx_atten_0(iomuxc_gpr13[13:11]),
*.tx_boost_0(iomuxc_gpr13[10:7]),
*.tx_lvl(iomuxc_gpr13[6:2]),
*.mpll_ck_off(iomuxc_gpr13[1]),
*.tx_edgerate_0(iomuxc_gpr13[0]),
*/
tmpdata = readl(IOMUXC_GPR13);
writel(((tmpdata & ~0x07FFFFFF) | 0x0593A044), IOMUXC_GPR13);
/* enable SATA_PHY PLL */
tmpdata = readl(IOMUXC_GPR13);
writel(((tmpdata & ~0x2) | 0x2), IOMUXC_GPR13);
/* Get the AHB clock rate, and configure the TIMER1MS reg later */
clk = clk_get(NULL, "ahb");
if (IS_ERR(clk)) {
dev_err(dev, "no ahb clock.\n");
ret = PTR_ERR(clk);
goto release_sata_clk;
}
tmpdata = clk_get_rate(clk) / 1000;
clk_put(clk);
ret = sata_init(addr, tmpdata);
if (ret == 0)
return ret;
release_sata_clk:
clk_disable(sata_clk);
put_sata_clk:
clk_put(sata_clk);
return ret;
}
int board_late_init(void)
{
#ifdef CONFIG_SCSI_AHCI_PLAT
sata_init();
#endif
return 0;
}
int board_late_init(void)
{
#ifdef CONFIG_SCSI_AHCI_PLAT
sata_init();
#endif
#ifdef CONFIG_CHAIN_OF_TRUST
fsl_setenv_chain_of_trust();
#endif
#ifdef CONFIG_QSPI_AHB_INIT
qspi_ahb_init();
#endif
return 0;
}
void sb700_after_pci_fixup(void) {
#ifdef ENABLE_SATA
printk_info("sata init\n");
sata_init(_pci_make_tag(0, 0x11, 0));
#endif
printk_info("OHCI0-USB1 init\n");
usb_init(_pci_make_tag(0, 0x12, 0));
printk_info("OHCI1-USB1 init\n");
usb_init(_pci_make_tag(0, 0x12, 1));
#if 1
//printk_info("EHCI-USB1 init\n");
//usb_init2(_pci_make_tag(0, 0x12, 2));
printk_info("OHCI0-USB2 init\n");
usb_init(_pci_make_tag(0, 0x13, 0));
printk_info("OHCI1-USB2 init\n");
usb_init(_pci_make_tag(0, 0x13, 1));
//printk_info("EHCI-USB2 init\n");
//usb_init2(_pci_make_tag(0, 0x13, 2));
printk_info("OHCI0-USB3 init\n");
usb_init(_pci_make_tag(0, 0x14, 5));
#endif
printk_info("lpc init\n");
lpc_init(_pci_make_tag(0, 0x14, 3));
printk_info("ide init\n");
ide_init(_pci_make_tag(0, 0x14, 1));
//vga test
printk_info("pci init\n");
pci_init(_pci_make_tag(0, 0x14, 4));
printk_info("sm init\n");
sm_init(_pci_make_tag(0, 0x14, 0));
#ifdef USE_780E_VGA
printk_info("rs780_internal_gfx_init\n");
internal_gfx_pci_dev_init(_pci_make_tag(0,0,0) , _pci_make_tag(1,0x5,0));
#endif
}
/* HW Initialization, if return 0, initialization is successful. */
static int wand_sata_init(struct device *dev, void __iomem *addr)
{
u32 tmpdata;
int ret = 0;
struct clk *clk;
wand_sata_clk = clk_get(dev, "imx_sata_clk");
if (IS_ERR(wand_sata_clk)) {
dev_err(dev, "no sata clock.\n");
return PTR_ERR(wand_sata_clk);
}
ret = clk_enable(wand_sata_clk);
if (ret) {
dev_err(dev, "can't enable sata clock.\n");
goto put_sata_clk;
}
/* Set PHY Paremeters, two steps to configure the GPR13,
* one write for rest of parameters, mask of first write is 0x07FFFFFD,
* and the other one write for setting the mpll_clk_off_b
*.rx_eq_val_0(iomuxc_gpr13[26:24]),
*.los_lvl(iomuxc_gpr13[23:19]),
*.rx_dpll_mode_0(iomuxc_gpr13[18:16]),
*.sata_speed(iomuxc_gpr13[15]),
*.mpll_ss_en(iomuxc_gpr13[14]),
*.tx_atten_0(iomuxc_gpr13[13:11]),
*.tx_boost_0(iomuxc_gpr13[10:7]),
*.tx_lvl(iomuxc_gpr13[6:2]),
*.mpll_ck_off(iomuxc_gpr13[1]),
*.tx_edgerate_0(iomuxc_gpr13[0]),
*/
tmpdata = readl(IOMUXC_GPR13);
writel(tmpdata & ~0x2, IOMUXC_GPR13);
writel(((tmpdata & ~0x07FFFFFF) | 0x0593A046), IOMUXC_GPR13);
sata_phy_cr_addr(0x7F3F, addr);
sata_phy_cr_write(0x1, addr);
sata_phy_cr_read(&tmpdata, addr);
/* Get the AHB clock rate, and configure the TIMER1MS reg later */
clk = clk_get(NULL, "ahb");
if (IS_ERR(clk)) {
dev_err(dev, "no ahb clock.\n");
ret = PTR_ERR(clk);
goto release_sata_clk;
}
tmpdata = clk_get_rate(clk) / 1000;
clk_put(clk);
#ifdef CONFIG_SATA_AHCI_PLATFORM
ret = sata_init(addr, tmpdata);
if (ret == 0)
return ret;
#else
usleep_range(1000, 2000);
/* AHCI PHY enter into PDDQ mode if the AHCI module is not enabled */
tmpdata = readl(addr + PORT_PHY_CTL);
writel(tmpdata | PORT_PHY_CTL_PDDQ_LOC, addr + PORT_PHY_CTL);
pr_info("No AHCI save PWR: PDDQ %s\n", ((readl(addr + PORT_PHY_CTL)
>> 20) & 1) ? "enabled" : "disabled");
#endif
release_sata_clk:
/* disable SATA_PHY PLL */
writel((readl(IOMUXC_GPR13) & ~0x2), IOMUXC_GPR13);
clk_disable(wand_sata_clk);
put_sata_clk:
clk_put(wand_sata_clk);
return ret;
}