void __init iop_init_time(unsigned long tick_rate) { u32 timer_ctl; setup_sched_clock(iop_read_sched_clock, 32, tick_rate); ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ); iop_tick_rate = tick_rate; timer_ctl = IOP_TMR_EN | IOP_TMR_PRIVILEGED | IOP_TMR_RELOAD | IOP_TMR_RATIO_1_1; /* * Set up interrupting clockevent timer 0. */ write_tmr0(timer_ctl & ~IOP_TMR_EN); write_tisr(1); setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq); clockevents_calc_mult_shift(&iop_clockevent, tick_rate, IOP_MIN_RANGE); iop_clockevent.max_delta_ns = clockevent_delta2ns(0xfffffffe, &iop_clockevent); iop_clockevent.min_delta_ns = clockevent_delta2ns(0xf, &iop_clockevent); iop_clockevent.cpumask = cpumask_of(0); clockevents_register_device(&iop_clockevent); /* * Set up free-running clocksource timer 1. */ write_trr1(0xffffffff); write_tcr1(0xffffffff); write_tmr1(timer_ctl); clocksource_register_hz(&iop_clocksource, tick_rate); }
static void __init shmac_clocksource_init(struct device_node *node) { void __iomem *base; u32 freq; base = of_iomap(node, 0); source_base = (u32) base; if (!base) panic("Can't remap registers"); if (of_property_read_u32(node, "clock-frequency", &freq)) panic("Can't read clock-frequency"); SHMAC_TIMER_CLEAR(base); SHMAC_TIMER_START(base); setup_sched_clock(shmac_sched_clock_read, 32, freq/1024); /* Schedule a clock read from system tick counter instead of using the timer value as a clocksource. if(clocksource_mmio_init(base + TIMER_VALUE, "SHMAC clocksource", freq, 200, 24, shmac_clocksource_mmio_readl_down)) panic("Can't register clocksource\n"); */ pr_info("SHMAC clocksource init done\n"); }
static void __init omap2_gptimer_clocksource_init(int gptimer_id, const char *fck_source, const char *property) { int res; clksrc.id = gptimer_id; clksrc.errata = omap_dm_timer_get_errata(); res = omap_dm_timer_init_one(&clksrc, fck_source, property, &clocksource_gpt.name, OMAP_TIMER_NONPOSTED); BUG_ON(res); __omap_dm_timer_load_start(&clksrc, OMAP_TIMER_CTRL_ST | OMAP_TIMER_CTRL_AR, 0, OMAP_TIMER_NONPOSTED); setup_sched_clock(dmtimer_read_sched_clock, 32, clksrc.rate); if (clocksource_register_hz(&clocksource_gpt, clksrc.rate)) pr_err("Could not register clocksource %s\n", clocksource_gpt.name); else pr_info("OMAP clocksource: %s at %lu Hz\n", clocksource_gpt.name, clksrc.rate); }
static void __init bcm2708_timer_init(void) { /* init high res timer */ bcm2708_clocksource_init(); /* * Initialise to a known state (all timers off) */ writel(0, __io_address(ARM_T_CONTROL)); /* * Make irqs happen for the system timer */ setup_irq(IRQ_TIMER3, &bcm2708_timer_irq); setup_sched_clock(bcm2708_read_sched_clock, 32, STC_FREQ_HZ); timer0_clockevent.mult = div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift); timer0_clockevent.max_delta_ns = clockevent_delta2ns(0xffffffff, &timer0_clockevent); timer0_clockevent.min_delta_ns = clockevent_delta2ns(0xf, &timer0_clockevent); timer0_clockevent.cpumask = cpumask_of(0); clockevents_register_device(&timer0_clockevent); register_current_timer_delay(&bcm2708_delay_timer); }
static void __init ixp4xx_clocksource_init(void) { setup_sched_clock(ixp4xx_read_sched_clock, 32, ixp4xx_timer_freq); clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32, ixp4xx_clocksource_read); }
void __init orion_time_init(unsigned int irq, unsigned int tclk) { u32 u; ticks_per_jiffy = (tclk + HZ/2) / HZ; /* * Set scale and timer for sched_clock */ setup_sched_clock(tclk); /* * Setup free-running clocksource timer (interrupts * disabled.) */ writel(0xffffffff, TIMER0_VAL); writel(0xffffffff, TIMER0_RELOAD); u = readl(BRIDGE_MASK); writel(u & ~BRIDGE_INT_TIMER0, BRIDGE_MASK); u = readl(TIMER_CTRL); writel(u | TIMER0_EN | TIMER0_RELOAD_EN, TIMER_CTRL); orion_clksrc.mult = clocksource_hz2mult(tclk, orion_clksrc.shift); clocksource_register(&orion_clksrc); /* * Setup clockevent timer (interrupt-driven.) */ setup_irq(irq, &orion_timer_irq); orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift); orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt); orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt); orion_clkevt.cpumask = cpumask_of(0); clockevents_register_device(&orion_clkevt); }
void __init aw_clksrc_init(void) { pr_info("%s(%d)\n", __func__, __LINE__); #if 0 /* start counting on booting, so cannot clear it, otherwise systime will be err */ /* we use 64bits counter as HPET(High Precision Event Timer) */ writel(0, SW_HSTMR_CTRL_REG); /* config clock source for 64bits counter */ temp = readl(SW_HSTMR_CTRL_REG); temp &= ~(1<<2); /* clear 64bits counter */ temp |= (1<<0); writel(temp, SW_HSTMR_CTRL_REG); /* wait clear complete */ while(cnt-- && (readl(SW_HSTMR_CTRL_REG) & (1<<0))); if(unlikely(0 == cnt)) pr_err("%s(%d): wait cleared timeout\n", __func__, __LINE__); #endif /* calculate the mult by shift */ aw_clocksrc.mult = clocksource_hz2mult(AW_HPET_CLOCK_SOURCE_HZ, aw_clocksrc.shift); /* register clock source */ clocksource_register(&aw_clocksrc); /* set sched clock */ setup_sched_clock(sched_clock_read, 32, AW_HPET_CLOCK_SOURCE_HZ); pr_info("%s(%d)\n", __func__, __LINE__); }
void __init sched_clock_postinit(void) { if (read_sched_clock == jiffy_sched_clock_read) setup_sched_clock(jiffy_sched_clock_read, 32, HZ); sched_clock_poll(sched_clock_timer.data); }
void __init apb_timer_init(void) { int cpu; tmr_group0_config(); tmr_group1_config(); tmr_group2_config(); setup_sched_clock(mmp_read_sched_clock, 32, CLOCK_TICK_RATE_32KHZ); clockevents_calc_mult_shift(&ckevt, CLOCK_TICK_RATE_32KHZ, 4); ckevt.max_delta_ns = clockevent_delta2ns(MAX_DELTA, &ckevt); ckevt.min_delta_ns = clockevent_delta2ns(MIN_DELTA, &ckevt); ckevt.cpumask = cpumask_of(0); ckevt.irq = IRQ_PXA1088_AP3_TIMER1; setup_irq(ckevt.irq, &timer_irq); clocksource_register_hz(&cksrc, CLOCK_TICK_RATE_32KHZ); clockevents_register_device(&ckevt); for (cpu = 0; cpu < num_possible_cpus(); cpu++) { setup_irq(irq_map[cpu].irq, &irq_map[cpu].irq_act); disable_irq(irq_map[cpu].irq); } local_timer_register(&mmp_percpu_timer_ops); }
void __init clksrc_dbx500_prcmu_init(void __iomem *base) { clksrc_dbx500_timer_base = base; /* * The A9 sub system expects the timer to be configured as * a continous looping timer. * The PRCMU should configure it but if it for some reason * don't we do it here. */ if (readl(clksrc_dbx500_timer_base + PRCMU_TIMER_MODE) != TIMER_MODE_CONTINOUS) { writel(TIMER_MODE_CONTINOUS, clksrc_dbx500_timer_base + PRCMU_TIMER_MODE); writel(TIMER_DOWNCOUNT_VAL, clksrc_dbx500_timer_base + PRCMU_TIMER_REF); } #ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK setup_sched_clock(dbx500_prcmu_sched_clock_read, 32, RATE_32K); #endif clocksource_calc_mult_shift(&clocksource_dbx500_prcmu, RATE_32K, SCHED_CLOCK_MIN_WRAP); clocksource_register(&clocksource_dbx500_prcmu); boottime_activate(&boottime_timer); }
void __init nmdk_timer_init(void __iomem *base, int irq) { unsigned long rate; struct clk *clk0, *pclk0; mtu_base = base; pclk0 = clk_get_sys("mtu0", "apb_pclk"); BUG_ON(IS_ERR(pclk0)); BUG_ON(clk_prepare(pclk0) < 0); BUG_ON(clk_enable(pclk0) < 0); clk0 = clk_get_sys("mtu0", NULL); BUG_ON(IS_ERR(clk0)); BUG_ON(clk_prepare(clk0) < 0); BUG_ON(clk_enable(clk0) < 0); /* * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz * for ux500. * Use a divide-by-16 counter if the tick rate is more than 32MHz. * At 32 MHz, the timer (with 32 bit counter) can be programmed * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer * with 16 gives too low timer resolution. */ rate = clk_get_rate(clk0); if (rate > 32000000) { rate /= 16; clk_prescale = MTU_CRn_PRESCALE_16; } else { clk_prescale = MTU_CRn_PRESCALE_1; } /* Cycles for periodic mode */ nmdk_cycle = DIV_ROUND_CLOSEST(rate, HZ); /* Timer 0 is the free running clocksource */ nmdk_clksrc_reset(); if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0", rate, 200, 32, clocksource_mmio_readl_down)) pr_err("timer: failed to initialize clock source %s\n", "mtu_0"); #ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK setup_sched_clock(nomadik_read_sched_clock, 32, rate); #endif /* Timer 1 is used for events, register irq and clockevents */ setup_irq(irq, &nmdk_timer_irq); nmdk_clkevt.cpumask = cpumask_of(0); nmdk_clkevt.irq = irq; clockevents_config_and_register(&nmdk_clkevt, rate, 2, 0xffffffffU); mtu_delay_timer.read_current_timer = &nmdk_timer_read_current_timer; mtu_delay_timer.freq = rate; register_current_timer_delay(&mtu_delay_timer); }
int __init arch_timer_sched_clock_init(void) { if (arch_timer_get_rate() == 0) return -ENXIO; setup_sched_clock(arch_timer_read_counter_u32, 32, arch_timer_get_rate()); return 0; }
void __init sched_clock_postinit(void) { /* * If no sched_clock function has been provided at that point, * make it the final one one. */ if (read_sched_clock == jiffy_sched_clock_read) setup_sched_clock(jiffy_sched_clock_read, 32, HZ); sched_clock_poll(sched_clock_timer.data); }
static int __init mxc_clocksource_init(struct clk *timer_clk) { unsigned int c = clk_get_rate(timer_clk); void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN); sched_clock_reg = reg; setup_sched_clock(mxc_read_sched_clock, 32, c); return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32, clocksource_mmio_readl_up); }
static void __init ns115_clocksource_init(void) { /* setup timer 0 as free-running clocksource */ writel(0, _timer3_va_base + TIMERX_CTRL); writel(0xffffffff, _timer3_va_base + TIMERX_LOAD); writel(3, _timer3_va_base + TIMERX_CTRL); setup_sched_clock(ns115_get_cycles, 32, TIMER_CLK_RATE); clocksource_register_hz(&clocksource_ns115, TIMER_CLK_RATE); clocksource_register_hz(&clocksource_ns115_n, TIMER_CLK_RATE_N); }
int __init omap_init_clocksource_32k(void) { static char err[] __initdata = KERN_ERR "%s: can't register clocksource!\n"; if (cpu_is_omap16xx() || cpu_class_is_omap2()) { u32 pbase; unsigned long size = SZ_4K; void __iomem *base; struct clk *sync_32k_ick; if (cpu_is_omap16xx()) { pbase = OMAP16XX_TIMER_32K_SYNCHRONIZED; size = SZ_1K; } else if (cpu_is_omap2420()) pbase = OMAP2420_32KSYNCT_BASE + 0x10; else if (cpu_is_omap2430()) pbase = OMAP2430_32KSYNCT_BASE + 0x10; else if (cpu_is_omap34xx()) pbase = OMAP3430_32KSYNCT_BASE + 0x10; else if (cpu_is_omap44xx()) pbase = OMAP4430_32KSYNCT_BASE + 0x10; else if (cpu_is_omap54xx()) pbase = OMAP54XX_32KSYNCT_BASE + 0x30; else return -ENODEV; /* For this to work we must have a static mapping in io.c for this area */ base = ioremap(pbase, size); if (!base) return -ENODEV; sync_32k_ick = clk_get(NULL, "omap_32ksync_ick"); if (!IS_ERR(sync_32k_ick)) clk_enable(sync_32k_ick); timer_32k_base = base; /* * 120000 rough estimate from the calculations in * __clocksource_updatefreq_scale. */ clocks_calc_mult_shift(&persistent_mult, &persistent_shift, 32768, NSEC_PER_SEC, 120000); if (clocksource_mmio_init(base, "32k_counter", 32768, 250, 32, clocksource_mmio_readl_up)) printk(err, "32k_counter"); setup_sched_clock(omap_32k_read_sched_clock, 32, 32768); } return 0; }
static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base) { struct ttc_timer_clocksource *ttccs; int err; ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL); if (WARN_ON(!ttccs)) return; ttccs->ttc.clk = clk; err = clk_prepare_enable(ttccs->ttc.clk); if (WARN_ON(err)) { kfree(ttccs); return; } ttccs->ttc.clk_rate_change_nb.notifier_call = ttc_rate_change_clocksource_cb; ttccs->ttc.clk_rate_change_nb.next = NULL; if (clk_notifier_register(ttccs->ttc.clk, &ttccs->ttc.clk_rate_change_nb)) pr_warn("Unable to register clock notifier.\n"); ttccs->ttc.base_addr = base; ttccs->cs.name = "ttc_clocksource"; ttccs->cs.rating = 200; ttccs->cs.read = __ttc_clocksource_read; ttccs->cs.mask = CLOCKSOURCE_MASK(16); ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS; /* * Setup the clock source counter to be an incrementing counter * with no interrupt and it rolls over at 0xFFFF. Pre-scale * it by 32 also. Let it start running now. */ __raw_writel(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET); __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN, ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET); __raw_writel(CNT_CNTRL_RESET, ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET); err = clocksource_register_hz(&ttccs->cs, clk_get_rate(ttccs->ttc.clk) / PRESCALE); if (WARN_ON(err)) { kfree(ttccs); return; } ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET; setup_sched_clock(ttc_sched_clock_read, 16, clk_get_rate(ttccs->ttc.clk) / PRESCALE); }
static inline void setup_clksrc(void) { struct clocksource *cs = &mt6589_gpt.clocksource; struct gpt_device *dev = id_to_dev(GPT_CLKSRC_ID); cs->mult = clocksource_hz2mult(SYS_CLK_RATE, cs->shift); setup_gpt_dev_locked(dev, GPT_FREE_RUN, GPT_CLK_SRC_SYS, GPT_CLK_DIV_1, 0, NULL, 0); setup_sched_clock((void *)mt_read_sched_clock, 32, SYS_CLK_RATE); }
void __init nmdk_timer_init(void) { unsigned long rate; struct clk *clk0; int ret; clk0 = clk_get_sys("mtu0", NULL); BUG_ON(IS_ERR(clk0)); ret = clk_prepare_enable(clk0); BUG_ON(ret != 0); /* * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz * for ux500. * Use a divide-by-16 counter if the tick rate is more than 32MHz. * At 32 MHz, the timer (with 32 bit counter) can be programmed * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer * with 16 gives too low timer resolution. */ rate = clk_get_rate(clk0); if (rate > 32000000) { rate /= 16; clk_prescale = MTU_CRn_PRESCALE_16; } else { clk_prescale = MTU_CRn_PRESCALE_1; } nmdk_cycle = (rate + HZ/2) / HZ; /* Timer 0 is the free running clocksource */ nmdk_clksrc_reset(); if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0", rate, 200, 32, clocksource_mmio_readl_down)) pr_err("timer: failed to initialize clock source %s\n", "mtu_0"); #ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK setup_sched_clock(nomadik_read_sched_clock, 32, rate); #endif /* Timer 1 is used for events, register irq and clockevents */ setup_irq(IRQ_MTU0, &nmdk_timer_irq); nmdk_clkevt.cpumask = cpumask_of(0); clockevents_config_and_register(&nmdk_clkevt, rate, 2, 0xffffffffU); #ifdef ARCH_HAS_READ_CURRENT_TIMER set_delay_fn(nmdk_timer_delay_loop); #endif }
void __init mtu_timer_init(void) { unsigned long rate; struct clk *clk0; clk0 = clk_get_sys("mtu0", NULL); BUG_ON(IS_ERR(clk0)); rate = clk_get_rate(clk0); clk_enable(clk0); /* * Set scale and timer for sched_clock */ setup_sched_clock(rate); u8500_cycle = (rate + HZ/2) / HZ; /* Save global pointer to mtu, used by functions above */ if (cpu_is_u5500()) { mtu0_base = ioremap(U5500_MTU0_BASE, SZ_4K); } else if (cpu_is_u8500()) { mtu0_base = ioremap(U8500_MTU0_BASE, SZ_4K); } else { ux500_unknown_soc(); } /* Restart clock source */ mtu_clocksource_reset(); /* Now the scheduling clock is ready */ u8500_clksrc.read = u8500_read_timer; u8500_clksrc.mult = clocksource_hz2mult(rate, u8500_clksrc.shift); clocksource_register(&u8500_clksrc); /* Register irq and clockevents */ /* We can sleep for max 10s (actually max is longer) */ clockevents_calc_mult_shift(&u8500_mtu_clkevt, rate, 10); u8500_mtu_clkevt.max_delta_ns = clockevent_delta2ns(0xffffffff, &u8500_mtu_clkevt); u8500_mtu_clkevt.min_delta_ns = clockevent_delta2ns(0xff, &u8500_mtu_clkevt); setup_irq(IRQ_MTU0, &u8500_timer_irq); clockevents_register_device(&u8500_mtu_clkevt); #ifdef ARCH_HAS_READ_CURRENT_TIMER set_delay_fn(mtu_timer_delay_loop); #endif }
static void __init omap_init_clocksource(unsigned long rate) { omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(1); static char err[] __initdata = KERN_ERR "%s: can't register clocksource!\n"; omap_mpu_timer_start(1, ~0, 1); setup_sched_clock(omap_mpu_read_sched_clock, 32, rate); if (clocksource_mmio_init(&timer->read_tim, "mpu_timer2", rate, 300, 32, clocksource_mmio_readl_down)) printk(err, "mpu_timer2"); }
static void __init gt_clocksource_init(void) { writel(0, gt_base + GT_CONTROL); writel(0, gt_base + GT_COUNTER0); writel(0, gt_base + GT_COUNTER1); /* enables timer on all the cores */ writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL); #ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK setup_sched_clock(gt_sched_clock_read, 32, gt_clk_rate); #endif clocksource_register_hz(>_clocksource, gt_clk_rate); }
static void init_sched_clock(void) { struct device_node *sched_timer; sched_timer = of_find_matching_node(NULL, sptimer_ids); if (sched_timer) { timer_get_base_and_rate(sched_timer, &sched_io_base, &sched_rate); of_node_put(sched_timer); } setup_sched_clock(read_sched_clock, 32, sched_rate); }
static void init_sched_clock(void) { struct device_node *sched_timer; u32 rate; sched_timer = of_find_matching_node(NULL, sptimer_ids); if (!sched_timer) panic("No RTC for sched clock to use"); timer_get_base_and_rate(sched_timer, &sched_io_base, &rate); of_node_put(sched_timer); setup_sched_clock(read_sched_clock, 32, rate); }
static void __init sun4i_timer_init(struct device_node *node) { unsigned long rate = 0; struct clk *clk; int ret, irq; u32 val; timer_base = of_iomap(node, 0); if (!timer_base) panic("Can't map registers"); irq = irq_of_parse_and_map(node, 0); if (irq <= 0) panic("Can't parse IRQ"); clk = of_clk_get(node, 0); if (IS_ERR(clk)) panic("Can't get timer clock"); clk_prepare_enable(clk); rate = clk_get_rate(clk); writel(~0, timer_base + TIMER_INTVAL_REG(1)); writel(TIMER_CTL_ENABLE | TIMER_CTL_RELOAD | TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M), timer_base + TIMER_CTL_REG(1)); setup_sched_clock(sun4i_timer_sched_read, 32, rate); clocksource_mmio_init(timer_base + TIMER_CNTVAL_REG(1), node->name, rate, 300, 32, clocksource_mmio_readl_down); ticks_per_jiffy = DIV_ROUND_UP(rate, HZ); writel(TIMER_CTL_CLK_SRC(TIMER_CTL_CLK_SRC_OSC24M), timer_base + TIMER_CTL_REG(0)); ret = setup_irq(irq, &sun4i_timer_irq); if (ret) pr_warn("failed to setup irq %d\n", irq); /* Enable timer0 interrupt */ val = readl(timer_base + TIMER_IRQ_EN_REG); writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG); sun4i_clockevent.cpumask = cpumask_of(0); clockevents_config_and_register(&sun4i_clockevent, rate, TIMER_SYNC_TICKS, 0xffffffff); }
static inline void setup_clksrc(void) { struct clocksource *cs = &mt6582_gpt.clocksource; struct gpt_device *dev = id_to_dev(GPT_CLKSRC_ID); cs->mult = clocksource_hz2mult(SYS_CLK_RATE, cs->shift); setup_gpt_dev_locked(dev, GPT_FREE_RUN, GPT_CLK_SRC_SYS, GPT_CLK_DIV_1, 0, NULL, 0); #if (LINUX_VERSION_CODE < KERNEL_VERSION(3, 7, 0)) setup_sched_clock_needs_suspend((void *)mt_read_sched_clock, 32, SYS_CLK_RATE); #else setup_sched_clock((void *)mt_read_sched_clock, 32, SYS_CLK_RATE); #endif }
void __init timer_init(int irq) { timer_config(); setup_sched_clock(mmp_read_sched_clock, 32, CLOCK_TICK_RATE); ckevt.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt.shift); ckevt.max_delta_ns = clockevent_delta2ns(MAX_DELTA, &ckevt); ckevt.min_delta_ns = clockevent_delta2ns(MIN_DELTA, &ckevt); ckevt.cpumask = cpumask_of(0); setup_irq(irq, &timer_irq); clocksource_register_hz(&cksrc, CLOCK_TICK_RATE); clockevents_register_device(&ckevt); }
void __init sa1100_timer_init(void) { writel_relaxed(0, OIER); writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR); setup_sched_clock(sa1100_read_sched_clock, 32, 3686400); ckevt_sa1100_osmr0.cpumask = cpumask_of(0); setup_irq(IRQ_OST0, &sa1100_timer_irq); clocksource_mmio_init(OSCR, "oscr", CLOCK_TICK_RATE, 200, 32, clocksource_mmio_readl_up); clockevents_config_and_register(&ckevt_sa1100_osmr0, 3686400, MIN_OSCR_DELTA * 2, 0x7fffffff); }
static void __init rps_clocksource_init(void __iomem *base, ulong ref_rate) { int ret; ulong clock_rate; /* use prescale 16 */ clock_rate = ref_rate / 16; iowrite32(TIMER_MAX_VAL, base + TIMER_LOAD); iowrite32(TIMER_PERIODIC | TIMER_ENABLE | TIMER_DIV16, base + TIMER_CTRL); ret = clocksource_mmio_init(base + TIMER_CURR, "rps_clocksource_timer", clock_rate, 250, TIMER_BITS, clocksource_mmio_readl_down); if (ret) panic("can't register clocksource\n"); setup_sched_clock(rps_read_sched_clock, TIMER_BITS, clock_rate); }
void __init pxa_timer_init(void) { unsigned long clock_tick_rate = get_clock_tick_rate(); writel_relaxed(0, OIER); writel_relaxed(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR); setup_sched_clock(pxa_read_sched_clock, 32, clock_tick_rate); ckevt_pxa_osmr0.cpumask = cpumask_of(0); setup_irq(IRQ_OST0, &pxa_ost0_irq); clocksource_mmio_init(OSCR, "oscr0", clock_tick_rate, 200, 32, clocksource_mmio_readl_up); clockevents_config_and_register(&ckevt_pxa_osmr0, clock_tick_rate, MIN_OSCR_DELTA * 2, 0x7fffffff); }